LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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chip_18xx_43xx
chip_clocks.h
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1
/*
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* @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
13
* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
19
* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CHIP_CLOCKS_H_
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#define __CHIP_CLOCKS_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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49
typedef
enum
CHIP_CGU_CLKIN {
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CLKIN_32K
,
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CLKIN_IRC
,
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CLKIN_ENET_RX
,
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CLKIN_ENET_TX
,
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CLKIN_CLKIN
,
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CLKIN_RESERVED1
,
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CLKIN_CRYSTAL
,
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CLKIN_USBPLL
,
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CLKIN_AUDIOPLL
,
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CLKIN_MAINPLL
,
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CLKIN_RESERVED2
,
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CLKIN_RESERVED3
,
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CLKIN_IDIVA
,
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CLKIN_IDIVB
,
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CLKIN_IDIVC
,
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CLKIN_IDIVD
,
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CLKIN_IDIVE
,
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CLKINPUT_PD
68
}
CHIP_CGU_CLKIN_T
;
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typedef
enum
CHIP_CGU_BASE_CLK {
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CLK_BASE_SAFE
,
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CLK_BASE_USB0
,
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#if defined(CHIP_LPC43XX)
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CLK_BASE_PERIPH,
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#else
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CLK_BASE_RESERVED1
,
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#endif
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CLK_BASE_USB1
,
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CLK_BASE_MX
,
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CLK_BASE_SPIFI
,
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#if defined(CHIP_LPC43XX)
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CLK_BASE_SPI,
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#else
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CLK_BASE_RESERVED2
,
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#endif
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CLK_BASE_PHY_RX
,
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CLK_BASE_PHY_TX
,
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CLK_BASE_APB1
,
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CLK_BASE_APB3
,
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CLK_BASE_LCD
,
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#if defined(CHIP_LPC43XX)
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CLK_BASE_ADCHS,
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#else
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CLK_BASE_RESERVED3
,
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#endif
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CLK_BASE_SDIO
,
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CLK_BASE_SSP0
,
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CLK_BASE_SSP1
,
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CLK_BASE_UART0
,
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CLK_BASE_UART1
,
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CLK_BASE_UART2
,
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CLK_BASE_UART3
,
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CLK_BASE_OUT
,
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CLK_BASE_RESERVED4
,
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CLK_BASE_RESERVED5
,
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CLK_BASE_RESERVED6
,
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CLK_BASE_RESERVED7
,
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CLK_BASE_APLL
,
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CLK_BASE_CGU_OUT0
,
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CLK_BASE_CGU_OUT1
,
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CLK_BASE_LAST
,
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CLK_BASE_NONE
=
CLK_BASE_LAST
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}
CHIP_CGU_BASE_CLK_T
;
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typedef
enum
CHIP_CGU_IDIV {
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CLK_IDIV_A
,
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CLK_IDIV_B
,
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CLK_IDIV_C
,
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CLK_IDIV_D
,
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CLK_IDIV_E
,
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CLK_IDIV_LAST
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}
CHIP_CGU_IDIV_T
;
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#define CHIP_CGU_IDIV_MASK(x) ("\x03\x0F\x0F\x0F\xFF"[x])
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typedef
enum
CHIP_CCU_CLK {
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/* CCU1 clocks */
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CLK_APB3_BUS
,
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CLK_APB3_I2C1
,
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CLK_APB3_DAC
,
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CLK_APB3_ADC0
,
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CLK_APB3_ADC1
,
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CLK_APB3_CAN0
,
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CLK_APB1_BUS
= 32,
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CLK_APB1_MOTOCON
,
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CLK_APB1_I2C0
,
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CLK_APB1_I2S
,
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CLK_APB1_CAN1
,
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CLK_SPIFI
= 64,
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CLK_MX_BUS
= 96,
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CLK_MX_SPIFI
,
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CLK_MX_GPIO
,
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CLK_MX_LCD
,
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CLK_MX_ETHERNET
,
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CLK_MX_USB0
,
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CLK_MX_EMC
,
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CLK_MX_SDIO
,
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CLK_MX_DMA
,
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CLK_MX_MXCORE
,
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RESERVED_ALIGN
=
CLK_MX_MXCORE
+ 3,
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CLK_MX_SCT
,
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CLK_MX_USB1
,
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CLK_MX_EMC_DIV
,
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CLK_MX_FLASHA
,
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CLK_MX_FLASHB
,
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#if defined(CHIP_LPC43XX)
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CLK_M4_M0APP,
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CLK_MX_ADCHS,
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#else
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CLK_RESERVED1
,
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CLK_RESERVED2
,
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#endif
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CLK_MX_EEPROM
,
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CLK_MX_WWDT
= 128,
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CLK_MX_UART0
,
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CLK_MX_UART1
,
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CLK_MX_SSP0
,
191
CLK_MX_TIMER0
,
192
CLK_MX_TIMER1
,
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CLK_MX_SCU
,
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CLK_MX_CREG
,
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CLK_MX_RITIMER
= 160,
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CLK_MX_UART2
,
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CLK_MX_UART3
,
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CLK_MX_TIMER2
,
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CLK_MX_TIMER3
,
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CLK_MX_SSP1
,
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CLK_MX_QEI
,
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#if defined(CHIP_LPC43XX)
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CLK_PERIPH_BUS = 192,
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CLK_RESERVED3
,
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CLK_PERIPH_CORE,
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CLK_PERIPH_SGPIO,
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#else
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CLK_RESERVED3
= 192,
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CLK_RESERVED3A
,
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CLK_RESERVED4
,
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CLK_RESERVED5
,
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#endif
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CLK_USB0
= 224,
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CLK_USB1
= 256,
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#if defined(CHIP_LPC43XX)
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CLK_SPI = 288,
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CLK_ADCHS = 320,
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#else
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CLK_RESERVED7
= 320,
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CLK_RESERVED8
,
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#endif
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CLK_CCU1_LAST
,
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/* CCU2 clocks */
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CLK_CCU2_START
,
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CLK_APLL
=
CLK_CCU2_START
,
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RESERVED_ALIGNB
=
CLK_CCU2_START
+ 31,
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CLK_APB2_UART3
,
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RESERVED_ALIGNC
=
CLK_CCU2_START
+ 63,
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CLK_APB2_UART2
,
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RESERVED_ALIGND
=
CLK_CCU2_START
+ 95,
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CLK_APB0_UART1
,
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RESERVED_ALIGNE
=
CLK_CCU2_START
+ 127,
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CLK_APB0_UART0
,
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RESERVED_ALIGNF
=
CLK_CCU2_START
+ 159,
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CLK_APB2_SSP1
,
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RESERVED_ALIGNG
=
CLK_CCU2_START
+ 191,
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CLK_APB0_SSP0
,
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RESERVED_ALIGNH
=
CLK_CCU2_START
+ 223,
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CLK_APB2_SDIO
,
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CLK_CCU2_LAST
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}
CHIP_CCU_CLK_T
;
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __CHIP_CLOCKS_H_ */
Generated on Fri Feb 20 2015 21:29:41 for LPCOpen Platform for LPC18XX/43XX microcontrollers by
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