LPCOpen Platform for LPC18XX/43XX microcontrollers: CHIP: LPC18xx/43xx General Purpose DMA driver

| LPCOpen Platform for LPC18XX/43XX microcontrollers 18XX43XX LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers

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Data Structures | Macros | Enumerations | Functions
CHIP: LPC18xx/43xx General Purpose DMA driver
LPC18xx/43xx chip specific drivers

## Detailed Description

## Data Structures
struct | GPDMA_CH_T
| GPDMA Channel register block structure. More...
struct | LPC_GPDMA_T
| GPDMA register block. More...
struct | GPDMA_CH_CFG_T
| GPDMA structure using for DMA configuration. More...
struct | DMA_ChannelHandle_t
| DMA channel handle structure. More...
struct | DMA_TransferDescriptor_t
| Transfer Descriptor structure typedef. More...

## Macros
#define | GPDMA_NUMBER_CHANNELS 8
| Number of channels on GPDMA. More...
#define | GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0))
| Macro defines for DMA channel control registers. More...
#define | GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12))
#define | GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15))
#define | GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18))
#define | GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21))
#define | GPDMA_DMACCxControl_SI ((1UL << 26))
#define | GPDMA_DMACCxControl_DI ((1UL << 27))
#define | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24))
#define | GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25))
#define | GPDMA_DMACCxControl_Prot1 ((1UL << 28))
#define | GPDMA_DMACCxControl_Prot2 ((1UL << 29))
#define | GPDMA_DMACCxControl_Prot3 ((1UL << 30))
#define | GPDMA_DMACCxControl_I ((1UL << 31))
#define | GPDMA_DMACConfig_E ((0x01))
| Macro defines for DMA Configuration register. More...
#define | GPDMA_DMACConfig_M ((0x02))
#define | GPDMA_DMACConfig_BITMASK ((0x03))
#define | GPDMA_DMACCxConfig_E ((1UL << 0))
| Macro defines for DMA Channel Configuration registers. More...
#define | GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1))
#define | GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6))
#define | GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11))
#define | GPDMA_DMACCxConfig_IE ((1UL << 14))
#define | GPDMA_DMACCxConfig_ITC ((1UL << 15))
#define | GPDMA_DMACCxConfig_L ((1UL << 16))
#define | GPDMA_DMACCxConfig_A ((1UL << 17))
#define | GPDMA_DMACCxConfig_H ((1UL << 18))
#define | GPDMA_CONN_MEMORY ((0UL))
| GPDMA request connections. More...
#define | GPDMA_CONN_MAT0_0 ((1UL))
#define | GPDMA_CONN_UART0_Tx ((2UL))
#define | GPDMA_CONN_MAT0_1 ((3UL))
#define | GPDMA_CONN_UART0_Rx ((4UL))
#define | GPDMA_CONN_MAT1_0 ((5UL))
#define | GPDMA_CONN_UART1_Tx ((6UL))
#define | GPDMA_CONN_MAT1_1 ((7UL))
#define | GPDMA_CONN_UART1_Rx ((8UL))
#define | GPDMA_CONN_MAT2_0 ((9UL))
#define | GPDMA_CONN_UART2_Tx ((10UL))
#define | GPDMA_CONN_MAT2_1 ((11UL))
#define | GPDMA_CONN_UART2_Rx ((12UL))
#define | GPDMA_CONN_MAT3_0 ((13UL))
#define | GPDMA_CONN_UART3_Tx ((14UL))
#define | GPDMA_CONN_SCT_0 ((15UL))
#define | GPDMA_CONN_MAT3_1 ((16UL))
#define | GPDMA_CONN_UART3_Rx ((17UL))
#define | GPDMA_CONN_SCT_1 ((18UL))
#define | GPDMA_CONN_SSP0_Rx ((19UL))
#define | GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))
#define | GPDMA_CONN_SSP0_Tx ((21UL))
#define | GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))
#define | GPDMA_CONN_SSP1_Rx ((23UL))
#define | GPDMA_CONN_SSP1_Tx ((24UL))
#define | GPDMA_CONN_ADC_0 ((25UL))
#define | GPDMA_CONN_ADC_1 ((26UL))
#define | GPDMA_CONN_DAC ((27UL))
#define | GPDMA_CONN_I2S1_Tx_Channel_0 ((28UL))
#define | GPDMA_CONN_I2S1_Rx_Channel_1 ((29UL))
#define | GPDMA_BSIZE_1 ((0UL))
| GPDMA Burst size in Source and Destination definitions. More...
#define | GPDMA_BSIZE_4 ((1UL))
#define | GPDMA_BSIZE_8 ((2UL))
#define | GPDMA_BSIZE_16 ((3UL))
#define | GPDMA_BSIZE_32 ((4UL))
#define | GPDMA_BSIZE_64 ((5UL))
#define | GPDMA_BSIZE_128 ((6UL))
#define | GPDMA_BSIZE_256 ((7UL))
#define | GPDMA_WIDTH_BYTE ((0UL))
| Width in Source transfer width and Destination transfer width definitions. More...
#define | GPDMA_WIDTH_HALFWORD ((1UL))
#define | GPDMA_WIDTH_WORD ((2UL))
#define | DMA_CONTROLLER 0
| Flow control definitions. More...
#define | SRC_PER_CONTROLLER 1
#define | DST_PER_CONTROLLER 2

## Enumerations
enum | GPDMA_STATECLEAR_T { GPDMA_STATCLR_INTTC, GPDMA_STATCLR_INTERR }
| GPDMA Interrupt Clear Status. More...
enum | GPDMA_STATUS_T { GPDMA_STAT_INT, GPDMA_STAT_INTTC, GPDMA_STAT_INTERR, GPDMA_STAT_RAWINTTC, GPDMA_STAT_RAWINTERR, GPDMA_STAT_ENABLED_CH }
| GPDMA Type of Interrupt Status. More...
enum | GPDMA_FLOW_CONTROL_T { GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) }
| GPDMA Type of DMA controller. More...

## Functions
void | Chip_GPDMA_Init (LPC_GPDMA_T *pGPDMA)
| Initialize the GPDMA. More...
void | Chip_GPDMA_DeInit (LPC_GPDMA_T *pGPDMA)
| Shutdown the GPDMA. More...
int | Chip_GPDMA_InitChannelCfg (LPC_GPDMA_T *pGPDMA, GPDMA_CH_CFG_T *GPDMACfg, uint8_t ChannelNum, uint32_t src, uint32_t dst, uint32_t Size, GPDMA_FLOW_CONTROL_T TransferType)
| Initialize channel configuration strucutre. More...
void | Chip_GPDMA_ChannelCmd (LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState)
| Enable or Disable the GPDMA Channel. More...
void | Chip_GPDMA_Stop (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum)
| Stop a stream DMA transfer. More...
Status | Chip_GPDMA_Interrupt (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum)
| The GPDMA stream interrupt status checking. More...
IntStatus | Chip_GPDMA_IntGetStatus (LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel)
| Read the status from different registers according to the type. More...
void | Chip_GPDMA_ClearIntPending (LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel)
| Clear the Interrupt Flag from different registers according to the type. More...
uint8_t | Chip_GPDMA_GetFreeChannel (LPC_GPDMA_T *pGPDMA, uint32_t PeripheralConnection_ID)
| Get a free GPDMA channel for one DMA connection. More...
Status | Chip_GPDMA_Transfer (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum, uint32_t src, uint32_t dst, GPDMA_FLOW_CONTROL_T TransferType, uint32_t Size)
| Do a DMA transfer M2M, M2P,P2M or P2P. More...
Status | Chip_GPDMA_SGTransfer (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum, const DMA_TransferDescriptor_t *DMADescriptor, GPDMA_FLOW_CONTROL_T TransferType)
| Do a DMA transfer using linked list of descriptors. More...
Status | Chip_GPDMA_PrepareDescriptor (LPC_GPDMA_T *pGPDMA, DMA_TransferDescriptor_t *DMADescriptor, uint32_t src, uint32_t dst, uint32_t Size, GPDMA_FLOW_CONTROL_T TransferType, const DMA_TransferDescriptor_t *NextDescriptor)
| Prepare a single DMA descriptor. More...

## Macro Definition Documentation

#define DMA_CONTROLLER 0

Flow control definitions.

Flow control is DMA controller

Definition at line 233 of file gpdma_18xx_43xx.h.

#define DST_PER_CONTROLLER 2

Flow control is Destination peripheral controller

Definition at line 235 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_1 ((0UL))

GPDMA Burst size in Source and Destination definitions.

Burst size = 1

Definition at line 214 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_128 ((6UL))

Burst size = 128

Definition at line 220 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_16 ((3UL))

Burst size = 16

Definition at line 217 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_256 ((7UL))

Burst size = 256

Definition at line 221 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_32 ((4UL))

Burst size = 32

Definition at line 218 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_4 ((1UL))

Burst size = 4

Definition at line 215 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_64 ((5UL))

Burst size = 64

Definition at line 219 of file gpdma_18xx_43xx.h.

#define GPDMA_BSIZE_8 ((2UL))

Burst size = 8

Definition at line 216 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_ADC_0 ((25UL))

ADC 0

Definition at line 205 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_ADC_1 ((26UL))

ADC 1

Definition at line 206 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_DAC ((27UL))

DAC

Definition at line 207 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S1_Rx_Channel_1 ((29UL))

I2S1 Rx on channel 0

Definition at line 209 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S1_Tx_Channel_0 ((28UL))

I2S1 Tx on channel 0

Definition at line 208 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))

I2S0 Rx on channel 0

Definition at line 202 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))

I2S0 Tx on channel 0

Definition at line 200 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT0_0 ((1UL))

MAT0.0

Definition at line 181 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT0_1 ((3UL))

MAT0.1

Definition at line 183 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT1_0 ((5UL))

MAT1.0

Definition at line 185 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT1_1 ((7UL))

MAT1.1

Definition at line 187 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT2_0 ((9UL))

MAT2.0

Definition at line 189 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT2_1 ((11UL))

MAT2.1

Definition at line 191 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT3_0 ((13UL))

MAT3.0

Definition at line 193 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MAT3_1 ((16UL))

MAT3.1

Definition at line 196 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_MEMORY ((0UL))

GPDMA request connections.

MEMORY

Definition at line 180 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SCT_0 ((15UL))

SCT timer channel 0

Definition at line 195 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SCT_1 ((18UL))

SCT timer channel 1

Definition at line 198 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP0_Rx ((19UL))

SSP0 Rx

Definition at line 199 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP0_Tx ((21UL))

SSP0 Tx

Definition at line 201 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP1_Rx ((23UL))

SSP1 Rx

Definition at line 203 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_SSP1_Tx ((24UL))

SSP1 Tx

Definition at line 204 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART0_Rx ((4UL))

UART0 Rx

Definition at line 184 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART0_Tx ((2UL))

UART0 Tx

Definition at line 182 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART1_Rx ((8UL))

UART1 Rx

Definition at line 188 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART1_Tx ((6UL))

UART1 Tx

Definition at line 186 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART2_Rx ((12UL))

UART2 Rx

Definition at line 192 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART2_Tx ((10UL))

UART2 Tx

Definition at line 190 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART3_Rx ((17UL))

UART3 Rx

Definition at line 197 of file gpdma_18xx_43xx.h.

#define GPDMA_CONN_UART3_Tx ((14UL))

UART3 Tx

Definition at line 194 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACConfig_BITMASK ((0x03))

Definition at line 105 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACConfig_E ((0x01))

Macro defines for DMA Configuration register.

DMA Controller enable

Definition at line 103 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACConfig_M ((0x02))

AHB Master endianness configuration

Definition at line 104 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_A ((1UL << 17))

Active

Definition at line 117 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_DestPeripheral | ( |  | n | ) | (((n & 0x1F) << 6))

Destination peripheral

Definition at line 112 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_E ((1UL << 0))

Macro defines for DMA Channel Configuration registers.

DMA control enable

Definition at line 110 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_H ((1UL << 18))

Halt

Definition at line 118 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_IE ((1UL << 14))

Interrupt error mask

Definition at line 114 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_ITC ((1UL << 15))

Terminal count interrupt mask

Definition at line 115 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_L ((1UL << 16))

Lock

Definition at line 116 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_SrcPeripheral | ( |  | n | ) | (((n & 0x1F) << 1))

Source peripheral

Definition at line 111 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxConfig_TransferType | ( |  | n | ) | (((n & 0x7) << 11))

This value indicates the type of transfer

Definition at line 113 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_DBSize | ( |  | n | ) | (((n & 0x07) << 15))

Destination burst size

Definition at line 88 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25))

Destination AHB master select in 18xx43xx

Definition at line 94 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_DI ((1UL << 27))

Destination increment

Definition at line 92 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_DWidth | ( |  | n | ) | (((n & 0x07) << 21))

Destination transfer width

Definition at line 90 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_I ((1UL << 31))

Terminal count interrupt enable bit

Definition at line 98 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_Prot1 ((1UL << 28))

Indicates that the access is in user mode or privileged mode

Definition at line 95 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_Prot2 ((1UL << 29))

Indicates that the access is bufferable or not bufferable

Definition at line 96 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_Prot3 ((1UL << 30))

Indicates that the access is cacheable or not cacheable

Definition at line 97 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_SBSize | ( |  | n | ) | (((n & 0x07) << 12))

Source burst size

Definition at line 87 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_SI ((1UL << 26))

Source increment

Definition at line 91 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24))

Source AHB master select in 18xx43xx

Definition at line 93 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_SWidth | ( |  | n | ) | (((n & 0x07) << 18))

Source transfer width

Definition at line 89 of file gpdma_18xx_43xx.h.

#define GPDMA_DMACCxControl_TransferSize | ( |  | n | ) | (((n & 0xFFF) << 0))

Macro defines for DMA channel control registers.

Transfer size

Definition at line 86 of file gpdma_18xx_43xx.h.

#define GPDMA_NUMBER_CHANNELS 8

Number of channels on GPDMA.

Definition at line 47 of file gpdma_18xx_43xx.h.

#define GPDMA_WIDTH_BYTE ((0UL))

Width in Source transfer width and Destination transfer width definitions.

Width = 1 byte

Definition at line 226 of file gpdma_18xx_43xx.h.

#define GPDMA_WIDTH_HALFWORD ((1UL))

Width = 2 bytes

Definition at line 227 of file gpdma_18xx_43xx.h.

#define GPDMA_WIDTH_WORD ((2UL))

Width = 4 bytes

Definition at line 228 of file gpdma_18xx_43xx.h.

#define SRC_PER_CONTROLLER 1

Flow control is Source peripheral controller

Definition at line 234 of file gpdma_18xx_43xx.h.

## Enumeration Type Documentation

enum GPDMA_FLOW_CONTROL_T

GPDMA Type of DMA controller.

Enumerator
GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA | Memory to memory - DMA control
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA | Memory to peripheral - DMA control
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA | Peripheral to memory - DMA control
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA | Source peripheral to destination peripheral - DMA control
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL | Source peripheral to destination peripheral - destination peripheral control
GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL | Memory to peripheral - peripheral control
GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL | Peripheral to memory - peripheral control
GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL | Source peripheral to destination peripheral - source peripheral control

Definition at line 143 of file gpdma_18xx_43xx.h.

enum GPDMA_STATECLEAR_T

GPDMA Interrupt Clear Status.

Enumerator
GPDMA_STATCLR_INTTC | GPDMA Interrupt Terminal Count Request Clear
GPDMA_STATCLR_INTERR | GPDMA Interrupt Error Clear

Definition at line 123 of file gpdma_18xx_43xx.h.

enum GPDMA_STATUS_T

GPDMA Type of Interrupt Status.

Enumerator
GPDMA_STAT_INT | GPDMA Interrupt Status
GPDMA_STAT_INTTC | GPDMA Interrupt Terminal Count Request Status
GPDMA_STAT_INTERR | GPDMA Interrupt Error Status
GPDMA_STAT_RAWINTTC | GPDMA Raw Interrupt Terminal Count Status
GPDMA_STAT_RAWINTERR | GPDMA Raw Error Interrupt Status
GPDMA_STAT_ENABLED_CH | GPDMA Enabled Channel Status

Definition at line 131 of file gpdma_18xx_43xx.h.

## Function Documentation

void Chip_GPDMA_ChannelCmd | ( | LPC_GPDMA_T * | pGPDMA,
|  | uint8_t | channelNum,
|  | FunctionalState | NewState
| ) |  |

Enable or Disable the GPDMA Channel.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  channelNum | : The GPDMA channel : 0 - 7
  NewState | : ENABLE to enable GPDMA or DISABLE to disable GPDMA

Returns
  Nothing

Definition at line 587 of file gpdma_18xx_43xx.c.

void Chip_GPDMA_ClearIntPending | ( | LPC_GPDMA_T * | pGPDMA,
|  | GPDMA_STATECLEAR_T | type,
|  | uint8_t | channel
| ) |  |

Clear the Interrupt Flag from different registers according to the type.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  type | : Flag mode, should be: GPDMA_STATCLR_INTTC : GPDMA Interrupt Terminal Count Request GPDMA_STATCLR_INTERR : GPDMA Interrupt Error
  channel | : The GPDMA channel : 0 - 7

Returns
  Nothing

Definition at line 574 of file gpdma_18xx_43xx.c.

void Chip_GPDMA_DeInit | ( | LPC_GPDMA_T * | pGPDMA | ) |

Shutdown the GPDMA.

Parameters

  pGPDMA | : The base of GPDMA on the chip

Returns
  Nothing

Definition at line 452 of file gpdma_18xx_43xx.c.

uint8_t Chip_GPDMA_GetFreeChannel | ( | LPC_GPDMA_T * | pGPDMA,
|  | uint32_t | PeripheralConnection_ID
| ) |  |

Get a free GPDMA channel for one DMA connection.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  PeripheralConnection_ID | : Some chip fix each peripheral DMA connection on a specified channel ( have not used in 17xx/40xx )

Returns
  The channel number which is selected

Definition at line 733 of file gpdma_18xx_43xx.c.

void Chip_GPDMA_Init | ( | LPC_GPDMA_T * | pGPDMA | ) |

Initialize the GPDMA.

Parameters

  pGPDMA | : The base of GPDMA on the chip

Returns
  Nothing

Definition at line 430 of file gpdma_18xx_43xx.c.

int Chip_GPDMA_InitChannelCfg | ( | LPC_GPDMA_T * | pGPDMA,
|  | GPDMA_CH_CFG_T * | GPDMACfg,
|  | uint8_t | ChannelNum,
|  | uint32_t | src,
|  | uint32_t | dst,
|  | uint32_t | Size,
|  | GPDMA_FLOW_CONTROL_T | TransferType
| ) |  |

Initialize channel configuration strucutre.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  GPDMACfg | : Pointer to configuration structure to be initialized
  ChannelNum | : Channel used for transfer must be obtained using Chip_GPDMA_GetFreeChannel()
  src | : Address of Memory or one of PeripheralConnection_ID , which is the source
  dst | : Address of Memory or one of PeripheralConnection_ID , which is the destination
  Size | : The number of DMA transfers
  TransferType | : Select the transfer controller and the type of transfer. (See, GPDMA_FLOW_CONTROL_T)

Returns
  ERROR on error, SUCCESS on success

Definition at line 496 of file gpdma_18xx_43xx.c.

Status Chip_GPDMA_Interrupt | ( | LPC_GPDMA_T * | pGPDMA,
|  | uint8_t | ChannelNum
| ) |  |

The GPDMA stream interrupt status checking.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  ChannelNum | : Channel Number to be checked on interruption

Returns
  Status:
  - SUCCESS : DMA transfer success
  - ERROR : DMA transfer failed

Definition at line 474 of file gpdma_18xx_43xx.c.

IntStatus Chip_GPDMA_IntGetStatus | ( | LPC_GPDMA_T * | pGPDMA,
|  | GPDMA_STATUS_T | type,
|  | uint8_t | channel
| ) |  |

Read the status from different registers according to the type.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  type | : Status mode, should be: GPDMA_STAT_INT : GPDMA Interrupt Status GPDMA_STAT_INTTC : GPDMA Interrupt Terminal Count Request Status GPDMA_STAT_INTERR : GPDMA Interrupt Error Status GPDMA_STAT_RAWINTTC : GPDMA Raw Interrupt Terminal Count Status GPDMA_STAT_RAWINTERR : GPDMA Raw Error Interrupt Status GPDMA_STAT_ENABLED_CH : GPDMA Enabled Channel Status
  channel | : The GPDMA channel : 0 - 7

Returns
  SET is interrupt is pending or RESET if not pending

TODO check the channel <=8 type is exited

Definition at line 547 of file gpdma_18xx_43xx.c.

Status Chip_GPDMA_PrepareDescriptor | ( | LPC_GPDMA_T * | pGPDMA,
|  | DMA_TransferDescriptor_t * | DMADescriptor,
|  | uint32_t | src,
|  | uint32_t | dst,
|  | uint32_t | Size,
|  | GPDMA_FLOW_CONTROL_T | TransferType,
|  | const DMA_TransferDescriptor_t * | NextDescriptor
| ) |  |

Prepare a single DMA descriptor.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  DMADescriptor | : DMA Descriptor to be initialized
  src | : Address of Memory or one of PeripheralConnection_ID , which is the source
  dst | : Address of Memory or one of PeripheralConnection_ID , which is the destination
  Size | : The number of DMA transfers
  TransferType | : Select the transfer controller and the type of transfer. (See, GPDMA_FLOW_CONTROL_T)
  NextDescriptor | : Pointer to next descriptor (0 if no more descriptors available)

Returns
  ERROR on error, SUCCESS on success

Definition at line 649 of file gpdma_18xx_43xx.c.

Status Chip_GPDMA_SGTransfer | ( | LPC_GPDMA_T * | pGPDMA,
|  | uint8_t | ChannelNum,
|  | const DMA_TransferDescriptor_t * | DMADescriptor,
|  | GPDMA_FLOW_CONTROL_T | TransferType
| ) |  |

Do a DMA transfer using linked list of descriptors.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  ChannelNum | : Channel used for transfer must be obtained using Chip_GPDMA_GetFreeChannel()
  DMADescriptor | : First node in the linked list of descriptors
  TransferType | : Select the transfer controller and the type of transfer. (See, GPDMA_FLOW_CONTROL_T)

Returns
  ERROR on error, SUCCESS on success

Definition at line 692 of file gpdma_18xx_43xx.c.

void Chip_GPDMA_Stop | ( | LPC_GPDMA_T * | pGPDMA,
|  | uint8_t | ChannelNum
| ) |  |

Stop a stream DMA transfer.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  ChannelNum | : Channel Number to be closed

Returns
  Nothing

Definition at line 458 of file gpdma_18xx_43xx.c.

Status Chip_GPDMA_Transfer | ( | LPC_GPDMA_T * | pGPDMA,
|  | uint8_t | ChannelNum,
|  | uint32_t | src,
|  | uint32_t | dst,
|  | GPDMA_FLOW_CONTROL_T | TransferType,
|  | uint32_t | Size
| ) |  |

Do a DMA transfer M2M, M2P,P2M or P2P.

Parameters

  pGPDMA | : The base of GPDMA on the chip
  ChannelNum | : Channel used for transfer
  src | : Address of Memory or PeripheralConnection_ID which is the source
  dst | : Address of Memory or PeripheralConnection_ID which is the destination
  TransferType,: | Select the transfer controller and the type of transfer. Should be: GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL
  Size | : The number of DMA transfers

Returns
  ERROR on error, SUCCESS on success

Definition at line 603 of file gpdma_18xx_43xx.c.