LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/chip_18xx_43xx.c Source File

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chip_18xx_43xx.c
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1 /*
2 * @brief LPC18xx/LPC43xx chip driver source
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licenser disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #include "chip.h"
33
34 /*****************************************************************************
35 * Private types/enumerations/variables
36 ****************************************************************************/
37 /* USB PLL pre-initialized setup values for 480MHz output rate */
38 static const CGU_USBAUDIO_PLL_SETUP_T usbPLLSetup = {
39 0x0000601D, /* Default control with main osc input, PLL disabled */
40 0x06167FFA, /* M-divider value for 480MHz output from 12MHz input */
41 0x00000000, /* N-divider value */
42 0x00000000, /* Not applicable for USB PLL */
43 480000000 /* PLL output frequency */
44 };
45
46 /*****************************************************************************
47 * Public types/enumerations/variables
48 ****************************************************************************/
49 /* System Clock Frequency (Core Clock) */
50 uint32_t SystemCoreClock;
51
52 /*****************************************************************************
53 * Private functions
54 ****************************************************************************/
55
56 static void Chip_USB_PllSetup(void)
57 {
58 /* No need to setup anything if PLL is already setup for the frequency */
59 if (Chip_Clock_GetClockInputHz(CLKIN_USBPLL) == usbPLLSetup.freq)
60 return ;
61
62 /* Setup default USB PLL state for a 480MHz output and attach */
63 Chip_Clock_SetupPLL(CLKIN_CRYSTAL, CGU_USB_PLL, &usbPLLSetup);
64
65 /* enable USB PLL */
66 Chip_Clock_EnablePLL(CGU_USB_PLL);
67
68 /* Wait for PLL lock */
69 while (!(Chip_Clock_GetPLLStatus(CGU_USB_PLL) & CGU_PLL_LOCKED)) {}
70 }
71
72 /*****************************************************************************
73 * Public functions
74 ****************************************************************************/
75
76 void Chip_USB0_Init(void)
77 {
78 /* Set up USB PLL */
79 Chip_USB_PllSetup();
80
81 /* Setup USB0 base clock as clock out from USB PLL */
82 Chip_Clock_SetBaseClock( CLK_BASE_USB0, CLKIN_USBPLL, true, true);
83
84 /* enable USB main clock */
85 Chip_Clock_EnableBaseClock(CLK_BASE_USB0);
86 Chip_Clock_EnableOpts(CLK_MX_USB0, true, true, 1);
87 /* enable USB0 phy */
88 Chip_CREG_EnableUSB0Phy();
89 }
90
91 void Chip_USB1_Init(void)
92 {
93 /* Setup and enable the PLL */
94 Chip_USB_PllSetup();
95
96 /* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
97 chained to make a divide by 8 function. Connect the output of
98 divider D to the USB1 base clock. */
99 Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 4);
100 Chip_Clock_SetDivider(CLK_IDIV_D, CLKIN_IDIVA, 2);
101 Chip_Clock_SetBaseClock(CLK_BASE_USB1, CLKIN_IDIVD, true, true);
102
103 /* enable USB main clock */
104 Chip_Clock_EnableBaseClock(CLK_BASE_USB1);
105 Chip_Clock_EnableOpts(CLK_MX_USB1, true, true, 1);
106 /* enable USB1_DP and USB1_DN on chip FS phy.*/
107 LPC_SCU->SFSUSB = 0x12;
108 }
109
110
111 /* Update system core clock rate, should be called if the system has
112 a clock rate change */
113 void SystemCoreClockUpdate(void)
114 {
115 /* CPU core speed */
116 SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
117 }