LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
gpdma_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx General Purpose DMA driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __GPDMA_18XX_43XX_H_
33 #define __GPDMA_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 #define GPDMA_NUMBER_CHANNELS 8
48 
52 typedef struct {
53  __IO uint32_t SRCADDR;
54  __IO uint32_t DESTADDR;
55  __IO uint32_t LLI;
56  __IO uint32_t CONTROL;
57  __IO uint32_t CONFIG;
58  __I uint32_t RESERVED1[3];
59 } GPDMA_CH_T;
60 
64 typedef struct {
65  __I uint32_t INTSTAT;
66  __I uint32_t INTTCSTAT;
67  __O uint32_t INTTCCLEAR;
68  __I uint32_t INTERRSTAT;
69  __O uint32_t INTERRCLR;
70  __I uint32_t RAWINTTCSTAT;
71  __I uint32_t RAWINTERRSTAT;
72  __I uint32_t ENBLDCHNS;
73  __IO uint32_t SOFTBREQ;
74  __IO uint32_t SOFTSREQ;
75  __IO uint32_t SOFTLBREQ;
76  __IO uint32_t SOFTLSREQ;
77  __IO uint32_t CONFIG;
78  __IO uint32_t SYNC;
79  __I uint32_t RESERVED0[50];
81 } LPC_GPDMA_T;
82 
86 #define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0))
87 #define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12))
88 #define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15))
89 #define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18))
90 #define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21))
91 #define GPDMA_DMACCxControl_SI ((1UL << 26))
92 #define GPDMA_DMACCxControl_DI ((1UL << 27))
93 #define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24))
94 #define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25))
95 #define GPDMA_DMACCxControl_Prot1 ((1UL << 28))
96 #define GPDMA_DMACCxControl_Prot2 ((1UL << 29))
97 #define GPDMA_DMACCxControl_Prot3 ((1UL << 30))
98 #define GPDMA_DMACCxControl_I ((1UL << 31))
103 #define GPDMA_DMACConfig_E ((0x01))
104 #define GPDMA_DMACConfig_M ((0x02))
105 #define GPDMA_DMACConfig_BITMASK ((0x03))
106 
110 #define GPDMA_DMACCxConfig_E ((1UL << 0))
111 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1))
112 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6))
113 #define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11))
114 #define GPDMA_DMACCxConfig_IE ((1UL << 14))
115 #define GPDMA_DMACCxConfig_ITC ((1UL << 15))
116 #define GPDMA_DMACCxConfig_L ((1UL << 16))
117 #define GPDMA_DMACCxConfig_A ((1UL << 17))
118 #define GPDMA_DMACCxConfig_H ((1UL << 18))
123 typedef enum {
127 
131 typedef enum {
139 
143 typedef enum {
153 
157 typedef struct {
158  uint32_t ChannelNum;
163  uint32_t TransferSize;
164  uint32_t TransferWidth;
165  uint32_t SrcAddr;
167  uint32_t DstAddr;
169  uint32_t TransferType;
176 
180 #define GPDMA_CONN_MEMORY ((0UL))
181 #define GPDMA_CONN_MAT0_0 ((1UL))
182 #define GPDMA_CONN_UART0_Tx ((2UL))
183 #define GPDMA_CONN_MAT0_1 ((3UL))
184 #define GPDMA_CONN_UART0_Rx ((4UL))
185 #define GPDMA_CONN_MAT1_0 ((5UL))
186 #define GPDMA_CONN_UART1_Tx ((6UL))
187 #define GPDMA_CONN_MAT1_1 ((7UL))
188 #define GPDMA_CONN_UART1_Rx ((8UL))
189 #define GPDMA_CONN_MAT2_0 ((9UL))
190 #define GPDMA_CONN_UART2_Tx ((10UL))
191 #define GPDMA_CONN_MAT2_1 ((11UL))
192 #define GPDMA_CONN_UART2_Rx ((12UL))
193 #define GPDMA_CONN_MAT3_0 ((13UL))
194 #define GPDMA_CONN_UART3_Tx ((14UL))
195 #define GPDMA_CONN_SCT_0 ((15UL))
196 #define GPDMA_CONN_MAT3_1 ((16UL))
197 #define GPDMA_CONN_UART3_Rx ((17UL))
198 #define GPDMA_CONN_SCT_1 ((18UL))
199 #define GPDMA_CONN_SSP0_Rx ((19UL))
200 #define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))
201 #define GPDMA_CONN_SSP0_Tx ((21UL))
202 #define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))
203 #define GPDMA_CONN_SSP1_Rx ((23UL))
204 #define GPDMA_CONN_SSP1_Tx ((24UL))
205 #define GPDMA_CONN_ADC_0 ((25UL))
206 #define GPDMA_CONN_ADC_1 ((26UL))
207 #define GPDMA_CONN_DAC ((27UL))
208 #define GPDMA_CONN_I2S1_Tx_Channel_0 ((28UL))
209 #define GPDMA_CONN_I2S1_Rx_Channel_1 ((29UL))
214 #define GPDMA_BSIZE_1 ((0UL))
215 #define GPDMA_BSIZE_4 ((1UL))
216 #define GPDMA_BSIZE_8 ((2UL))
217 #define GPDMA_BSIZE_16 ((3UL))
218 #define GPDMA_BSIZE_32 ((4UL))
219 #define GPDMA_BSIZE_64 ((5UL))
220 #define GPDMA_BSIZE_128 ((6UL))
221 #define GPDMA_BSIZE_256 ((7UL))
226 #define GPDMA_WIDTH_BYTE ((0UL))
227 #define GPDMA_WIDTH_HALFWORD ((1UL))
228 #define GPDMA_WIDTH_WORD ((2UL))
233 #define DMA_CONTROLLER 0
234 #define SRC_PER_CONTROLLER 1
235 #define DST_PER_CONTROLLER 2
240 typedef struct {
243 
247 typedef struct DMA_TransferDescriptor {
248  uint32_t src;
249  uint32_t dst;
250  uint32_t lli;
251  uint32_t ctrl;
253 
259 void Chip_GPDMA_Init(LPC_GPDMA_T *pGPDMA);
260 
266 void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA);
267 
282  GPDMA_CH_CFG_T *GPDMACfg,
283  uint8_t ChannelNum,
284  uint32_t src,
285  uint32_t dst,
286  uint32_t Size,
287  GPDMA_FLOW_CONTROL_T TransferType);
288 
296 void Chip_GPDMA_ChannelCmd(LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState);
297 
304 void Chip_GPDMA_Stop(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
305 
314 Status Chip_GPDMA_Interrupt(LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum);
315 
329 IntStatus Chip_GPDMA_IntGetStatus(LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel);
330 
340 void Chip_GPDMA_ClearIntPending(LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel);
341 
348 uint8_t Chip_GPDMA_GetFreeChannel(LPC_GPDMA_T *pGPDMA,
349  uint32_t PeripheralConnection_ID);
350 
370  uint8_t ChannelNum,
371  uint32_t src,
372  uint32_t dst,
373  GPDMA_FLOW_CONTROL_T TransferType,
374  uint32_t Size);
375 
385  uint8_t ChannelNum,
386  const DMA_TransferDescriptor_t *DMADescriptor,
387  GPDMA_FLOW_CONTROL_T TransferType);
388 
403  DMA_TransferDescriptor_t *DMADescriptor,
404  uint32_t src,
405  uint32_t dst,
406  uint32_t Size,
407  GPDMA_FLOW_CONTROL_T TransferType,
408  const DMA_TransferDescriptor_t *NextDescriptor);
409 
414 #ifdef __cplusplus
415 }
416 #endif
417 
418 #endif /* __GPDMA_18XX_43XX_H_ */