LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/timer_18xx_43xx.h Source File

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timer_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx 16/32-bit Timer/PWM driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __TIMER_18XX_43XX_H_
33 #define __TIMER_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t IR;
49 __IO uint32_t TCR;
50 __IO uint32_t TC;
51 __IO uint32_t PR;
52 __IO uint32_t PC;
53 __IO uint32_t MCR;
54 __IO uint32_t MR[4];
55 __IO uint32_t CCR;
56 __IO uint32_t CR[4];
57 __IO uint32_t EMR;
58 __I uint32_t RESERVED0[12];
59 __IO uint32_t CTCR;
60 } LPC_TIMER_T;
61
63 #define TIMER_IR_CLR(n) _BIT(n)
64
66 #define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
67
68 #define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
69
71 #define TIMER_ENABLE ((uint32_t) (1 << 0))
72
73 #define TIMER_RESET ((uint32_t) (1 << 1))
74
76 #define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
77
78 #define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
79
80 #define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
81
83 #define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
84
85 #define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
86
87 #define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
88
94 void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
95
101 void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
102
111 STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
112 {
113 return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
114 }
115
124 STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
125 {
126 return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
127 }
128
136 STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
137 {
138 pTMR->IR = TIMER_IR_CLR(matchnum);
139 }
140
148 STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
149 {
150 pTMR->IR = (0x10 << capnum);
151 }
152
159 STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
160 {
161 pTMR->TCR |= TIMER_ENABLE;
162 }
163
170 STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
171 {
172 pTMR->TCR &= ~TIMER_ENABLE;
173 }
174
181 STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
182 {
183 return pTMR->TC;
184 }
185
192 STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
193 {
194 return pTMR->PC;
195 }
196
204 STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
205 {
206 pTMR->PR = prescale;
207 }
208
217 STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
218 {
219 pTMR->MR[matchnum] = matchval;
220 }
221
229 STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
230 {
231 return pTMR->CR[capnum];
232 }
233
239 void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
240
248 STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
249 {
250 pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
251 }
252
259 STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
260 {
261 pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
262 }
263
270 STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
271 {
272 pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
273 }
274
281 STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
282 {
283 pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
284 }
285
293 STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
294 {
295 pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
296 }
297
305 STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
306 {
307 pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
308 }
309
318 STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
319 {
320 pTMR->CCR |= TIMER_CAP_RISING(capnum);
321 }
322
331 STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
332 {
333 pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
334 }
335
344 STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
345 {
346 pTMR->CCR |= TIMER_CAP_FALLING(capnum);
347 }
348
357 STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
358 {
359 pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
360 }
361
370 STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
371 {
372 pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
373 }
374
381 STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
382 {
383 pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
384 }
385
389 typedef enum IP_TIMER_PIN_MATCH_STATE {
390 TIMER_EXTMATCH_DO_NOTHING = 0,
391 TIMER_EXTMATCH_CLEAR = 1,
392 TIMER_EXTMATCH_SET = 2,
393 TIMER_EXTMATCH_TOGGLE = 3
394 } TIMER_PIN_MATCH_STATE_T;
395
408 void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
409 TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
410
414 typedef enum IP_TIMER_CAP_SRC_STATE {
415 TIMER_CAPSRC_RISING_PCLK = 0,
416 TIMER_CAPSRC_RISING_CAPN = 1,
417 TIMER_CAPSRC_FALLING_CAPN = 2,
418 TIMER_CAPSRC_BOTH_CAPN = 3
419 } TIMER_CAP_SRC_STATE_T;
420
430 STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
431 TIMER_CAP_SRC_STATE_T capSrc,
432 int8_t capnum)
433 {
434 pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
435 }
436
441 #ifdef __cplusplus
442 }
443 #endif
444
445 #endif /* __TIMER_18XX_43XX_H_ */