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LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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Go to the source code of this file.
Data Structures | |
| struct | GPDMA_CH_T |
| GPDMA Channel register block structure. More... | |
| struct | LPC_GPDMA_T |
| GPDMA register block. More... | |
| struct | GPDMA_CH_CFG_T |
| GPDMA structure using for DMA configuration. More... | |
| struct | DMA_ChannelHandle_t |
| DMA channel handle structure. More... | |
| struct | DMA_TransferDescriptor_t |
| Transfer Descriptor structure typedef. More... | |
Macros | |
| #define | GPDMA_NUMBER_CHANNELS 8 |
| Number of channels on GPDMA. More... | |
| #define | GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0)) |
| Macro defines for DMA channel control registers. More... | |
| #define | GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12)) |
| #define | GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15)) |
| #define | GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18)) |
| #define | GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21)) |
| #define | GPDMA_DMACCxControl_SI ((1UL << 26)) |
| #define | GPDMA_DMACCxControl_DI ((1UL << 27)) |
| #define | GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24)) |
| #define | GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25)) |
| #define | GPDMA_DMACCxControl_Prot1 ((1UL << 28)) |
| #define | GPDMA_DMACCxControl_Prot2 ((1UL << 29)) |
| #define | GPDMA_DMACCxControl_Prot3 ((1UL << 30)) |
| #define | GPDMA_DMACCxControl_I ((1UL << 31)) |
| #define | GPDMA_DMACConfig_E ((0x01)) |
| Macro defines for DMA Configuration register. More... | |
| #define | GPDMA_DMACConfig_M ((0x02)) |
| #define | GPDMA_DMACConfig_BITMASK ((0x03)) |
| #define | GPDMA_DMACCxConfig_E ((1UL << 0)) |
| Macro defines for DMA Channel Configuration registers. More... | |
| #define | GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1)) |
| #define | GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6)) |
| #define | GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11)) |
| #define | GPDMA_DMACCxConfig_IE ((1UL << 14)) |
| #define | GPDMA_DMACCxConfig_ITC ((1UL << 15)) |
| #define | GPDMA_DMACCxConfig_L ((1UL << 16)) |
| #define | GPDMA_DMACCxConfig_A ((1UL << 17)) |
| #define | GPDMA_DMACCxConfig_H ((1UL << 18)) |
| #define | GPDMA_CONN_MEMORY ((0UL)) |
| GPDMA request connections. More... | |
| #define | GPDMA_CONN_MAT0_0 ((1UL)) |
| #define | GPDMA_CONN_UART0_Tx ((2UL)) |
| #define | GPDMA_CONN_MAT0_1 ((3UL)) |
| #define | GPDMA_CONN_UART0_Rx ((4UL)) |
| #define | GPDMA_CONN_MAT1_0 ((5UL)) |
| #define | GPDMA_CONN_UART1_Tx ((6UL)) |
| #define | GPDMA_CONN_MAT1_1 ((7UL)) |
| #define | GPDMA_CONN_UART1_Rx ((8UL)) |
| #define | GPDMA_CONN_MAT2_0 ((9UL)) |
| #define | GPDMA_CONN_UART2_Tx ((10UL)) |
| #define | GPDMA_CONN_MAT2_1 ((11UL)) |
| #define | GPDMA_CONN_UART2_Rx ((12UL)) |
| #define | GPDMA_CONN_MAT3_0 ((13UL)) |
| #define | GPDMA_CONN_UART3_Tx ((14UL)) |
| #define | GPDMA_CONN_SCT_0 ((15UL)) |
| #define | GPDMA_CONN_MAT3_1 ((16UL)) |
| #define | GPDMA_CONN_UART3_Rx ((17UL)) |
| #define | GPDMA_CONN_SCT_1 ((18UL)) |
| #define | GPDMA_CONN_SSP0_Rx ((19UL)) |
| #define | GPDMA_CONN_I2S_Tx_Channel_0 ((20UL)) |
| #define | GPDMA_CONN_SSP0_Tx ((21UL)) |
| #define | GPDMA_CONN_I2S_Rx_Channel_1 ((22UL)) |
| #define | GPDMA_CONN_SSP1_Rx ((23UL)) |
| #define | GPDMA_CONN_SSP1_Tx ((24UL)) |
| #define | GPDMA_CONN_ADC_0 ((25UL)) |
| #define | GPDMA_CONN_ADC_1 ((26UL)) |
| #define | GPDMA_CONN_DAC ((27UL)) |
| #define | GPDMA_CONN_I2S1_Tx_Channel_0 ((28UL)) |
| #define | GPDMA_CONN_I2S1_Rx_Channel_1 ((29UL)) |
| #define | GPDMA_BSIZE_1 ((0UL)) |
| GPDMA Burst size in Source and Destination definitions. More... | |
| #define | GPDMA_BSIZE_4 ((1UL)) |
| #define | GPDMA_BSIZE_8 ((2UL)) |
| #define | GPDMA_BSIZE_16 ((3UL)) |
| #define | GPDMA_BSIZE_32 ((4UL)) |
| #define | GPDMA_BSIZE_64 ((5UL)) |
| #define | GPDMA_BSIZE_128 ((6UL)) |
| #define | GPDMA_BSIZE_256 ((7UL)) |
| #define | GPDMA_WIDTH_BYTE ((0UL)) |
| Width in Source transfer width and Destination transfer width definitions. More... | |
| #define | GPDMA_WIDTH_HALFWORD ((1UL)) |
| #define | GPDMA_WIDTH_WORD ((2UL)) |
| #define | DMA_CONTROLLER 0 |
| Flow control definitions. More... | |
| #define | SRC_PER_CONTROLLER 1 |
| #define | DST_PER_CONTROLLER 2 |
Enumerations | |
| enum | GPDMA_STATECLEAR_T { GPDMA_STATCLR_INTTC, GPDMA_STATCLR_INTERR } |
| GPDMA Interrupt Clear Status. More... | |
| enum | GPDMA_STATUS_T { GPDMA_STAT_INT, GPDMA_STAT_INTTC, GPDMA_STAT_INTERR, GPDMA_STAT_RAWINTTC, GPDMA_STAT_RAWINTERR, GPDMA_STAT_ENABLED_CH } |
| GPDMA Type of Interrupt Status. More... | |
| enum | GPDMA_FLOW_CONTROL_T { GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA = ((0UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA = ((1UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA = ((2UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA = ((3UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL = ((4UL)), GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL = ((5UL)), GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL = ((6UL)), GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL = ((7UL)) } |
| GPDMA Type of DMA controller. More... | |
Functions | |
| void | Chip_GPDMA_Init (LPC_GPDMA_T *pGPDMA) |
| Initialize the GPDMA. More... | |
| void | Chip_GPDMA_DeInit (LPC_GPDMA_T *pGPDMA) |
| Shutdown the GPDMA. More... | |
| int | Chip_GPDMA_InitChannelCfg (LPC_GPDMA_T *pGPDMA, GPDMA_CH_CFG_T *GPDMACfg, uint8_t ChannelNum, uint32_t src, uint32_t dst, uint32_t Size, GPDMA_FLOW_CONTROL_T TransferType) |
| Initialize channel configuration strucutre. More... | |
| void | Chip_GPDMA_ChannelCmd (LPC_GPDMA_T *pGPDMA, uint8_t channelNum, FunctionalState NewState) |
| Enable or Disable the GPDMA Channel. More... | |
| void | Chip_GPDMA_Stop (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum) |
| Stop a stream DMA transfer. More... | |
| Status | Chip_GPDMA_Interrupt (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum) |
| The GPDMA stream interrupt status checking. More... | |
| IntStatus | Chip_GPDMA_IntGetStatus (LPC_GPDMA_T *pGPDMA, GPDMA_STATUS_T type, uint8_t channel) |
| Read the status from different registers according to the type. More... | |
| void | Chip_GPDMA_ClearIntPending (LPC_GPDMA_T *pGPDMA, GPDMA_STATECLEAR_T type, uint8_t channel) |
| Clear the Interrupt Flag from different registers according to the type. More... | |
| uint8_t | Chip_GPDMA_GetFreeChannel (LPC_GPDMA_T *pGPDMA, uint32_t PeripheralConnection_ID) |
| Get a free GPDMA channel for one DMA connection. More... | |
| Status | Chip_GPDMA_Transfer (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum, uint32_t src, uint32_t dst, GPDMA_FLOW_CONTROL_T TransferType, uint32_t Size) |
| Do a DMA transfer M2M, M2P,P2M or P2P. More... | |
| Status | Chip_GPDMA_SGTransfer (LPC_GPDMA_T *pGPDMA, uint8_t ChannelNum, const DMA_TransferDescriptor_t *DMADescriptor, GPDMA_FLOW_CONTROL_T TransferType) |
| Do a DMA transfer using linked list of descriptors. More... | |
| Status | Chip_GPDMA_PrepareDescriptor (LPC_GPDMA_T *pGPDMA, DMA_TransferDescriptor_t *DMADescriptor, uint32_t src, uint32_t dst, uint32_t Size, GPDMA_FLOW_CONTROL_T TransferType, const DMA_TransferDescriptor_t *NextDescriptor) |
| Prepare a single DMA descriptor. More... | |
1.8.3.1