LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
enet_18xx_43xx.c
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1 /*
2  * @brief LPC18xx/43xx Ethernet driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #include "chip.h"
33 
34 /*****************************************************************************
35  * Private types/enumerations/variables
36  ****************************************************************************/
37 
38 /* Saved address for PHY and clock divider */
39 STATIC uint32_t phyCfg;
40 
41 /*****************************************************************************
42  * Public types/enumerations/variables
43  ****************************************************************************/
44 
45 /*****************************************************************************
46  * Private functions
47  ****************************************************************************/
48 
50 {
53  {}
54 
55  /* Reset ethernet peripheral */
56  Chip_ENET_Reset(pENET);
57 }
58 
60 {
61  uint32_t val = SystemCoreClock / 1000000UL;
62 
63  if (val >= 20 && val < 35)
64  return 2;
65  if (val >= 35 && val < 60)
66  return 3;
67  if (val >= 60 && val < 100)
68  return 0;
69  if (val >= 100 && val < 150)
70  return 1;
71  if (val >= 150 && val < 250)
72  return 4;
73  if (val >= 250 && val < 300)
74  return 5;
75 
76  /* Code should never reach here
77  unless there is BUG in frequency settings
78  */
79  return 0;
80 }
81 
82 /*****************************************************************************
83  * Public functions
84  ****************************************************************************/
85 
86 /* Basic Ethernet interface initialization */
87 void Chip_ENET_Init(LPC_ENET_T *pENET, uint32_t phyAddr)
88 {
89  Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);
90 
91  reset(pENET);
92 
93  /* Setup MII link divider to /102 and PHY address 1 */
94  Chip_ENET_SetupMII(pENET, Chip_ENET_CalcMDCClock(), phyAddr);
95 
96  /* Enhanced descriptors, burst length = 1 */
98 
99  /* Initial MAC configuration for checksum offload, full duplex,
100  100Mbps, disable receive own in half duplex, inter-frame gap
101  of 64-bits */
102  pENET->MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM |
104 
105  /* Setup default filter */
107 
108  /* Flush transmit FIFO */
109  pENET->DMA_OP_MODE = DMA_OM_FTF;
110 
111  /* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at
112  64 bytes */
113  pENET->DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0);
114 
115  /* Clear all MAC interrupts */
116  pENET->DMA_STAT = DMA_ST_ALL;
117 
118  /* Enable MAC interrupts */
119  pENET->DMA_INT_EN = 0;
120 }
121 
122 /* Ethernet interface shutdown */
124 {
125  /* Disable packet reception */
126  pENET->MAC_CONFIG = 0;
127 
128  /* Flush transmit FIFO */
129  pENET->DMA_OP_MODE = DMA_OM_FTF;
130 
131  /* Disable receive and transmit DMA processes */
132  pENET->DMA_OP_MODE = 0;
133 
135 }
136 
137 /* Sets up the PHY link clock divider and PHY address */
138 void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr)
139 {
140  /* Save clock divider and PHY address in MII address register */
141  phyCfg = MAC_MIIA_PA(addr) | MAC_MIIA_CR(div);
142 }
143 
144 /* Starts a PHY write via the MII */
145 void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data)
146 {
147  /* Write value at PHY address and register */
148  pENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg) | MAC_MIIA_W;
149  pENET->MAC_MII_DATA = (uint32_t) data;
150  pENET->MAC_MII_ADDR |= MAC_MIIA_GB;
151 }
152 
153 /*Starts a PHY read via the MII */
154 void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg)
155 {
156  /* Read value at PHY address and register */
157  pENET->MAC_MII_ADDR = phyCfg | MAC_MIIA_GR(reg);
158  pENET->MAC_MII_ADDR |= MAC_MIIA_GB;
159 }
160 
161 /* Sets full or half duplex for the interface */
162 void Chip_ENET_SetDuplex(LPC_ENET_T *pENET, bool full)
163 {
164  if (full) {
165  pENET->MAC_CONFIG |= MAC_CFG_DM;
166  }
167  else {
168  pENET->MAC_CONFIG &= ~MAC_CFG_DM;
169  }
170 }
171 
172 /* Sets speed for the interface */
173 void Chip_ENET_SetSpeed(LPC_ENET_T *pENET, bool speed100)
174 {
175  if (speed100) {
176  pENET->MAC_CONFIG |= MAC_CFG_FES;
177  }
178  else {
179  pENET->MAC_CONFIG &= ~MAC_CFG_FES;
180  }
181 }
182