LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h File Reference

| LPCOpen Platform for LPC18XX/43XX microcontrollers 18XX43XX LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers

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Data Structures | Macros | Functions
enet_18xx_43xx.h File Reference

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## Data Structures
struct | LPC_ENET_T
| 10/100 MII & RMII Ethernet with timestamping register block structure More...
struct | ENET_TXDESC_T
| Structure of a transmit descriptor (without timestamp) More...
struct | ENET_ENHTXDESC_T
| Structure of a enhanced transmit descriptor (with timestamp) More...
struct | ENET_RXDESC_T
| Structure of a receive descriptor (without timestamp) More...
struct | ENET_ENHRXDESC_T
| Structure of a enhanced receive descriptor (with timestamp) More...

## Macros
#define | MAC_CFG_RE (1 << 2)
#define | MAC_CFG_TE (1 << 3)
#define | MAC_CFG_DF (1 << 4)
#define | MAC_CFG_BL(n) ((n) << 5)
#define | MAC_CFG_ACS (1 << 7)
#define | MAC_CFG_LUD (1 << 8)
#define | MAC_CFG_DR (1 << 9)
#define | MAC_CFG_IPC (1 << 10)
#define | MAC_CFG_DM (1 << 11)
#define | MAC_CFG_LM (1 << 12)
#define | MAC_CFG_DO (1 << 13)
#define | MAC_CFG_FES (1 << 14)
#define | MAC_CFG_PS (1 << 15)
#define | MAC_CFG_DCRS (1 << 16)
#define | MAC_CFG_IFG(n) ((n) << 17)
#define | MAC_CFG_JE (1 << 20)
#define | MAC_CFG_JD (1 << 22)
#define | MAC_CFG_WD (1 << 23)
#define | MAC_FF_PR (1 << 0)
#define | MAC_FF_DAIF (1 << 3)
#define | MAC_FF_PM (1 << 4)
#define | MAC_FF_DBF (1 << 5)
#define | MAC_FF_PCF(n) ((n) << 6)
#define | MAC_FF_SAIF (1 << 8)
#define | MAC_FF_SAF (1 << 9)
#define | MAC_FF_RA (1UL << 31)
#define | MAC_MIIA_GB (1 << 0)
#define | MAC_MIIA_W (1 << 1)
#define | MAC_MIIA_CR(n) ((n) << 2)
#define | MAC_MIIA_GR(n) ((n) << 6)
#define | MAC_MIIA_PA(n) ((n) << 11)
#define | MAC_MIID_GDMSK (0xFFFF)
#define | MAC_FC_FCB (1 << 0)
| MAC_FLOW_CONTROL register bit defines. More...
#define | MAC_FC_TFE (1 << 1)
#define | MAC_FC_RFE (1 << 2)
#define | MAC_FC_UP (1 << 3)
#define | MAC_FC_PLT(n) ((n) << 4)
#define | MAC_FC_DZPQ (1 << 7)
#define | MAC_FC_PT(n) ((n) << 16)
#define | MAC_VT_VL(n) ((n) << 0)
#define | MAC_VT_ETC (1 << 7)
#define | MAC_PMT_PD (1 << 0)
#define | MAC_PMT_MPE (1 << 1)
#define | MAC_PMT_WFE (1 << 2)
#define | MAC_PMT_MPR (1 << 5)
#define | MAC_PMT_WFR (1 << 6)
#define | MAC_PMT_GU (1 << 9)
#define | MAC_PMT_WFFRPR (1UL << 31)
#define | MAC_IM_PMT (1 << 3)
#define | MAC_ADRH_MO (1UL << 31)
#define | MAC_TS_TSENA (1 << 0)
#define | MAC_TS_TSCFUP (1 << 1)
#define | MAC_TS_TSINIT (1 << 2)
#define | MAC_TS_TSUPDT (1 << 3)
#define | MAC_TS_TSTRIG (1 << 4)
#define | MAC_TS_TSADDR (1 << 5)
#define | MAC_TS_TSENAL (1 << 8)
#define | MAC_TS_TSCTRL (1 << 9)
#define | MAC_TS_TSVER2 (1 << 10)
#define | MAC_TS_TSIPENA (1 << 11)
#define | MAC_TS_TSIPV6E (1 << 12)
#define | MAC_TS_TSIPV4E (1 << 13)
#define | MAC_TS_TSEVNT (1 << 14)
#define | MAC_TS_TSMSTR (1 << 15)
#define | MAC_TS_TSCLKT(n) ((n) << 16)
#define | MAC_TS_TSENMA (1 << 18)
#define | DMA_BM_SWR (1 << 0)
#define | DMA_BM_DA (1 << 1)
#define | DMA_BM_DSL(n) ((n) << 2)
#define | DMA_BM_ATDS (1 << 7)
#define | DMA_BM_PBL(n) ((n) << 8)
#define | DMA_BM_PR(n) ((n) << 14)
#define | DMA_BM_FB (1 << 16)
#define | DMA_BM_RPBL(n) ((n) << 17)
#define | DMA_BM_USP (1 << 23)
#define | DMA_BM_PBL8X (1 << 24)
#define | DMA_BM_AAL (1 << 25)
#define | DMA_BM_MB (1 << 26)
#define | DMA_BM_TXPR (1 << 27)
#define | DMA_ST_TI (1 << 0)
#define | DMA_ST_TPS (1 << 1)
#define | DMA_ST_TU (1 << 2)
#define | DMA_ST_TJT (1 << 3)
#define | DMA_ST_OVF (1 << 4)
#define | DMA_ST_UNF (1 << 5)
#define | DMA_ST_RI (1 << 6)
#define | DMA_ST_RU (1 << 7)
#define | DMA_ST_RPS (1 << 8)
#define | DMA_ST_RWT (1 << 9)
#define | DMA_ST_ETI (1 << 10)
#define | DMA_ST_FBI (1 << 13)
#define | DMA_ST_ERI (1 << 14)
#define | DMA_ST_AIE (1 << 15)
#define | DMA_ST_NIS (1 << 16)
#define | DMA_ST_ALL (0x1E7FF)
#define | DMA_OM_SR (1 << 1)
#define | DMA_OM_OSF (1 << 2)
#define | DMA_OM_RTC(n) ((n) << 3)
#define | DMA_OM_FUF (1 << 6)
#define | DMA_OM_FEF (1 << 7)
#define | DMA_OM_ST (1 << 13)
#define | DMA_OM_TTC(n) ((n) << 14)
#define | DMA_OM_FTF (1 << 20)
#define | DMA_OM_TSF (1 << 21)
#define | DMA_OM_DFF (1 << 24)
#define | DMA_OM_RSF (1 << 25)
#define | DMA_OM_DT (1 << 26)
#define | DMA_IE_TIE (1 << 0)
#define | DMA_IE_TSE (1 << 1)
#define | DMA_IE_TUE (1 << 2)
#define | DMA_IE_TJE (1 << 3)
#define | DMA_IE_OVE (1 << 4)
#define | DMA_IE_UNE (1 << 5)
#define | DMA_IE_RIE (1 << 6)
#define | DMA_IE_RUE (1 << 7)
#define | DMA_IE_RSE (1 << 8)
#define | DMA_IE_RWE (1 << 9)
#define | DMA_IE_ETE (1 << 10)
#define | DMA_IE_FBE (1 << 13)
#define | DMA_IE_ERE (1 << 14)
#define | DMA_IE_AIE (1 << 15)
#define | DMA_IE_NIE (1 << 16)
#define | DMA_MFRM_FMCMSK (0xFFFF)
#define | DMA_MFRM_OC (1 << 16)
#define | DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17)
#define | DMA_MFRM_OF (1 << 28)
#define | TDES_DB (1 << 0)
#define | TDES_UF (1 << 1)
#define | TDES_ED (1 << 2)
#define | TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)
#define | TDES_VF (1 << 7)
#define | TDES_EC (1 << 8)
#define | TDES_LC (1 << 9)
#define | TDES_NC (1 << 10)
#define | TDES_LCAR (1 << 11)
#define | TDES_IPE (1 << 12)
#define | TDES_FF (1 << 13)
#define | TDES_JT (1 << 14)
#define | TDES_ES (1 << 15)
#define | TDES_IHE (1 << 16)
#define | TDES_TTSS (1 << 17)
#define | TDES_OWN (1UL << 31)
#define | TDES_ENH_IC (1UL << 30)
#define | TDES_ENH_LS (1 << 29)
#define | TDES_ENH_FS (1 << 28)
#define | TDES_ENH_DC (1 << 27)
#define | TDES_ENH_DP (1 << 26)
#define | TDES_ENH_TTSE (1 << 25)
#define | TDES_ENH_CIC(n) ((n) << 22)
#define | TDES_ENH_TER (1 << 21)
#define | TDES_ENH_TCH (1 << 20)
#define | TDES_NORM_IC (1UL << 31)
#define | TDES_NORM_FS (1 << 30)
#define | TDES_NORM_LS (1 << 29)
#define | TDES_NORM_CIC(n) ((n) << 27)
#define | TDES_NORM_DC (1 << 26)
#define | TDES_NORM_TER (1 << 25)
#define | TDES_NORM_TCH (1 << 24)
#define | TDES_NORM_DP (1 << 23)
#define | TDES_NORM_TTSE (1 << 22)
#define | TDES_NORM_BS2(n) (((n) & 0x3FF) << 11)
#define | TDES_NORM_BS1(n) (((n) & 0x3FF) << 0)
#define | TDES_ENH_BS2(n) (((n) & 0xFFF) << 16)
#define | TDES_ENH_BS1(n) (((n) & 0xFFF) << 0)
#define | RDES_ESA (1 << 0)
#define | RDES_CE (1 << 1)
#define | RDES_DRE (1 << 2)
#define | RDES_RE (1 << 3)
#define | RDES_RWT (1 << 4)
#define | RDES_FT (1 << 5)
#define | RDES_LC (1 << 6)
#define | RDES_TSA (1 << 7)
#define | RDES_LS (1 << 8)
#define | RDES_FS (1 << 9)
#define | RDES_VLAN (1 << 10)
#define | RDES_OE (1 << 11)
#define | RDES_LE (1 << 12)
#define | RDES_SAF (1 << 13)
#define | RDES_DE (1 << 14)
#define | RDES_ES (1 << 15)
#define | RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)
#define | RDES_AFM (1 << 30)
#define | RDES_OWN (1UL << 31)
#define | RDES_DINT (1UL << 31)
#define | RDES_NORM_RER (1 << 25)
#define | RDES_NORM_RCH (1 << 24)
#define | RDES_NORM_BS2(n) (((n) & 0x3FF) << 11)
#define | RDES_NORM_BS1(n) (((n) & 0x3FF) << 0)
#define | RDES_ENH_RER (1 << 15)
| REC_DESC_ENH_T only CTRL field bit defines. More...
#define | RDES_ENH_RCH (1 << 14)
#define | RDES_ENH_BS2(n) (((n) & 0xFFF) << 16)
#define | RDES_ENH_BS1(n) (((n) & 0xFFF) << 0)
#define | RDES_ENH_IPPL(n) (((n) & 0x7) >> 2)
#define | RDES_ENH_IPHE (1 << 3)
#define | RDES_ENH_IPPLE (1 << 4)
#define | RDES_ENH_IPCSB (1 << 5)
#define | RDES_ENH_IPV4 (1 << 6)
#define | RDES_ENH_IPV6 (1 << 7)
#define | RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8)
#define | EMAC_ETH_MAX_FLEN (1536)

## Functions
STATIC INLINE void | Chip_ENET_Reset (LPC_ENET_T *pENET)
| Resets the ethernet interface. More...
STATIC INLINE void | Chip_ENET_SetADDR (LPC_ENET_T *pENET, const uint8_t *macAddr)
| Sets the address of the interface. More...
void | Chip_ENET_SetupMII (LPC_ENET_T *pENET, uint32_t div, uint8_t addr)
| Sets up the PHY link clock divider and PHY address. More...
void | Chip_ENET_StartMIIWrite (LPC_ENET_T *pENET, uint8_t reg, uint16_t data)
| Starts a PHY write via the MII. More...
void | Chip_ENET_StartMIIRead (LPC_ENET_T *pENET, uint8_t reg)
| Starts a PHY read via the MII. More...
STATIC INLINE bool | Chip_ENET_IsMIIBusy (LPC_ENET_T *pENET)
| Returns MII link (PHY) busy status. More...
STATIC INLINE uint16_t | Chip_ENET_ReadMIIData (LPC_ENET_T *pENET)
| Returns the value read from the PHY. More...
STATIC INLINE void | Chip_ENET_TXEnable (LPC_ENET_T *pENET)
| Enables ethernet transmit. More...
STATIC INLINE void | Chip_ENET_TXDisable (LPC_ENET_T *pENET)
| Disables ethernet transmit. More...
STATIC INLINE void | Chip_ENET_RXEnable (LPC_ENET_T *pENET)
| Enables ethernet packet reception. More...
STATIC INLINE void | Chip_ENET_RXDisable (LPC_ENET_T *pENET)
| Disables ethernet packet reception. More...
STATIC INLINE void | Chip_ENET_RMIIEnable (LPC_ENET_T *pENET)
| Enable RMII ethernet operation. More...
STATIC INLINE void | Chip_ENET_MIIEnable (LPC_ENET_T *pENET)
| Enable MII ethernet operation. More...
void | Chip_ENET_SetDuplex (LPC_ENET_T *pENET, bool full)
| Sets full or half duplex for the interface. More...
void | Chip_ENET_SetSpeed (LPC_ENET_T *pENET, bool speed100)
| Sets speed for the interface. More...
STATIC INLINE void | Chip_ENET_InitDescriptors (LPC_ENET_T *pENET, ENET_ENHTXDESC_T *pTXDescs, ENET_ENHRXDESC_T *pRXDescs)
| Configures the initial ethernet descriptors. More...
STATIC INLINE void | Chip_ENET_RXStart (LPC_ENET_T *pENET)
| Starts receive polling of RX descriptors. More...
STATIC INLINE void | Chip_ENET_TXStart (LPC_ENET_T *pENET)
| Starts transmit polling of TX descriptors. More...
void | Chip_ENET_Init (LPC_ENET_T *pENET, uint32_t phyAddr)
| Initialize ethernet interface. More...
void | Chip_ENET_DeInit (LPC_ENET_T *pENET)
| De-initialize the ethernet interface. More...