32 #ifndef __SGPIO_43XX_H_
33 #define __SGPIO_43XX_H_
45 #if defined(CHIP_LPC43XX)
51 __IO uint32_t OUT_MUX_CFG[16];
52 __IO uint32_t SGPIO_MUX_CFG[16];
53 __IO uint32_t SLICE_MUX_CFG[16];
54 __IO uint32_t REG[16];
55 __IO uint32_t REG_SS[16];
56 __IO uint32_t PRESET[16];
57 __IO uint32_t COUNT[16];
58 __IO uint32_t POS[16];
63 __I uint32_t GPIO_INREG;
64 __IO uint32_t GPIO_OUTREG;
65 __IO uint32_t GPIO_OENREG;
66 __IO uint32_t CTRL_ENABLED;
67 __IO uint32_t CTRL_DISABLED;
68 __I uint32_t RESERVED0[823];
69 __O uint32_t CLR_EN_0;
70 __O uint32_t SET_EN_0;
71 __I uint32_t ENABLE_0;
72 __I uint32_t STATUS_0;
73 __O uint32_t CTR_STATUS_0;
74 __O uint32_t SET_STATUS_0;
75 __I uint32_t RESERVED1[2];
76 __O uint32_t CLR_EN_1;
77 __O uint32_t SET_EN_1;
78 __I uint32_t ENABLE_1;
79 __I uint32_t STATUS_1;
80 __O uint32_t CTR_STATUS_1;
81 __O uint32_t SET_STATUS_1;
82 __I uint32_t RESERVED2[2];
83 __O uint32_t CLR_EN_2;
84 __O uint32_t SET_EN_2;
85 __I uint32_t ENABLE_2;
86 __I uint32_t STATUS_2;
87 __O uint32_t CTR_STATUS_2;
88 __O uint32_t SET_STATUS_2;
89 __I uint32_t RESERVED3[2];
90 __O uint32_t CLR_EN_3;
91 __O uint32_t SET_EN_3;
92 __I uint32_t ENABLE_3;
93 __I uint32_t STATUS_3;
94 __O uint32_t CTR_STATUS_3;
95 __O uint32_t SET_STATUS_3;