LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/uart_18xx_43xx.h Source File

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uart_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx UART chip driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __UART_18XX_43XX_H_
33 #define __UART_18XX_43XX_H_
34
35 #include "ring_buffer.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
49 typedef struct {
51 union {
52 __IO uint32_t DLL;
53 __O uint32_t THR;
54 __I uint32_t RBR;
55 };
56
57 union {
58 __IO uint32_t IER;
59 __IO uint32_t DLM;
60 };
61
62 union {
63 __O uint32_t FCR;
64 __I uint32_t IIR;
65 };
66
67 __IO uint32_t LCR;
68 __IO uint32_t MCR;
69 __I uint32_t LSR;
70 __I uint32_t MSR;
71 __IO uint32_t SCR;
72 __IO uint32_t ACR;
73 __IO uint32_t ICR;
74 __IO uint32_t FDR;
75 __IO uint32_t OSR;
76 __IO uint32_t TER1;
77 uint32_t RESERVED0[3];
78 __IO uint32_t HDEN;
79 __I uint32_t RESERVED1[1];
80 __IO uint32_t SCICTRL;
82 __IO uint32_t RS485CTRL;
83 __IO uint32_t RS485ADRMATCH;
84 __IO uint32_t RS485DLY;
86 union {
87 __IO uint32_t SYNCCTRL;
88 __I uint32_t FIFOLVL;
89 };
90
91 __IO uint32_t TER2;
92 } LPC_USART_T;
93
94
98 #define UART_RBR_MASKBIT (0xFF)
103 #define UART_LOAD_DLL(div) ((div) & 0xFF)
104 #define UART_DLL_MASKBIT (0xFF)
109 #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
110 #define UART_DLM_MASKBIT (0xFF)
115 #define UART_IER_RBRINT (1 << 0)
116 #define UART_IER_THREINT (1 << 1)
117 #define UART_IER_RLSINT (1 << 2)
118 #define UART_IER_MSINT (1 << 3)
119 #define UART_IER_CTSINT (1 << 7)
120 #define UART_IER_ABEOINT (1 << 8)
121 #define UART_IER_ABTOINT (1 << 9)
122 #define UART_IER_BITMASK (0x307)
123 #define UART1_IER_BITMASK (0x30F)
124 #define UART2_IER_BITMASK (0x38F)
129 #define UART_IIR_INTSTAT_PEND (1 << 0)
130 #define UART_IIR_FIFO_EN (3 << 6)
131 #define UART_IIR_ABEO_INT (1 << 8)
132 #define UART_IIR_ABTO_INT (1 << 9)
133 #define UART_IIR_BITMASK (0x3CF)
135 /* Interrupt ID bit definitions */
136 #define UART_IIR_INTID_MASK (7 << 1)
137 #define UART_IIR_INTID_RLS (3 << 1)
138 #define UART_IIR_INTID_RDA (2 << 1)
139 #define UART_IIR_INTID_CTI (6 << 1)
140 #define UART_IIR_INTID_THRE (1 << 1)
141 #define UART_IIR_INTID_MODEM (0 << 1)
146 #define UART_FCR_FIFO_EN (1 << 0)
147 #define UART_FCR_RX_RS (1 << 1)
148 #define UART_FCR_TX_RS (1 << 2)
149 #define UART_FCR_DMAMODE_SEL (1 << 3)
150 #define UART_FCR_BITMASK (0xCF)
152 #define UART_TX_FIFO_SIZE (16)
153
154 /* FIFO trigger level bit definitions */
155 #define UART_FCR_TRG_LEV0 (0)
156 #define UART_FCR_TRG_LEV1 (1 << 6)
157 #define UART_FCR_TRG_LEV2 (2 << 6)
158 #define UART_FCR_TRG_LEV3 (3 << 6)
163 /* UART word length select bit definitions */
164 #define UART_LCR_WLEN_MASK (3 << 0)
165 #define UART_LCR_WLEN5 (0 << 0)
166 #define UART_LCR_WLEN6 (1 << 0)
167 #define UART_LCR_WLEN7 (2 << 0)
168 #define UART_LCR_WLEN8 (3 << 0)
170 /* UART Stop bit select bit definitions */
171 #define UART_LCR_SBS_MASK (1 << 2)
172 #define UART_LCR_SBS_1BIT (0 << 2)
173 #define UART_LCR_SBS_2BIT (1 << 2)
175 /* UART Parity enable bit definitions */
176 #define UART_LCR_PARITY_EN (1 << 3)
177 #define UART_LCR_PARITY_DIS (0 << 3)
178 #define UART_LCR_PARITY_ODD (0 << 4)
179 #define UART_LCR_PARITY_EVEN (1 << 4)
180 #define UART_LCR_PARITY_F_1 (2 << 4)
181 #define UART_LCR_PARITY_F_0 (3 << 4)
182 #define UART_LCR_BREAK_EN (1 << 6)
183 #define UART_LCR_DLAB_EN (1 << 7)
184 #define UART_LCR_BITMASK (0xFF)
189 #define UART_MCR_DTR_CTRL (1 << 0)
190 #define UART_MCR_RTS_CTRL (1 << 1)
191 #define UART_MCR_LOOPB_EN (1 << 4)
192 #define UART_MCR_AUTO_RTS_EN (1 << 6)
193 #define UART_MCR_AUTO_CTS_EN (1 << 7)
194 #define UART_MCR_BITMASK (0xD3)
199 #define UART_LSR_RDR (1 << 0)
200 #define UART_LSR_OE (1 << 1)
201 #define UART_LSR_PE (1 << 2)
202 #define UART_LSR_FE (1 << 3)
203 #define UART_LSR_BI (1 << 4)
204 #define UART_LSR_THRE (1 << 5)
205 #define UART_LSR_TEMT (1 << 6)
206 #define UART_LSR_RXFE (1 << 7)
207 #define UART_LSR_TXFE (1 << 8)
208 #define UART_LSR_BITMASK (0xFF)
209 #define UART1_LSR_BITMASK (0x1FF)
214 #define UART_MSR_DELTA_CTS (1 << 0)
215 #define UART_MSR_DELTA_DSR (1 << 1)
216 #define UART_MSR_LO2HI_RI (1 << 2)
217 #define UART_MSR_DELTA_DCD (1 << 3)
218 #define UART_MSR_CTS (1 << 4)
219 #define UART_MSR_DSR (1 << 5)
220 #define UART_MSR_RI (1 << 6)
221 #define UART_MSR_DCD (1 << 7)
222 #define UART_MSR_BITMASK (0xFF)
227 #define UART_ACR_START (1 << 0)
228 #define UART_ACR_MODE (1 << 1)
229 #define UART_ACR_AUTO_RESTART (1 << 2)
230 #define UART_ACR_ABEOINT_CLR (1 << 8)
231 #define UART_ACR_ABTOINT_CLR (1 << 9)
232 #define UART_ACR_BITMASK (0x307)
237 #define UART_ACR_MODE0 (0)
238 #define UART_ACR_MODE1 (1)
243 #define UART_RS485CTRL_NMM_EN (1 << 0)
244 #define UART_RS485CTRL_RX_DIS (1 << 1)
245 #define UART_RS485CTRL_AADEN (1 << 2)
246 #define UART_RS485CTRL_SEL_DTR (1 << 3)
248 #define UART_RS485CTRL_DCTRL_EN (1 << 4)
249 #define UART_RS485CTRL_OINV_1 (1 << 5)
252 #define UART_RS485CTRL_BITMASK (0x3F)
257 #define UART_ICR_IRDAEN (1 << 0)
258 #define UART_ICR_IRDAINV (1 << 1)
259 #define UART_ICR_FIXPULSE_EN (1 << 2)
260 #define UART_ICR_PULSEDIV(n) ((n & 0x07) << 3)
261 #define UART_ICR_BITMASK (0x3F)
266 #define UART_HDEN_HDEN ((1 << 0))
271 #define UART_SCICTRL_SCIEN (1 << 0)
272 #define UART_SCICTRL_NACKDIS (1 << 1)
273 #define UART_SCICTRL_PROTSEL_T1 (1 << 2)
274 #define UART_SCICTRL_TXRETRY(n) ((n & 0x07) << 5)
275 #define UART_SCICTRL_GUARDTIME(n) ((n & 0xFF) << 8)
280 #define UART_FDR_DIVADDVAL(n) (n & 0x0F)
281 #define UART_FDR_MULVAL(n) ((n << 4) & 0xF0)
282 #define UART_FDR_BITMASK (0xFF)
287 #define UART_TER1_TXEN (1 << 7)
288 #define UART_TER2_TXEN (1 << 0)
293 #define UART_SYNCCTRL_SYNC (1 << 0)
294 #define UART_SYNCCTRL_CSRC_MASTER (1 << 1)
295 #define UART_SYNCCTRL_FES (1 << 2)
296 #define UART_SYNCCTRL_TSBYPASS (1 << 3)
297 #define UART_SYNCCTRL_CSCEN (1 << 4)
298 #define UART_SYNCCTRL_STARTSTOPDISABLE (1 << 5)
299 #define UART_SYNCCTRL_CCCLR (1 << 6)
306 STATIC INLINE void Chip_UART_TXEnable(LPC_USART_T *pUART)
307 {
308 pUART->TER2 = UART_TER2_TXEN;
309 }
310
316 STATIC INLINE void Chip_UART_TXDisable(LPC_USART_T *pUART)
317 {
318 pUART->TER2 = 0;
319 }
320
329 STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)
330 {
331 pUART->THR = (uint32_t) data;
332 }
333
342 STATIC INLINE uint8_t Chip_UART_ReadByte(LPC_USART_T *pUART)
343 {
344 return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
345 }
346
357 STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask)
358 {
359 pUART->IER |= intMask;
360 }
361
372 STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask)
373 {
374 pUART->IER &= ~intMask;
375 }
376
385 STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART)
386 {
387 return pUART->IER;
388 }
389
395 STATIC INLINE uint32_t Chip_UART_ReadIntIDReg(LPC_USART_T *pUART)
396 {
397 return pUART->IIR;
398 }
399
410 STATIC INLINE void Chip_UART_SetupFIFOS(LPC_USART_T *pUART, uint32_t fcr)
411 {
412 pUART->FCR = fcr;
413 }
414
425 STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config)
426 {
427 pUART->LCR = config;
428 }
429
435 STATIC INLINE void Chip_UART_EnableDivisorAccess(LPC_USART_T *pUART)
436 {
437 pUART->LCR |= UART_LCR_DLAB_EN;
438 }
439
445 STATIC INLINE void Chip_UART_DisableDivisorAccess(LPC_USART_T *pUART)
446 {
447 pUART->LCR &= ~UART_LCR_DLAB_EN;
448 }
449
460 STATIC INLINE void Chip_UART_SetDivisorLatches(LPC_USART_T *pUART, uint8_t dll, uint8_t dlm)
461 {
462 pUART->DLL = (uint32_t) dll;
463 pUART->DLM = (uint32_t) dlm;
464 }
465
466
474 STATIC INLINE uint32_t Chip_UART_ReadModemControl(LPC_USART_T *pUART)
475 {
476 return pUART->MCR;
477 }
478
487 STATIC INLINE void Chip_UART_SetModemControl(LPC_USART_T *pUART, uint32_t mcr)
488 {
489 pUART->MCR |= mcr;
490 }
491
500 STATIC INLINE void Chip_UART_ClearModemControl(LPC_USART_T *pUART, uint32_t mcr)
501 {
502 pUART->MCR &= ~mcr;
503 }
504
512 STATIC INLINE uint32_t Chip_UART_ReadLineStatus(LPC_USART_T *pUART)
513 {
514 return pUART->LSR;
515 }
516
524 STATIC INLINE uint32_t Chip_UART_ReadModemStatus(LPC_USART_T *pUART)
525 {
526 return pUART->MSR;
527 }
528
535 STATIC INLINE void Chip_UART_SetScratch(LPC_USART_T *pUART, uint8_t data)
536 {
537 pUART->SCR = (uint32_t) data;
538 }
539
545 STATIC INLINE uint8_t Chip_UART_ReadScratch(LPC_USART_T *pUART)
546 {
547 return (uint8_t) (pUART->SCR & 0xFF);
548 }
549
558 STATIC INLINE void Chip_UART_SetAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
559 {
560 pUART->ACR |= acr;
561 }
562
571 STATIC INLINE void Chip_UART_ClearAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
572 {
573 pUART->ACR &= ~acr;
574 }
575
584 STATIC INLINE void Chip_UART_SetRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
585 {
586 pUART->RS485CTRL |= ctrl;
587 }
588
597 STATIC INLINE void Chip_UART_ClearRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
598 {
599 pUART->RS485CTRL &= ~ctrl;
600 }
601
608 STATIC INLINE void Chip_UART_SetRS485Addr(LPC_USART_T *pUART, uint8_t addr)
609 {
610 pUART->RS485ADRMATCH = (uint32_t) addr;
611 }
612
618 STATIC INLINE uint8_t Chip_UART_GetRS485Addr(LPC_USART_T *pUART)
619 {
620 return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
621 }
622
631 STATIC INLINE void Chip_UART_SetRS485Delay(LPC_USART_T *pUART, uint8_t dly)
632 {
633 pUART->RS485DLY = (uint32_t) dly;
634 }
635
643 STATIC INLINE uint8_t Chip_UART_GetRS485Delay(LPC_USART_T *pUART)
644 {
645 return (uint8_t) (pUART->RS485DLY & 0xFF);
646 }
647
653 void Chip_UART_Init(LPC_USART_T *pUART);
654
660 void Chip_UART_DeInit(LPC_USART_T *pUART);
661
662
668 FlagStatus Chip_UART_CheckBusy(LPC_USART_T *pUART);
669
681 int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes);
682
693 int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes);
694
701 uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);
702
714 uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baud);
715
725 int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes);
726
737 int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes);
738
748 void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
749
759 void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
760
772 uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes);
773
785 int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes);
786
797 void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB);
798
804 FlagStatus Chip_UART_GetABEOStatus(LPC_USART_T *pUART);
805
815 void Chip_UART_ABCmd(LPC_USART_T *pUART, uint32_t mode, bool autorestart,
816 FunctionalState NewState);
817
822 #ifdef __cplusplus
823 }
824 #endif
825
826 #endif /* __UART_18XX_43XX_H_ */