LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
sct_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx State Configurable Timer (SCT) driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licenser disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SCT_18XX_43XX_H_
33 #define __SCT_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
44 /*
45  * @brief SCT Module configuration
46  */
47 #define CONFIG_SCT_nEV (16)
48 #define CONFIG_SCT_nRG (16)
49 #define CONFIG_SCT_nOU (16)
54 typedef struct {
55  __IO uint32_t CONFIG;
56  union {
57  __IO uint32_t CTRL_U;
58  struct {
59  __IO uint16_t CTRL_L;
60  __IO uint16_t CTRL_H;
61  };
62 
63  };
64 
65  __IO uint16_t LIMIT_L;
66  __IO uint16_t LIMIT_H;
67  __IO uint16_t HALT_L;
68  __IO uint16_t HALT_H;
69  __IO uint16_t STOP_L;
70  __IO uint16_t STOP_H;
71  __IO uint16_t START_L;
72  __IO uint16_t START_H;
73  uint32_t RESERVED1[10];
74  union {
75  __IO uint32_t COUNT_U;
76  struct {
77  __IO uint16_t COUNT_L;
78  __IO uint16_t COUNT_H;
79  };
80 
81  };
82 
83  __IO uint16_t STATE_L;
84  __IO uint16_t STATE_H;
85  __I uint32_t INPUT;
86  __IO uint16_t REGMODE_L;
87  __IO uint16_t REGMODE_H;
88  __IO uint32_t OUTPUT;
89  __IO uint32_t OUTPUTDIRCTRL;
90  __IO uint32_t RES;
91  __IO uint32_t DMA0REQUEST;
92  __IO uint32_t DMA1REQUEST;
93  uint32_t RESERVED2[35];
94  __IO uint32_t EVEN;
95  __IO uint32_t EVFLAG;
96  __IO uint32_t CONEN;
97  __IO uint32_t CONFLAG;
98  union {
99  __IO union {
100  uint32_t U;
101  struct {
102  uint16_t L;
103  uint16_t H;
104  };
105 
106  } MATCH[CONFIG_SCT_nRG];
107 
108  __I union {
109  uint32_t U;
110  struct {
111  uint16_t L;
112  uint16_t H;
113  };
114 
115  } CAP[CONFIG_SCT_nRG];
116 
117  };
118 
119  uint32_t RESERVED3[32 - CONFIG_SCT_nRG];
120  union {
121  __IO uint16_t MATCH_L[CONFIG_SCT_nRG];
122  __I uint16_t CAP_L[CONFIG_SCT_nRG];
123  };
124 
125  uint16_t RESERVED4[32 - CONFIG_SCT_nRG];
126  union {
127  __IO uint16_t MATCH_H[CONFIG_SCT_nRG];
128  __I uint16_t CAP_H[CONFIG_SCT_nRG];
129  };
130 
131  uint16_t RESERVED5[32 - CONFIG_SCT_nRG];
132  union {
133  __IO union {
134  uint32_t U;
135  struct {
136  uint16_t L;
137  uint16_t H;
138  };
139 
140  } MATCHREL[CONFIG_SCT_nRG];
141 
142  __IO union {
143  uint32_t U;
144  struct {
145  uint16_t L;
146  uint16_t H;
147  };
148 
149  } CAPCTRL[CONFIG_SCT_nRG];
150 
151  };
152 
153  uint32_t RESERVED6[32 - CONFIG_SCT_nRG];
154  union {
155  __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG];
156  __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG];
157  };
158 
159  uint16_t RESERVED7[32 - CONFIG_SCT_nRG];
160  union {
161  __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG];
162  __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG];
163  };
164 
165  uint16_t RESERVED8[32 - CONFIG_SCT_nRG];
166  __IO struct {
167  uint32_t STATE;
168  uint32_t CTRL;
169  } EVENT[CONFIG_SCT_nEV];
170 
171  uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV];
172  __IO struct {
173  uint32_t SET;
174  uint32_t CLR;
175  } OUT[CONFIG_SCT_nOU];
176 
177  uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU];
178  __I uint32_t MODULECONTENT;
179 } LPC_SCT_T;
180 
181 /*
182  * @brief Macro defines for SCT configuration register
183  */
184 #define SCT_CONFIG_16BIT_COUNTER 0x00000000
185 #define SCT_CONFIG_32BIT_COUNTER 0x00000001
187 #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1)
188 #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1)
189 #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1)
190 #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1)
192 #define SCT_CONFIG_NORELOADL_U (0x1 << 7)
193 #define SCT_CONFIG_NORELOADH (0x1 << 8)
194 #define SCT_CONFIG_AUTOLIMIT_L (0x1 << 17)
195 #define SCT_CONFIG_AUTOLIMIT_H (0x1 << 18)
197 /*
198  * @brief Macro defines for SCT control register
199  */
200 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
201 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
202 
203 #define SCT_CTRL_STOP_L (1 << 1)
204 #define SCT_CTRL_HALT_L (1 << 2)
205 #define SCT_CTRL_CLRCTR_L (1 << 3)
206 #define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4)
207 #define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5)
209 #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0
210 #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
211 #define SCT_CTRL_STOP_H (1 << 17)
212 #define SCT_CTRL_HALT_H (1 << 18)
213 #define SCT_CTRL_CLRCTR_H (1 << 19)
214 #define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
215 #define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21)
217 /*
218  * @brief Macro defines for SCT Conflict resolution register
219  */
220 #define SCT_RES_NOCHANGE (0)
221 #define SCT_RES_SET_OUTPUT (1)
222 #define SCT_RES_CLEAR_OUTPUT (2)
223 #define SCT_RES_TOGGLE_OUTPUT (3)
224 
228 typedef enum CHIP_SCT_MATCH_REG {
235 
239 typedef enum CHIP_SCT_EVENT {
240  SCT_EVT_0 = (1 << 0),
241  SCT_EVT_1 = (1 << 1),
242  SCT_EVT_2 = (1 << 2),
243  SCT_EVT_3 = (1 << 3),
244  SCT_EVT_4 = (1 << 4)
246 
253 STATIC INLINE void Chip_SCT_Config(LPC_SCT_T *pSCT, uint32_t value)
254 {
255  pSCT->CONFIG = value;
256 }
257 
270 void Chip_SCT_SetClrControl(LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena);
271 
286 void Chip_SCT_SetConflictResolution(LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value);
287 
294 STATIC INLINE void Chip_SCT_SetCount(LPC_SCT_T *pSCT, uint32_t count)
295 {
296  pSCT->COUNT_U = count;
297 }
298 
305 STATIC INLINE void Chip_SCT_SetCountL(LPC_SCT_T *pSCT, uint16_t count)
306 {
307  pSCT->COUNT_L = count;
308 }
309 
316 STATIC INLINE void Chip_SCT_SetCountH(LPC_SCT_T *pSCT, uint16_t count)
317 {
318  pSCT->COUNT_H = count;
319 }
320 
329 {
330  pSCT->MATCH[n].U = value;
331 }
332 
339 STATIC INLINE void Chip_SCT_SetControl(LPC_SCT_T *pSCT, uint32_t value)
340 {
341  pSCT->CTRL_U |= value;
342 }
343 
350 STATIC INLINE void Chip_SCT_ClearControl(LPC_SCT_T *pSCT, uint32_t value)
351 {
352  pSCT->CTRL_U &= ~(value);
353 }
354 
363 {
364  pSCT->MATCHREL[n].U = value;
365 }
366 
374 {
375  pSCT->EVEN |= evt;
376 }
377 
385 {
386  pSCT->EVEN &= ~(evt);
387 }
388 
396 {
397  pSCT->EVFLAG |= evt;
398 }
399 
405 void Chip_SCT_Init(LPC_SCT_T *pSCT);
406 
412 void Chip_SCT_DeInit(LPC_SCT_T *pSCT);
413 
418 #ifdef __cplusplus
419 }
420 
421 #endif
422 
423 #endif /* __SCT_18XX_43XX_H_ */