LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
rgu_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx Reset Generator Unit driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __RGU_18XX_43XX_H_
33 #define __RGU_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef enum CHIP_RGU_RST {
91 #ifdef CHIP_LPC43XX
92  RGU_M0APP_RST,
93  RGU_SGPIO_RST,
94  RGU_SPI_RST,
95  RGU_ADCHS_RST = 60,
96 #endif
99 
103 typedef struct {
104  __I uint32_t RESERVED0[64];
105  __O uint32_t RESET_CTRL[2];
106  __I uint32_t RESERVED1[2];
107  __IO uint32_t RESET_STATUS[4];
108  __I uint32_t RESERVED2[12];
109  __I uint32_t RESET_ACTIVE_STATUS[2];
110  __I uint32_t RESERVED3[170];
111  __IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];
112 } LPC_RGU_T;
113 
120 {
121  LPC_RGU->RESET_CTRL[ResetNumber >> 5] = 1 << (ResetNumber & 31);
122  /* Reset will auto clear after 1 clock cycle */
123 }
124 
131 {
132  return !(LPC_RGU->RESET_ACTIVE_STATUS[ResetNumber >> 5] & (1 << (ResetNumber & 31)));
133 }
134 
146 {
147  LPC_RGU->RESET_CTRL[ResetNumber >> 5] = 0;
148 }
149 
154 #ifdef __cplusplus
155 }
156 #endif
157 
158 #endif /* __RGU_18XX_43XX_H_ */