LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/rtc_18xx_43xx.h Source File

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rtc_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx RTC driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __RTC_18XX_43XX_H_
33 #define __RTC_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
44 #define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
45
49 typedef enum {
50 RTC_TIMETYPE_SECOND,
51 RTC_TIMETYPE_MINUTE,
52 RTC_TIMETYPE_HOUR,
53 RTC_TIMETYPE_DAYOFMONTH,
54 RTC_TIMETYPE_DAYOFWEEK,
55 RTC_TIMETYPE_DAYOFYEAR,
56 RTC_TIMETYPE_MONTH,
57 RTC_TIMETYPE_YEAR,
58 RTC_TIMETYPE_LAST
59 } RTC_TIMEINDEX_T;
60
61 #if RTC_EV_SUPPORT
62
65 typedef enum {
66 RTC_EV_CHANNEL_1 = 0,
67 RTC_EV_CHANNEL_2,
68 RTC_EV_CHANNEL_3,
69 RTC_EV_CHANNEL_NUM,
70 } RTC_EV_CHANNEL_T;
71 #endif /*RTC_EV_SUPPORT*/
72
76 typedef struct {
77 __IO uint32_t ILR;
78 __I uint32_t RESERVED0;
79 __IO uint32_t CCR;
80 __IO uint32_t CIIR;
81 __IO uint32_t AMR;
82 __I uint32_t CTIME[3];
83 __IO uint32_t TIME[RTC_TIMETYPE_LAST];
84 __IO uint32_t CALIBRATION;
85 __I uint32_t RESERVED1[7];
86 __IO uint32_t ALRM[RTC_TIMETYPE_LAST];
87 #if RTC_EV_SUPPORT
88 __IO uint32_t ERSTATUS;
89 __IO uint32_t ERCONTROL;
90 __I uint32_t ERCOUNTERS;
91 __I uint32_t RESERVED2;
92 __I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM];
93 __I uint32_t RESERVED3;
94 __I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM];
95 #endif /*RTC_EV_SUPPORT*/
96 } LPC_RTC_T;
97
101 typedef struct {
102 __IO uint32_t REGFILE[64];
103 } LPC_REGFILE_T;
104
105 /*
106 * @brief ILR register definitions
107 */
109 #define RTC_ILR_BITMASK ((0x00000003))
110
111 #define RTC_IRL_RTCCIF ((1 << 0))
112
113 #define RTC_IRL_RTCALF ((1 << 1))
114
115 /*
116 * @brief CCR register definitions
117 */
119 #define RTC_CCR_BITMASK ((0x00000013))
120
121 #define RTC_CCR_CLKEN ((1 << 0))
122
123 #define RTC_CCR_CTCRST ((1 << 1))
124
125 #define RTC_CCR_CCALEN ((1 << 4))
126
127 /*
128 * @brief CIIR and AMR register definitions
129 */
131 #define RTC_AMR_CIIR_IMSEC ((1 << 0))
132
133 #define RTC_AMR_CIIR_IMMIN ((1 << 1))
134
135 #define RTC_AMR_CIIR_IMHOUR ((1 << 2))
136
137 #define RTC_AMR_CIIR_IMDOM ((1 << 3))
138
139 #define RTC_AMR_CIIR_IMDOW ((1 << 4))
140
141 #define RTC_AMR_CIIR_IMDOY ((1 << 5))
142
143 #define RTC_AMR_CIIR_IMMON ((1 << 6))
144
145 #define RTC_AMR_CIIR_IMYEAR ((1 << 7))
146
147 #define RTC_AMR_CIIR_BITMASK ((0xFF))
148
149 /*
150 * @brief RTC_AUX register definitions
151 */
153 #define RTC_AUX_RTC_OSCF ((1 << 4))
154
155 /*
156 * @brief RTC_AUXEN register definitions
157 */
159 #define RTC_AUXEN_RTC_OSCFEN ((1 << 4))
160
161 /*
162 * @brief Consolidated Time Register 0 definitions
163 */
164 #define RTC_CTIME0_SECONDS_MASK ((0x3F))
165 #define RTC_CTIME0_MINUTES_MASK ((0x3F00))
166 #define RTC_CTIME0_HOURS_MASK ((0x1F0000))
167 #define RTC_CTIME0_DOW_MASK ((0x7000000))
168
169 /*
170 * @brief Consolidated Time Register 1 definitions
171 */
172 #define RTC_CTIME1_DOM_MASK ((0x1F))
173 #define RTC_CTIME1_MONTH_MASK ((0xF00))
174 #define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
175
176 /*
177 * @brief Consolidated Time Register 2 definitions
178 */
179 #define RTC_CTIME2_DOY_MASK ((0xFFF))
180
181 /*
182 * @brief Time Counter Group and Alarm register group
183 */
185 #define RTC_SEC_MASK (0x0000003F)
186
187 #define RTC_MIN_MASK (0x0000003F)
188
189 #define RTC_HOUR_MASK (0x0000001F)
190
191 #define RTC_DOM_MASK (0x0000001F)
192
193 #define RTC_DOW_MASK (0x00000007)
194
195 #define RTC_DOY_MASK (0x000001FF)
196
197 #define RTC_MONTH_MASK (0x0000000F)
198
199 #define RTC_YEAR_MASK (0x00000FFF)
200
201 #define RTC_SECOND_MAX 59
202 #define RTC_MINUTE_MAX 59
203 #define RTC_HOUR_MAX 23
204 #define RTC_MONTH_MIN 1
205 #define RTC_MONTH_MAX 12
206 #define RTC_DAYOFMONTH_MIN 1
207 #define RTC_DAYOFMONTH_MAX 31
208 #define RTC_DAYOFWEEK_MAX 6
209 #define RTC_DAYOFYEAR_MIN 1
210 #define RTC_DAYOFYEAR_MAX 366
211 #define RTC_YEAR_MAX 4095
213 /*
214 * @brief Calibration register
215 */
216
217 #define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
218
219 #define RTC_CALIBRATION_LIBDIR ((1 << 17))
220
221 #define RTC_CALIBRATION_MAX ((0x20000))
222
223 #define RTC_CALIB_DIR_FORWARD ((uint8_t) (0))
224 #define RTC_CALIB_DIR_BACKWARD ((uint8_t) (1))
225
226 #if RTC_EV_SUPPORT
227 /*
228 * @brief Event Monitor/Recorder Control register
229 */
231 #define RTC_ERCTRL_BITMASK ((uint32_t) 0xC0F03C0F)
232
233 #define RTC_ERCTRL_INTWAKE_EN ((uint32_t) (1 << 0))
234
235 #define RTC_ERCTRL_GPCLEAR_EN ((uint32_t) (1 << 1))
236
237 #define RTC_ERCTRL_POL_NEGATIVE (0) /* Event as positive edge */
238 #define RTC_ERCTRL_POL_POSITIVE ((uint32_t) (1 << 2)) /* Event as negative edge */
239
240 #define RTC_ERCTRL_INPUT_EN ((uint32_t) (1 << 3))
241
242 #define RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch) ((uint32_t) (0x0F << (10 * ch)))
243 #define RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) ((uint32_t) (flag << (10 * ch)))
244
246 #define RTC_ERCTRL_MODE_MASK (((uint32_t) 3) << 30)
247 #define RTC_ERCTRL_MODE_CLK_DISABLE (((uint32_t) 0) << 30)
248 #define RTC_ERCTRL_MODE_16HZ (((uint32_t) 1) << 30)
249 #define RTC_ERCTRL_MODE_64HZ (((uint32_t) 2) << 30)
250 #define RTC_ERCTRL_MODE_1KHZ (((uint32_t) 3) << 30)
251 #define RTC_ERCTRL_MODE(n) (((uint32_t) n) << 30)
252
253 /*
254 * @brief Event Monitor/Recorder Status register
255 */
257 #define RTC_ERSTATUS_CHANNEL_EV(ch) ((uint32_t) (1 << ch)) /* At least 1 event has occurred on a specific channel */
258
259 #define RTC_ERSTATUS_GPCLEARED ((uint32_t) (1 << 3))
260
261 #define RTC_ERSTATUS_WAKEUP ((uint32_t) (((uint32_t) 1) << 31))
262
263 /*
264 * @brief Event Monitor/Recorder Counter register
265 */
267 #define RTC_ER_COUNTER(ch, n) ((uint32_t) ((n >> (8 * ch)) & 0x07))
268
269 /*
270 * @brief Event Monitor/Recorder TimeStamp register
271 */
272 #define RTC_ER_TIMESTAMP_SEC(n) ((uint32_t) (n & 0x3F))
273 #define RTC_ER_TIMESTAMP_MIN(n) ((uint32_t) ((n >> 6) & 0x3F))
274 #define RTC_ER_TIMESTAMP_HOUR(n) ((uint32_t) ((n >> 12) & 0x1F))
275 #define RTC_ER_TIMESTAMP_DOY(n) ((uint32_t) ((n >> 17) & 0x1FF))
276
280 typedef enum IP_RTC_EV_MODE {
281 RTC_EV_MODE_DISABLE = 0,
282 RTC_EV_MODE_ENABLE_16HZ = 1,
283 RTC_EV_MODE_ENABLE_64HZ = 2,
284 RTC_EV_MODE_ENABLE_1KHZ = 3,
285 RTC_EV_MODE_LAST,
286 } RTC_EV_MODE_T;
287
291 typedef struct {
292 uint8_t sec;
293 uint8_t min;
294 uint8_t hour;
295 uint16_t dayofyear;
296 } RTC_EV_TIMESTAMP_T;
297
298 #endif /*RTC_EV_SUPPORT*/
299
305 typedef enum {
306 RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF,
307 RTC_INT_ALARM = RTC_IRL_RTCALF
308 } RTC_INT_OPT_T;
309
310 typedef struct {
311 uint32_t time[RTC_TIMETYPE_LAST];
312 } RTC_TIME_T;
313
319 void Chip_RTC_ResetClockTickCounter(LPC_RTC_T *pRTC);
320
329 void Chip_RTC_Enable(LPC_RTC_T *pRTC, FunctionalState NewState);
330
338 void Chip_RTC_CntIncrIntConfig(LPC_RTC_T *pRTC, uint32_t cntrMask, FunctionalState NewState);
339
347 void Chip_RTC_AlarmIntConfig(LPC_RTC_T *pRTC, uint32_t alarmMask, FunctionalState NewState);
348
356 STATIC INLINE void Chip_RTC_SetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t TimeValue)
357 {
358 pRTC->TIME[Timetype] = TimeValue;
359 }
360
367 STATIC INLINE uint32_t Chip_RTC_GetTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype)
368 {
369 return pRTC->TIME[Timetype];
370 }
371
378 void Chip_RTC_SetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
379
386 void Chip_RTC_GetFullTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
387
395 STATIC INLINE void Chip_RTC_SetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype, uint32_t ALValue)
396 {
397 pRTC->ALRM[Timetype] = ALValue;
398 }
399
406 STATIC INLINE uint32_t Chip_RTC_GetAlarmTime(LPC_RTC_T *pRTC, RTC_TIMEINDEX_T Timetype)
407 {
408 return pRTC->ALRM[Timetype];
409 }
410
417 void Chip_RTC_SetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
418
425 void Chip_RTC_GetFullAlarmTime(LPC_RTC_T *pRTC, RTC_TIME_T *pFullTime);
426
438 STATIC INLINE void Chip_REGFILE_Write(LPC_REGFILE_T *pRegFile, uint8_t index, uint32_t value)
439 {
440 pRegFile->REGFILE[index] = value;
441 }
442
453 STATIC INLINE uint32_t Chip_REGFILE_Read(LPC_REGFILE_T *pRegFile, uint8_t index)
454 {
455 return pRegFile->REGFILE[index];
456 }
457
466 void Chip_RTC_CalibCounterCmd(LPC_RTC_T *pRTC, FunctionalState NewState);
467
477 STATIC INLINE void Chip_RTC_CalibConfig(LPC_RTC_T *pRTC, uint32_t CalibValue, uint8_t CalibDir)
478 {
479 pRTC->CALIBRATION = ((CalibValue - 1) & RTC_CALIBRATION_CALVAL_MASK)
480 | ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);
481 }
482
491 STATIC INLINE void Chip_RTC_ClearIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
492 {
493 pRTC->ILR = IntType;
494 }
495
504 STATIC INLINE IntStatus Chip_RTC_GetIntPending(LPC_RTC_T *pRTC, uint32_t IntType)
505 {
506 return (pRTC->ILR & IntType) ? SET : RESET;
507 }
508
509 #if RTC_EV_SUPPORT
510
520 STATIC INLINE void Chip_RTC_EV_Config(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, uint32_t flag)
521 {
522 uint32_t temp;
523
524 temp = pRTC->ERCONTROL & (~(RTC_ERCTRL_CHANNEL_CONFIG_BITMASK(ch))) & RTC_ERCTRL_BITMASK;
525 pRTC->ERCONTROL = temp | (RTC_ERCTRL_CHANNEL_CONFIG(ch, flag) & RTC_ERCTRL_BITMASK);
526 }
527
534 STATIC INLINE void Chip_RTC_EV_SetMode(LPC_RTC_T *pRTC, RTC_EV_MODE_T mode)
535 {
536 uint32_t temp;
537
538 temp = pRTC->ERCONTROL & (~RTC_ERCTRL_MODE_MASK) & RTC_ERCTRL_BITMASK;
539 pRTC->ERCONTROL = temp | RTC_ERCTRL_MODE(mode);
540 }
541
547 STATIC INLINE uint8_t Chip_RTC_EV_GetStatus(LPC_RTC_T *pRTC)
548 {
549 return pRTC->ERSTATUS & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
550 }
551
558 STATIC INLINE void Chip_RTC_EV_ClearStatus(LPC_RTC_T *pRTC, uint32_t flag)
559 {
560 pRTC->ERSTATUS = flag & (RTC_ERSTATUS_GPCLEARED | RTC_ERSTATUS_WAKEUP);
561 }
562
569 STATIC INLINE FlagStatus Chip_RTC_EV_GetChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
570 {
571 return (pRTC->ERSTATUS & RTC_ERSTATUS_CHANNEL_EV(ch)) ? SET : RESET;
572 }
573
580 STATIC INLINE void Chip_RTC_EV_ClearChannelStatus(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
581 {
582 pRTC->ERSTATUS = RTC_ERSTATUS_CHANNEL_EV(ch);
583 }
584
591 STATIC INLINE uint8_t Chip_RTC_EV_GetCounter(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch)
592 {
593 return RTC_ER_COUNTER(ch, pRTC->ERCOUNTERS);
594 }
595
603 void Chip_RTC_EV_GetFirstTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp);
604
612 void Chip_RTC_EV_GetLastTimeStamp(LPC_RTC_T *pRTC, RTC_EV_CHANNEL_T ch, RTC_EV_TIMESTAMP_T *pTimeStamp);
613
614 #endif /*RTC_EV_SUPPORT*/
615
621 void Chip_RTC_Init(LPC_RTC_T *pRTC);
622
628 void Chip_RTC_DeInit(LPC_RTC_T *pRTC);
629
634 #ifdef __cplusplus
635 }
636 #endif
637
638 #endif /* __RTC_18XX_43XX_H_ */