LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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chip_18xx_43xx
clock_18xx_43xx.h
Go to the documentation of this file.
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/*
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* @brief LPC18xx/43xx clock driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CLOCK_18XX_43XX_H_
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#define __CLOCK_18XX_43XX_H_
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#include "
cguccu_18xx_43xx.h
"
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* Internal oscillator frequency */
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#define CGU_IRC_FREQ (12000000)
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#ifndef MAX_CLOCK_FREQ
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#if defined(CHIP_LPC43XX)
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#define MAX_CLOCK_FREQ (204000000)
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#else
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#define MAX_CLOCK_FREQ (180000000)
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#endif
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#endif
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#define PLL_MIN_CCO_FREQ 156000000
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#define PLL_MAX_CCO_FREQ 320000000
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typedef struct {
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int
ctrl
;
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CHIP_CGU_CLKIN_T
srcin
;
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int
nsel
;
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int
psel
;
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int
msel
;
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uint32_t
fin
;
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uint32_t
fout
;
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uint32_t
fcco
;
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}
PLL_PARAM_T
;
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void
Chip_Clock_EnableCrystal
(
void
);
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void
Chip_Clock_DisableCrystal
(
void
);
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uint32_t
Chip_Clock_SetupMainPLLHz
(
CHIP_CGU_CLKIN_T
Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
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uint32_t
Chip_Clock_SetupMainPLLMult
(
CHIP_CGU_CLKIN_T
Input, uint32_t mult);
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uint32_t
Chip_Clock_GetMainPLLHz
(
void
);
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__STATIC_INLINE
void
Chip_Clock_DisableMainPLL
(
void
)
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{
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/* power down main PLL */
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LPC_CGU
->PLL1_CTRL |= 1;
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}
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__STATIC_INLINE
void
Chip_Clock_EnableMainPLL
(
void
)
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{
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/* power up main PLL */
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LPC_CGU
->PLL1_CTRL &= ~1;
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}
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__STATIC_INLINE
void
Chip_Clock_SetupMainPLL
(
const
PLL_PARAM_T
*ppll)
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{
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/* power up main PLL */
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LPC_CGU
->PLL1_CTRL = ppll->
ctrl
| ((uint32_t) ppll->
srcin
<< 24) | (ppll->
msel
<< 16) | (ppll->
nsel
<< 12) | (ppll->
psel
<< 8);
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}
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void
Chip_Clock_SetDivider
(
CHIP_CGU_IDIV_T
Divider,
CHIP_CGU_CLKIN_T
Input, uint32_t Divisor);
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CHIP_CGU_CLKIN_T
Chip_Clock_GetDividerSource
(
CHIP_CGU_IDIV_T
Divider);
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uint32_t
Chip_Clock_GetDividerDivisor
(
CHIP_CGU_IDIV_T
Divider);
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uint32_t
Chip_Clock_GetClockInputHz
(
CHIP_CGU_CLKIN_T
input);
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uint32_t
Chip_Clock_GetBaseClocktHz
(
CHIP_CGU_BASE_CLK_T
clock);
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void
Chip_Clock_SetBaseClock
(
CHIP_CGU_BASE_CLK_T
BaseClock,
CHIP_CGU_CLKIN_T
Input,
bool
autoblocken,
bool
powerdn);
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void
Chip_Clock_GetBaseClockOpts
(
CHIP_CGU_BASE_CLK_T
BaseClock,
CHIP_CGU_CLKIN_T
*Input,
bool
*autoblocken,
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bool
*powerdn);
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CHIP_CGU_CLKIN_T
Chip_Clock_GetBaseClock
(
CHIP_CGU_BASE_CLK_T
BaseClock);
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void
Chip_Clock_EnableBaseClock
(
CHIP_CGU_BASE_CLK_T
BaseClock);
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void
Chip_Clock_DisableBaseClock
(
CHIP_CGU_BASE_CLK_T
BaseClock);
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bool
Chip_Clock_IsBaseClockEnabled
(
CHIP_CGU_BASE_CLK_T
BaseClock);
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void
Chip_Clock_EnableOpts
(
CHIP_CCU_CLK_T
clk,
bool
autoen,
bool
wakeupen,
int
div);
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void
Chip_Clock_Enable
(
CHIP_CCU_CLK_T
clk);
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void
Chip_Clock_RTCEnable
(
void
);
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void
Chip_Clock_Disable
(
CHIP_CCU_CLK_T
clk);
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uint32_t
Chip_Clock_GetRate
(
CHIP_CCU_CLK_T
clk);
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uint32_t
Chip_Clock_GetEMCRate
(
void
);
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void
Chip_Clock_StartPowerDown
(
void
);
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void
Chip_Clock_ClearPowerDown
(
void
);
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typedef
struct
{
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uint32_t
ctrl
;
/* Default control word for PLL */
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uint32_t
mdiv
;
/* Default M-divider value for PLL */
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uint32_t
ndiv
;
/* Default NP-divider value for PLL */
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uint32_t
fract
;
/* Default fractional value for audio PLL only */
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uint32_t
freq
;
/* Output frequency of the pll */
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}
CGU_USBAUDIO_PLL_SETUP_T
;
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void
Chip_Clock_SetupPLL
(
CHIP_CGU_CLKIN_T
Input,
CHIP_CGU_USB_AUDIO_PLL_T
pllnum,
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const
CGU_USBAUDIO_PLL_SETUP_T
*pPLLSetup);
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void
Chip_Clock_EnablePLL
(
CHIP_CGU_USB_AUDIO_PLL_T
pllnum);
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void
Chip_Clock_DisablePLL
(
CHIP_CGU_USB_AUDIO_PLL_T
pllnum);
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#define CGU_PLL_LOCKED (1 << 0)
/* PLL locked status */
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#define CGU_PLL_FR (1 << 1)
/* PLL free running indicator status */
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uint32_t
Chip_Clock_GetPLLStatus
(
CHIP_CGU_USB_AUDIO_PLL_T
pllnum);
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int
Chip_Clock_CalcMainPLLValue
(uint32_t freq,
PLL_PARAM_T
*ppll);
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__STATIC_INLINE
int
Chip_Clock_MainPLLLocked
(
void
)
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{
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/* Return true if locked */
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return
(
LPC_CGU
->PLL1_STAT & 1) != 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __CLOCK_18XX_43XX_H_ */
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