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LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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Data Structures | |
| struct | LPC_SCT_T |
| State Configurable Timer register block structure. More... | |
Macros | |
| #define | CONFIG_SCT_nEV (16) |
| #define | CONFIG_SCT_nRG (16) |
| #define | CONFIG_SCT_nOU (16) |
| #define | SCT_CONFIG_16BIT_COUNTER 0x00000000 |
| #define | SCT_CONFIG_32BIT_COUNTER 0x00000001 |
| #define | SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) |
| #define | SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) |
| #define | SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) |
| #define | SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) |
| #define | SCT_CONFIG_NORELOADL_U (0x1 << 7) |
| #define | SCT_CONFIG_NORELOADH (0x1 << 8) |
| #define | SCT_CONFIG_AUTOLIMIT_L (0x1 << 17) |
| #define | SCT_CONFIG_AUTOLIMIT_H (0x1 << 18) |
| #define | COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 |
| #define | COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 |
| #define | COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 |
| #define | COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 |
| #define | SCT_CTRL_STOP_L (1 << 1) |
| #define | SCT_CTRL_HALT_L (1 << 2) |
| #define | SCT_CTRL_CLRCTR_L (1 << 3) |
| #define | SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) |
| #define | SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) |
| #define | SCT_CTRL_STOP_H (1 << 17) |
| #define | SCT_CTRL_HALT_H (1 << 18) |
| #define | SCT_CTRL_CLRCTR_H (1 << 19) |
| #define | SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20) |
| #define | SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) |
| #define | SCT_RES_NOCHANGE (0) |
| #define | SCT_RES_SET_OUTPUT (1) |
| #define | SCT_RES_CLEAR_OUTPUT (2) |
| #define | SCT_RES_TOGGLE_OUTPUT (3) |
Enumerations | |
| enum | CHIP_SCT_MATCH_REG_T { SCT_MATCH_0 = 0, SCT_MATCH_1 = 1, SCT_MATCH_2 = 2, SCT_MATCH_3 = 3, SCT_MATCH_4 = 4 } |
| enum | CHIP_SCT_EVENT_T { SCT_EVT_0 = (1 << 0), SCT_EVT_1 = (1 << 1), SCT_EVT_2 = (1 << 2), SCT_EVT_3 = (1 << 3), SCT_EVT_4 = (1 << 4) } |
Functions | |
| STATIC INLINE void | Chip_SCT_Config (LPC_SCT_T *pSCT, uint32_t value) |
| Configures the State Configurable Timer. More... | |
| void | Chip_SCT_SetClrControl (LPC_SCT_T *pSCT, uint32_t value, FunctionalState ena) |
| Set or Clear the Control register. More... | |
| void | Chip_SCT_SetConflictResolution (LPC_SCT_T *pSCT, uint8_t outnum, uint8_t value) |
| Set the conflict resolution. More... | |
| STATIC INLINE void | Chip_SCT_SetCount (LPC_SCT_T *pSCT, uint32_t count) |
| Set unified count value in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_SetCountL (LPC_SCT_T *pSCT, uint16_t count) |
| Set lower count value in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_SetCountH (LPC_SCT_T *pSCT, uint16_t count) |
| Set higher count value in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_SetMatchCount (LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) |
| Set unified match count value in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_SetControl (LPC_SCT_T *pSCT, uint32_t value) |
| Set control register in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_ClearControl (LPC_SCT_T *pSCT, uint32_t value) |
| Clear control register in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_SetMatchReload (LPC_SCT_T *pSCT, CHIP_SCT_MATCH_REG_T n, uint32_t value) |
| Set unified match reload count value in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_EnableEventInt (LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) |
| Enable the interrupt for the specified event in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_DisableEventInt (LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) |
| Disable the interrupt for the specified event in State Configurable Timer. More... | |
| STATIC INLINE void | Chip_SCT_ClearEventFlag (LPC_SCT_T *pSCT, CHIP_SCT_EVENT_T evt) |
| Clear the specified event flag in State Configurable Timer. More... | |
| void | Chip_SCT_Init (LPC_SCT_T *pSCT) |
| Initializes the State Configurable Timer. More... | |
| void | Chip_SCT_DeInit (LPC_SCT_T *pSCT) |
| Deinitializes the State Configurable Timer. More... | |
| #define CONFIG_SCT_nEV (16) |
Number of events
Definition at line 47 of file sct_18xx_43xx.h.
| #define CONFIG_SCT_nOU (16) |
Number of outputs
Definition at line 49 of file sct_18xx_43xx.h.
| #define CONFIG_SCT_nRG (16) |
Number of match/compare registers
Definition at line 48 of file sct_18xx_43xx.h.
| #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 |
Definition at line 210 of file sct_18xx_43xx.h.
| #define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1 |
Definition at line 210 of file sct_18xx_43xx.h.
| #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 |
Direction for low or unified counter
Direction for high counter
Definition at line 209 of file sct_18xx_43xx.h.
| #define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 |
Direction for low or unified counter
Direction for high counter
Definition at line 209 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_16BIT_COUNTER 0x00000000 |
Operate as 2 16-bit counters
Definition at line 184 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_32BIT_COUNTER 0x00000001 |
Operate as 1 32-bit counter
Definition at line 185 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_AUTOLIMIT_H (0x1 << 18) |
Limits counter(L) based on MATCH0
Definition at line 195 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_AUTOLIMIT_L (0x1 << 17) |
Limits counter(L) based on MATCH0
Definition at line 194 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) |
Bus clock
Definition at line 187 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) |
Input clock selected in CLKSEL field
Definition at line 189 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) |
Input clock edge selected in CLKSEL field
Definition at line 190 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) |
SCT clock
Definition at line 188 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_NORELOADH (0x1 << 8) |
Operate as 1 32-bit counter
Definition at line 193 of file sct_18xx_43xx.h.
| #define SCT_CONFIG_NORELOADL_U (0x1 << 7) |
Operate as 1 32-bit counter
Definition at line 192 of file sct_18xx_43xx.h.
| #define SCT_CTRL_BIDIR_H | ( | x | ) | (((x) & 0x01) << 20) |
Definition at line 214 of file sct_18xx_43xx.h.
| #define SCT_CTRL_BIDIR_L | ( | x | ) | (((x) & 0x01) << 4) |
Bidirectional bit
Definition at line 206 of file sct_18xx_43xx.h.
| #define SCT_CTRL_CLRCTR_H (1 << 19) |
Clear high counter
Definition at line 213 of file sct_18xx_43xx.h.
| #define SCT_CTRL_CLRCTR_L (1 << 3) |
Clear low or unified counter
Definition at line 205 of file sct_18xx_43xx.h.
| #define SCT_CTRL_HALT_H (1 << 18) |
Halt high counter
Definition at line 212 of file sct_18xx_43xx.h.
| #define SCT_CTRL_HALT_L (1 << 2) |
Halt low counter
Definition at line 204 of file sct_18xx_43xx.h.
| #define SCT_CTRL_PRE_H | ( | x | ) | (((x) & 0xFF) << 21) |
Prescale clock for high counter
Definition at line 215 of file sct_18xx_43xx.h.
| #define SCT_CTRL_PRE_L | ( | x | ) | (((x) & 0xFF) << 5) |
Prescale clock for low or unified counter
Definition at line 207 of file sct_18xx_43xx.h.
| #define SCT_CTRL_STOP_H (1 << 17) |
Stop high counter
Definition at line 211 of file sct_18xx_43xx.h.
| #define SCT_CTRL_STOP_L (1 << 1) |
Stop low counter
Definition at line 203 of file sct_18xx_43xx.h.
| #define SCT_RES_CLEAR_OUTPUT (2) |
Definition at line 222 of file sct_18xx_43xx.h.
| #define SCT_RES_NOCHANGE (0) |
Definition at line 220 of file sct_18xx_43xx.h.
| #define SCT_RES_SET_OUTPUT (1) |
Definition at line 221 of file sct_18xx_43xx.h.
| #define SCT_RES_TOGGLE_OUTPUT (3) |
Definition at line 223 of file sct_18xx_43xx.h.
| enum CHIP_SCT_EVENT_T |
SCT Event values enum
| Enumerator | |
|---|---|
| SCT_EVT_0 |
Event 0 |
| SCT_EVT_1 |
Event 1 |
| SCT_EVT_2 |
Event 2 |
| SCT_EVT_3 |
Event 3 |
| SCT_EVT_4 |
Event 4 |
Definition at line 239 of file sct_18xx_43xx.h.
| enum CHIP_SCT_MATCH_REG_T |
SCT Match register values enum
| Enumerator | |
|---|---|
| SCT_MATCH_0 |
SCT Match register 0 |
| SCT_MATCH_1 |
SCT Match register 1 |
| SCT_MATCH_2 |
SCT Match register 2 |
| SCT_MATCH_3 |
SCT Match register 3 |
| SCT_MATCH_4 |
SCT Match register 4 |
Definition at line 228 of file sct_18xx_43xx.h.
Clear control register in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| value | : Value (ORed value of SCT_CTRL_* bits) |
Definition at line 350 of file sct_18xx_43xx.h.
| STATIC INLINE void Chip_SCT_ClearEventFlag | ( | LPC_SCT_T * | pSCT, |
| CHIP_SCT_EVENT_T | evt | ||
| ) |
Clear the specified event flag in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| evt | : Event value |
Definition at line 395 of file sct_18xx_43xx.h.
Configures the State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| value | : The 32-bit CONFIG register value |
Definition at line 253 of file sct_18xx_43xx.h.
| void Chip_SCT_DeInit | ( | LPC_SCT_T * | pSCT | ) |
Deinitializes the State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
Definition at line 57 of file sct_18xx_43xx.c.
| STATIC INLINE void Chip_SCT_DisableEventInt | ( | LPC_SCT_T * | pSCT, |
| CHIP_SCT_EVENT_T | evt | ||
| ) |
Disable the interrupt for the specified event in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| evt | : Event value |
Definition at line 384 of file sct_18xx_43xx.h.
| STATIC INLINE void Chip_SCT_EnableEventInt | ( | LPC_SCT_T * | pSCT, |
| CHIP_SCT_EVENT_T | evt | ||
| ) |
Enable the interrupt for the specified event in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| evt | : Event value |
Definition at line 373 of file sct_18xx_43xx.h.
| void Chip_SCT_Init | ( | LPC_SCT_T * | pSCT | ) |
Initializes the State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
Definition at line 51 of file sct_18xx_43xx.c.
| void Chip_SCT_SetClrControl | ( | LPC_SCT_T * | pSCT, |
| uint32_t | value, | ||
| FunctionalState | ena | ||
| ) |
Set or Clear the Control register.
| pSCT | : Pointer to SCT register block |
| value | : SCT Control register value |
| ena | : ENABLE - To set the fields specified by value : DISABLE - To clear the field specified by value |
Definition at line 63 of file sct_18xx_43xx.c.
| void Chip_SCT_SetConflictResolution | ( | LPC_SCT_T * | pSCT, |
| uint8_t | outnum, | ||
| uint8_t | value | ||
| ) |
Set the conflict resolution.
| pSCT | : Pointer to SCT register block |
| outnum | : Output number |
| value | : Output value
|
Definition at line 78 of file sct_18xx_43xx.c.
Set control register in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| value | : Value (ORed value of SCT_CTRL_* bits) |
Definition at line 339 of file sct_18xx_43xx.h.
Set unified count value in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| count | : The 32-bit count value |
Definition at line 294 of file sct_18xx_43xx.h.
Set higher count value in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| count | : The 16-bit count value |
Definition at line 316 of file sct_18xx_43xx.h.
Set lower count value in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| count | : The 16-bit count value |
Definition at line 305 of file sct_18xx_43xx.h.
| STATIC INLINE void Chip_SCT_SetMatchCount | ( | LPC_SCT_T * | pSCT, |
| CHIP_SCT_MATCH_REG_T | n, | ||
| uint32_t | value | ||
| ) |
Set unified match count value in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| n | : Match register value |
| value | : The 32-bit match count value |
Definition at line 328 of file sct_18xx_43xx.h.
| STATIC INLINE void Chip_SCT_SetMatchReload | ( | LPC_SCT_T * | pSCT, |
| CHIP_SCT_MATCH_REG_T | n, | ||
| uint32_t | value | ||
| ) |
Set unified match reload count value in State Configurable Timer.
| pSCT | : The base of SCT peripheral on the chip |
| n | : Match register value |
| value | : The 32-bit match count reload value |
Definition at line 362 of file sct_18xx_43xx.h.
1.8.3.1