32 #ifndef __GPDMA_18XX_43XX_H_
33 #define __GPDMA_18XX_43XX_H_
47 #define GPDMA_NUMBER_CHANNELS 8
58 __I uint32_t RESERVED1[3];
79 __I uint32_t RESERVED0[50];
86 #define GPDMA_DMACCxControl_TransferSize(n) (((n & 0xFFF) << 0))
87 #define GPDMA_DMACCxControl_SBSize(n) (((n & 0x07) << 12))
88 #define GPDMA_DMACCxControl_DBSize(n) (((n & 0x07) << 15))
89 #define GPDMA_DMACCxControl_SWidth(n) (((n & 0x07) << 18))
90 #define GPDMA_DMACCxControl_DWidth(n) (((n & 0x07) << 21))
91 #define GPDMA_DMACCxControl_SI ((1UL << 26))
92 #define GPDMA_DMACCxControl_DI ((1UL << 27))
93 #define GPDMA_DMACCxControl_SrcTransUseAHBMaster1 ((1UL << 24))
94 #define GPDMA_DMACCxControl_DestTransUseAHBMaster1 ((1UL << 25))
95 #define GPDMA_DMACCxControl_Prot1 ((1UL << 28))
96 #define GPDMA_DMACCxControl_Prot2 ((1UL << 29))
97 #define GPDMA_DMACCxControl_Prot3 ((1UL << 30))
98 #define GPDMA_DMACCxControl_I ((1UL << 31))
103 #define GPDMA_DMACConfig_E ((0x01))
104 #define GPDMA_DMACConfig_M ((0x02))
105 #define GPDMA_DMACConfig_BITMASK ((0x03))
110 #define GPDMA_DMACCxConfig_E ((1UL << 0))
111 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n & 0x1F) << 1))
112 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n & 0x1F) << 6))
113 #define GPDMA_DMACCxConfig_TransferType(n) (((n & 0x7) << 11))
114 #define GPDMA_DMACCxConfig_IE ((1UL << 14))
115 #define GPDMA_DMACCxConfig_ITC ((1UL << 15))
116 #define GPDMA_DMACCxConfig_L ((1UL << 16))
117 #define GPDMA_DMACCxConfig_A ((1UL << 17))
118 #define GPDMA_DMACCxConfig_H ((1UL << 18))
169 uint32_t TransferType;
180 #define GPDMA_CONN_MEMORY ((0UL))
181 #define GPDMA_CONN_MAT0_0 ((1UL))
182 #define GPDMA_CONN_UART0_Tx ((2UL))
183 #define GPDMA_CONN_MAT0_1 ((3UL))
184 #define GPDMA_CONN_UART0_Rx ((4UL))
185 #define GPDMA_CONN_MAT1_0 ((5UL))
186 #define GPDMA_CONN_UART1_Tx ((6UL))
187 #define GPDMA_CONN_MAT1_1 ((7UL))
188 #define GPDMA_CONN_UART1_Rx ((8UL))
189 #define GPDMA_CONN_MAT2_0 ((9UL))
190 #define GPDMA_CONN_UART2_Tx ((10UL))
191 #define GPDMA_CONN_MAT2_1 ((11UL))
192 #define GPDMA_CONN_UART2_Rx ((12UL))
193 #define GPDMA_CONN_MAT3_0 ((13UL))
194 #define GPDMA_CONN_UART3_Tx ((14UL))
195 #define GPDMA_CONN_SCT_0 ((15UL))
196 #define GPDMA_CONN_MAT3_1 ((16UL))
197 #define GPDMA_CONN_UART3_Rx ((17UL))
198 #define GPDMA_CONN_SCT_1 ((18UL))
199 #define GPDMA_CONN_SSP0_Rx ((19UL))
200 #define GPDMA_CONN_I2S_Tx_Channel_0 ((20UL))
201 #define GPDMA_CONN_SSP0_Tx ((21UL))
202 #define GPDMA_CONN_I2S_Rx_Channel_1 ((22UL))
203 #define GPDMA_CONN_SSP1_Rx ((23UL))
204 #define GPDMA_CONN_SSP1_Tx ((24UL))
205 #define GPDMA_CONN_ADC_0 ((25UL))
206 #define GPDMA_CONN_ADC_1 ((26UL))
207 #define GPDMA_CONN_DAC ((27UL))
208 #define GPDMA_CONN_I2S1_Tx_Channel_0 ((28UL))
209 #define GPDMA_CONN_I2S1_Rx_Channel_1 ((29UL))
214 #define GPDMA_BSIZE_1 ((0UL))
215 #define GPDMA_BSIZE_4 ((1UL))
216 #define GPDMA_BSIZE_8 ((2UL))
217 #define GPDMA_BSIZE_16 ((3UL))
218 #define GPDMA_BSIZE_32 ((4UL))
219 #define GPDMA_BSIZE_64 ((5UL))
220 #define GPDMA_BSIZE_128 ((6UL))
221 #define GPDMA_BSIZE_256 ((7UL))
226 #define GPDMA_WIDTH_BYTE ((0UL))
227 #define GPDMA_WIDTH_HALFWORD ((1UL))
228 #define GPDMA_WIDTH_WORD ((2UL))
233 #define DMA_CONTROLLER 0
234 #define SRC_PER_CONTROLLER 1
235 #define DST_PER_CONTROLLER 2
247 typedef struct DMA_TransferDescriptor {
349 uint32_t PeripheralConnection_ID);