32 #ifndef __I2S_18XX_43XX_H_
33 #define __I2S_18XX_43XX_H_
76 #define I2S_WORDWIDTH_8 (0UL << 0)
77 #define I2S_WORDWIDTH_16 (1UL << 0)
78 #define I2S_WORDWIDTH_32 (3UL << 0)
81 #define I2S_STEREO (0UL << 2)
82 #define I2S_MONO (1UL << 2)
85 #define I2S_MASTER_MODE (0UL << 5)
86 #define I2S_SLAVE_MODE (1UL << 5)
89 #define I2S_STOP_ENABLE (0UL << 3)
90 #define I2S_STOP_DISABLE (1UL << 3)
93 #define I2S_RESET_ENABLE (1UL << 4)
94 #define I2S_RESET_DISABLE (0UL << 4)
97 #define I2S_MUTE_ENABLE (1UL << 15)
98 #define I2S_MUTE_DISABLE (0UL << 15)
104 #define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0))
105 #define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1))
106 #define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3))
107 #define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))
110 #define I2S_DAO_MONO ((uint32_t) (1 << 2))
113 #define I2S_DAO_STOP ((uint32_t) (1 << 3))
116 #define I2S_DAO_RESET ((uint32_t) (1 << 4))
119 #define I2S_DAO_SLAVE ((uint32_t) (1 << 5))
122 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6))
123 #define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
126 #define I2S_DAO_MUTE ((uint32_t) (1 << 15))
132 #define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0))
133 #define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1))
134 #define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3))
135 #define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3))
138 #define I2S_DAI_MONO ((uint32_t) (1 << 2))
141 #define I2S_DAI_STOP ((uint32_t) (1 << 3))
144 #define I2S_DAI_RESET ((uint32_t) (1 << 4))
147 #define I2S_DAI_SLAVE ((uint32_t) (1 << 5))
150 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6))
151 #define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
156 #define I2S_STATE_IRQ ((uint32_t) (1))
157 #define I2S_STATE_DMA1 ((uint32_t) (1 << 1))
158 #define I2S_STATE_DMA2 ((uint32_t) (1 << 2))
159 #define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))
160 #define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16))
165 #define I2S_DMA1_RX_ENABLE ((uint32_t) (1))
166 #define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1))
167 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
168 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
173 #define I2S_DMA2_RX_ENABLE ((uint32_t) (1))
174 #define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1))
175 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
176 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
182 #define I2S_IRQ_RX_ENABLE ((uint32_t) (1))
183 #define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1))
184 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8))
185 #define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))
186 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16))
187 #define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))
192 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
193 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
194 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
195 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
200 #define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
201 #define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))
206 #define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
207 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
208 #define I2S_TXMODE_MCENA ((uint32_t) (1 << 3))
209 #define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
210 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
211 #define I2S_RXMODE_MCENA ((uint32_t) (1 << 3))
387 pI2S->
TXMODE = clksel | fpin | mcena;
407 pI2S->
RXMODE = clksel | fpin | mcena;
417 return (pI2S->
STATE >> 16) & 0xF;
427 return (pI2S->
STATE >> 8) & 0xF;
472 pI2S->
TXRATE = yDiv | (xDiv << 8);
491 pI2S->
RXRATE = yDiv | (xDiv << 8);