32 #ifndef __HSADC_18XX_43XX_H_
33 #define __HSADC_18XX_43XX_H_
70 __I uint32_t LAST_SAMPLE[6];
71 uint32_t RESERVED0[49];
74 uint32_t RESERVED1[61];
75 __I uint32_t FIFO_OUTPUT[16];
76 uint32_t RESERVED2[48];
77 __IO uint32_t DESCRIPTOR[2][8];
78 uint32_t RESERVED3[752];
82 #define HSADC_MAX_SAMPLEVAL 0xFFF
165 pHSADC->
DSCR_STS = (uint32_t) ((desc << 1) | table);
175 return (uint8_t) ((pHSADC->
DSCR_STS >> 1) & 0x7);
185 return (uint8_t) (pHSADC->
DSCR_STS & 1);
256 pHSADC->
CONFIG = (uint32_t) mask | (uint32_t) mode | (uint32_t) sync |
257 (uint32_t) chID | (uint32_t) (recoveryTime << 6);
279 #define HSADC_LS_DONE (1 << 0)
280 #define HSADC_LS_OVERRUN (1 << 1)
281 #define HSADC_LS_RANGE_IN (0 << 2)
282 #define HSADC_LS_RANGE_BELOW (1 << 2)
283 #define HSADC_LS_RANGE_ABOVE (2 << 2)
284 #define HSADC_LS_RANGE(val) ((val) & 0xC)
285 #define HSADC_LS_CROSSING_NONE (0 << 4)
286 #define HSADC_LS_CROSSING_DOWN (1 << 4)
287 #define HSADC_LS_CROSSING_UP (2 << 4)
288 #define HSADC_LS_CROSSING(val) ((val) & 0x30)
289 #define HSADC_LS_DATA(val) ((val) >> 6)
305 STATIC INLINE uint32_t Chip_HSADC_GetLastSample(LPC_HSADC_T *pHSADC, uint8_t channel)
307 return pHSADC->LAST_SAMPLE[channel];
383 #define HSADC_FIFO_SAMPLE_MASK (0xFFF)
384 #define HSADC_FIFO_SAMPLE(val) ((val) & 0xFFF)
385 #define HSADC_FIFO_CHAN_ID_MASK (0x7000)
386 #define HSADC_FIFO_CHAN_ID(val) (((val) >> 12) & 0x7)
387 #define HSADC_FIFO_EMPTY (0x1 << 15)
388 #define HSADC_FIFO_SHIFTPACKED(val) ((val) >> 16)
389 #define HSADC_FIFO_PACKEDMASK (1UL << 31)
402 STATIC INLINE uint32_t Chip_HSADC_GetFIFO(LPC_HSADC_T *pHSADC)
404 return pHSADC->FIFO_OUTPUT[0];
408 #define HSADC_DESC_CH(ch) (ch)
409 #define HSADC_DESC_HALT (1 << 3)
410 #define HSADC_DESC_INT (1 << 4)
411 #define HSADC_DESC_POWERDOWN (1 << 5)
412 #define HSADC_DESC_BRANCH_NEXT (0 << 6)
413 #define HSADC_DESC_BRANCH_FIRST (1 << 6)
414 #define HSADC_DESC_BRANCH_SWAP (2 << 6)
415 #define HSADC_DESC_MATCH(val) ((val) << 8)
416 #define HSADC_DESC_THRESH_NONE (0 << 22)
417 #define HSADC_DESC_THRESH_A (1 << 22)
418 #define HSADC_DESC_THRESH_B (2 << 22)
419 #define HSADC_DESC_RESET_TIMER (1 << 24)
420 #define HSADC_DESC_UPDATE_TABLE (1UL << 31)
438 STATIC INLINE void Chip_HSADC_SetupDescEntry(LPC_HSADC_T *pHSADC, uint8_t table,
439 uint8_t descNo, uint32_t desc)
441 pHSADC->DESCRIPTOR[table][descNo] = desc;
460 #define HSADC_INT0_FIFO_FULL (1 << 0)
461 #define HSADC_INT0_FIFO_EMPTY (1 << 1)
462 #define HSADC_INT0_FIFO_OVERFLOW (1 << 2)
463 #define HSADC_INT0_DSCR_DONE (1 << 3)
464 #define HSADC_INT0_DSCR_ERROR (1 << 4)
465 #define HSADC_INT0_ADC_OVF (1 << 5)
466 #define HSADC_INT0_ADC_UNF (1 << 6)
470 #define HSADC_INT1_THCMP_BRANGE(ch) (1 << ((ch * 5) + 0))
471 #define HSADC_INT1_THCMP_ARANGE(ch) (1 << ((ch * 5) + 1))
472 #define HSADC_INT1_THCMP_DCROSS(ch) (1 << ((ch * 5) + 2))
473 #define HSADC_INT1_THCMP_UCROSS(ch) (1 << ((ch * 5) + 3))
474 #define HSADC_INT1_OVERRUN(ch) (1 << ((ch * 5) + 4))
484 STATIC INLINE void Chip_HSADC_EnableInts(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t intMask)
486 pHSADC->INTS[intGrp].SET_EN = intMask;