LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/i2cm_18xx_43xx.h Source File

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i2cm_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx I2C driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __I2CM_18XX_43XX_H_
33 #define __I2CM_18XX_43XX_H_
34
35 #include "i2c_common_18xx_43xx.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
65 #define I2CM_XFER_OPTION_IGNORE_NACK 0x01
66
67 #define I2CM_XFER_OPTION_LAST_RX_ACK 0x02
68
77 #define I2CM_STATUS_OK 0x00
78 #define I2CM_STATUS_ERROR 0x01
79 #define I2CM_STATUS_NAK 0x02
80 #define I2CM_STATUS_BUS_ERROR 0x03
81 #define I2CM_STATUS_SLAVE_NAK 0x04
82 #define I2CM_STATUS_ARBLOST 0x05
83 #define I2CM_STATUS_BUSY 0xFF
92 typedef struct {
93 uint8_t slaveAddr;
94 uint8_t options;
95 uint16_t status;
96 uint16_t txSz;
98 uint16_t rxSz;
100 const uint8_t *txBuff;
101 uint8_t *rxBuff;
102 } I2CM_XFER_T;
103
110 void Chip_I2CM_Init(LPC_I2C_T *pI2C);
111
118 void Chip_I2CM_DeInit(LPC_I2C_T *pI2C);
119
130 static INLINE void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
131 {
132 pI2C->SCLH = (uint32_t) sclH;
133 pI2C->SCLL = (uint32_t) sclL;
134 }
135
148 void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed);
149
157 static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C)
158 {
159 pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
160 }
161
168 static INLINE void Chip_I2CM_ResetControl(LPC_I2C_T *pI2C)
169 {
170 /* Reset STA, AA and SI. Stop flag should not be cleared as it is a reserved bit */
171 pI2C->CONCLR = I2C_CON_SI | I2C_CON_STA | I2C_CON_AA;
172
173 }
174
184 static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data)
185 {
186 pI2C->DAT = (uint32_t) data;
187 }
188
197 static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C)
198 {
199 return (uint8_t) (pI2C->DAT & I2C_I2DAT_BITMASK);
200 }
201
209 static INLINE void Chip_I2CM_NackNextByte(LPC_I2C_T *pI2C)
210 {
211 pI2C->CONCLR = I2C_CON_AA;
212 }
213
220 static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C)
221 {
222 pI2C->CONSET = I2C_CON_STO;
223 }
224
237 static INLINE void Chip_I2CM_ForceStart(LPC_I2C_T *pI2C)
238 {
239 /* check if we are pending on start */
240 if (pI2C->CONSET & I2C_CON_STA) {
241 pI2C->CONSET = I2C_CON_STO;
242 }
243 else {
244 Chip_I2CM_SendStart(pI2C);
245 }
246 }
247
255 static INLINE void Chip_I2CM_SendStartAfterStop(LPC_I2C_T *pI2C)
256 {
257 pI2C->CONSET = I2C_CON_STO | I2C_CON_STA;
258 }
259
266 static INLINE uint32_t Chip_I2CM_StateChanged(LPC_I2C_T *pI2C)
267 {
268 return pI2C->CONSET & I2C_CON_SI;
269 }
270
277 static INLINE void Chip_I2CM_ClearSI(LPC_I2C_T *pI2C)
278 {
279 /* Stop flag should not be cleared as it is a reserved bit */
280 pI2C->CONCLR = I2C_CON_SI | I2C_CON_STA;
281 }
282
290 static INLINE uint32_t Chip_I2CM_BusFree(LPC_I2C_T *pI2C)
291 {
292 return !(pI2C->CONSET & I2C_CON_STO);
293 }
294
302 static INLINE uint32_t Chip_I2CM_GetCurState(LPC_I2C_T *pI2C)
303 {
304 return pI2C->STAT & I2C_STAT_CODE_BITMASK;
305 }
306
313 static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C)
314 {
315 pI2C->CONCLR = I2C_CON_I2EN;
316 }
317
329 uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
330
369 void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
370
379 uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
380
394 uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len);
395
409 uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len);
410
415 #ifdef __cplusplus
416 }
417 #endif
418
419 #endif /* __I2C_18XX_43XX_H_ */