LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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chip_18xx_43xx
pinint_18xx_43xx.h
Go to the documentation of this file.
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/*
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* @brief LPC18xx/43xx Pin Interrupt and Pattern Match Registers and driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __PININT_18XX_43XX_H_
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#define __PININT_18XX_43XX_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
struct
{
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__IO uint32_t
ISEL
;
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__IO uint32_t
IENR
;
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__IO uint32_t
SIENR
;
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__IO uint32_t
CIENR
;
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__IO uint32_t
IENF
;
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__IO uint32_t
SIENF
;
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__IO uint32_t
CIENF
;
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__IO uint32_t
RISE
;
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__IO uint32_t
FALL
;
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__IO uint32_t
IST
;
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}
LPC_PIN_INT_T
;
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#define PININTCH0 (1 << 0)
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#define PININTCH1 (1 << 1)
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#define PININTCH2 (1 << 2)
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#define PININTCH3 (1 << 3)
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#define PININTCH4 (1 << 4)
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#define PININTCH5 (1 << 5)
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#define PININTCH6 (1 << 6)
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#define PININTCH7 (1 << 7)
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#define PININTCH(ch) (1 << (ch))
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STATIC
INLINE
void
Chip_PININT_Init
(
LPC_PIN_INT_T
*pPININT) {}
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STATIC
INLINE
void
Chip_PININT_DeInit
(
LPC_PIN_INT_T
*pPININT) {}
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STATIC
INLINE
void
Chip_PININT_SetPinModeEdge
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
ISEL
&= ~pins;
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}
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STATIC
INLINE
void
Chip_PININT_SetPinModeLevel
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
ISEL
|= pins;
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}
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STATIC
INLINE
uint32_t
Chip_PININT_GetHighEnabled
(
LPC_PIN_INT_T
*pPININT)
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{
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return
pPININT->
IENR
;
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}
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STATIC
INLINE
void
Chip_PININT_EnableIntHigh
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
SIENR
= pins;
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}
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STATIC
INLINE
void
Chip_PININT_DisableIntHigh
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
CIENR
= pins;
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}
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STATIC
INLINE
uint32_t
Chip_PININT_GetLowEnabled
(
LPC_PIN_INT_T
*pPININT)
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{
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return
pPININT->
IENF
;
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}
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STATIC
INLINE
void
Chip_PININT_EnableIntLow
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
SIENF
= pins;
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}
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STATIC
INLINE
void
Chip_PININT_DisableIntLow
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
CIENF
= pins;
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}
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STATIC
INLINE
uint32_t
Chip_PININT_GetRiseStates
(
LPC_PIN_INT_T
*pPININT)
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{
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return
pPININT->
RISE
;
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}
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STATIC
INLINE
void
Chip_PININT_ClearRiseStates
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
RISE
= pins;
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}
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STATIC
INLINE
uint32_t
Chip_PININT_GetFallStates
(
LPC_PIN_INT_T
*pPININT)
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{
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return
pPININT->
FALL
;
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}
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STATIC
INLINE
void
Chip_PININT_ClearFallStates
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
FALL
= pins;
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}
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STATIC
INLINE
uint32_t
Chip_PININT_GetIntStatus
(
LPC_PIN_INT_T
*pPININT)
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{
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return
pPININT->
IST
;
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}
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STATIC
INLINE
void
Chip_PININT_ClearIntStatus
(
LPC_PIN_INT_T
*pPININT, uint32_t pins)
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{
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pPININT->
IST
= pins;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __PININT_18XX_43XX_H_ */
Generated on Fri Feb 20 2015 21:29:43 for LPCOpen Platform for LPC18XX/43XX microcontrollers by
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