LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/sgpio_18xx_43xx.h Source File

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sgpio_18xx_43xx.h
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1 /*
2 * @brief LPC43xx Serial GPIO driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SGPIO_43XX_H_
33 #define __SGPIO_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
45 #if defined(CHIP_LPC43XX)
46
50 typedef struct {
51 __IO uint32_t OUT_MUX_CFG[16];
52 __IO uint32_t SGPIO_MUX_CFG[16];
53 __IO uint32_t SLICE_MUX_CFG[16];
54 __IO uint32_t REG[16];
55 __IO uint32_t REG_SS[16];
56 __IO uint32_t PRESET[16];
57 __IO uint32_t COUNT[16];
58 __IO uint32_t POS[16];
59 __IO uint32_t MASK_A;
60 __IO uint32_t MASK_H;
61 __IO uint32_t MASK_I;
62 __IO uint32_t MASK_P;
63 __I uint32_t GPIO_INREG;
64 __IO uint32_t GPIO_OUTREG;
65 __IO uint32_t GPIO_OENREG;
66 __IO uint32_t CTRL_ENABLED;
67 __IO uint32_t CTRL_DISABLED;
68 __I uint32_t RESERVED0[823];
69 __O uint32_t CLR_EN_0;
70 __O uint32_t SET_EN_0;
71 __I uint32_t ENABLE_0;
72 __I uint32_t STATUS_0;
73 __O uint32_t CTR_STATUS_0;
74 __O uint32_t SET_STATUS_0;
75 __I uint32_t RESERVED1[2];
76 __O uint32_t CLR_EN_1;
77 __O uint32_t SET_EN_1;
78 __I uint32_t ENABLE_1;
79 __I uint32_t STATUS_1;
80 __O uint32_t CTR_STATUS_1;
81 __O uint32_t SET_STATUS_1;
82 __I uint32_t RESERVED2[2];
83 __O uint32_t CLR_EN_2;
84 __O uint32_t SET_EN_2;
85 __I uint32_t ENABLE_2;
86 __I uint32_t STATUS_2;
87 __O uint32_t CTR_STATUS_2;
88 __O uint32_t SET_STATUS_2;
89 __I uint32_t RESERVED3[2];
90 __O uint32_t CLR_EN_3;
91 __O uint32_t SET_EN_3;
92 __I uint32_t ENABLE_3;
93 __I uint32_t STATUS_3;
94 __O uint32_t CTR_STATUS_3;
95 __O uint32_t SET_STATUS_3;
96 } LPC_SGPIO_T;
97
98 #endif
99
104 #ifdef __cplusplus
105 }
106 #endif
107
108 #endif /* __SGPIO_43XX_H_ */