32 #ifndef __CREG_18XX_43XX_H_
33 #define __CREG_18XX_43XX_H_
50 __I uint32_t RESERVED1[62];
52 #if defined(CHIP_LPC18XX)
53 __I uint32_t RESERVED2[5];
67 #if defined(CHIP_LPC18XX)
68 __I uint32_t RESERVED4[52];
71 __I uint32_t RESERVED4[51];
74 #if defined(CHIP_LPC18XX)
75 __I uint32_t RESERVED5[191];
77 __I uint32_t RESERVED5[65];
79 __I uint32_t RESERVED6[2];
81 __I uint32_t RESERVED7[58];
84 __I uint32_t RESERVED8[62];
87 __I uint32_t RESERVED9[63];
97 return LPC_CREG->CHIPID != 0x3284E02B;
110 uint32_t FAValue = Hz / 21510000;
112 LPC_CREG->FLASHCFGA = (
LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
113 LPC_CREG->FLASHCFGB = (
LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
142 tmpA =
LPC_CREG->FLASHCFGA & ~(0xF << 12);
143 LPC_CREG->FLASHCFGA = tmpA | ((uint32_t) clks << 12);
144 tmpB =
LPC_CREG->FLASHCFGB & ~(0xF << 12);
145 LPC_CREG->FLASHCFGB = tmpB | ((uint32_t) clks << 12);
178 LPC_CREG->CREG0 = (
LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
181 #if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
187 STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
189 LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
197 STATIC INLINE void Chip_CREG_SetM0SubMemMap(uint32_t memaddr)
199 LPC_CREG->M0SUBMEMMAP = memaddr & ~0xFFF;