LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
Data Structures | Macros | Enumerations | Functions
CHIP: LPC18xx/43xx SSP driver

Detailed Description

Data Structures

struct  LPC_SSP_T
 SSP register block structure. More...
 
struct  SSP_ConfigFormat
 
struct  SPI_Address_t
 
struct  Chip_SSP_DATA_SETUP_T
 

Macros

#define SSP_CR0_DSS(n)   ((uint32_t) ((n) & 0xF))
 
#define SSP_CR0_FRF_SPI   ((uint32_t) (0 << 4))
 
#define SSP_CR0_FRF_TI   ((uint32_t) (1 << 4))
 
#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))
 
#define SSP_CR0_CPOL_LO   ((uint32_t) (0))
 
#define SSP_CR0_CPOL_HI   ((uint32_t) (1 << 6))
 
#define SSP_CR0_CPHA_FIRST   ((uint32_t) (0))
 
#define SSP_CR0_CPHA_SECOND   ((uint32_t) (1 << 7))
 
#define SSP_CR0_SCR(n)   ((uint32_t) ((n & 0xFF) << 8))
 
#define SSP_CR0_SCR(n)   ((uint32_t) ((n & 0xFF) << 8))
 
#define SSP_CR0_BITMASK   ((uint32_t) (0xFFFF))
 
#define SSP_CR0_BITMASK   ((uint32_t) (0xFFFF))
 
#define SSP_CR1_LBM_EN   ((uint32_t) (1 << 0))
 
#define SSP_CR1_SSP_EN   ((uint32_t) (1 << 1))
 
#define SSP_CR1_SLAVE_EN   ((uint32_t) (1 << 2))
 
#define SSP_CR1_MASTER_EN   ((uint32_t) (0))
 
#define SSP_CR1_SO_DISABLE   ((uint32_t) (1 << 3))
 
#define SSP_CR1_BITMASK   ((uint32_t) (0x0F))
 
#define SSP_CPSR_BITMASK   ((uint32_t) (0xFF))
 
#define SSP_DR_BITMASK(n)   ((n) & 0xFFFF)
 
#define SSP_SR_BITMASK   ((uint32_t) (0x1F))
 
#define SSP_ICR_BITMASK   ((uint32_t) (0x03))
 
#define SSP_CPHA_FIRST   SSP_CR0_CPHA_FIRST
 
#define SSP_CPHA_SECOND   SSP_CR0_CPHA_SECOND
 
#define SSP_CPOL_HI   SSP_CR0_CPOL_LO
 
#define SSP_CPOL_LO   SSP_CR0_CPOL_HI
 
#define SSP_SLAVE_MODE   SSP_CR1_SLAVE_EN
 
#define SSP_MASTER_MODE   SSP_CR1_MASTER_EN
 

Enumerations

enum  SSP_STATUS_T {
  SSP_STAT_TFE = ((uint32_t)(1 << 0)), SSP_STAT_TNF = ((uint32_t)(1 << 1)), SSP_STAT_RNE = ((uint32_t)(1 << 2)), SSP_STAT_RFF = ((uint32_t)(1 << 3)),
  SSP_STAT_BSY = ((uint32_t)(1 << 4))
}
 SSP Type of Status. More...
 
enum  SSP_INTMASK_T {
  SSP_RORIM = ((uint32_t)(1 << 0)), SSP_RTIM = ((uint32_t)(1 << 1)), SSP_RXIM = ((uint32_t)(1 << 2)), SSP_TXIM = ((uint32_t)(1 << 3)),
  SSP_INT_MASK_BITMASK = ((uint32_t)(0xF))
}
 SSP Type of Interrupt Mask. More...
 
enum  SSP_MASKINTSTATUS_T {
  SSP_RORMIS = ((uint32_t)(1 << 0)), SSP_RTMIS = ((uint32_t)(1 << 1)), SSP_RXMIS = ((uint32_t)(1 << 2)), SSP_TXMIS = ((uint32_t)(1 << 3)),
  SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF))
}
 SSP Type of Mask Interrupt Status. More...
 
enum  SSP_RAWINTSTATUS_T {
  SSP_RORRIS = ((uint32_t)(1 << 0)), SSP_RTRIS = ((uint32_t)(1 << 1)), SSP_RXRIS = ((uint32_t)(1 << 2)), SSP_TXRIS = ((uint32_t)(1 << 3)),
  SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF))
}
 SSP Type of Raw Interrupt Status. More...
 
enum  SSP_INTCLEAR_T { SSP_RORIC = 0x0, SSP_RTIC = 0x1, SSP_INT_CLEAR_BITMASK = 0x3 }
 
enum  SSP_DMA_T { SSP_DMA_RX = (1u), SSP_DMA_TX = (1u << 1), SSP_DMA_BITMASK = ((uint32_t)(0x3)) }
 
enum  CHIP_SSP_CLOCK_MODE_T {
  SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
  SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0, SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0, SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1, SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1
}
 
enum  CHIP_SSP_FRAME_FORMAT_T { SSP_FRAMEFORMAT_SPI = (0 << 4), CHIP_SSP_FRAME_FORMAT_TI = (1u << 4), SSP_FRAMEFORMAT_MICROWIRE = (2u << 4) }
 
enum  CHIP_SSP_BITS_T {
  SSP_BITS_4 = (3u << 0), SSP_BITS_5 = (4u << 0), SSP_BITS_6 = (5u << 0), SSP_BITS_7 = (6u << 0),
  SSP_BITS_8 = (7u << 0), SSP_BITS_9 = (8u << 0), SSP_BITS_10 = (9u << 0), SSP_BITS_11 = (10u << 0),
  SSP_BITS_12 = (11u << 0), SSP_BITS_13 = (12u << 0), SSP_BITS_14 = (13u << 0), SSP_BITS_15 = (14u << 0),
  SSP_BITS_16 = (15u << 0)
}
 
enum  CHIP_SSP_MODE_T { SSP_MODE_MASTER = (0 << 2), SSP_MODE_SLAVE = (1u << 2) }
 

Functions

STATIC INLINE void Chip_SSP_Enable (LPC_SSP_T *pSSP)
 Enable SSP operation. More...
 
STATIC INLINE void Chip_SSP_Disable (LPC_SSP_T *pSSP)
 Disable SSP operation. More...
 
STATIC INLINE void Chip_SSP_EnableLoopBack (LPC_SSP_T *pSSP)
 Enable loopback mode. More...
 
STATIC INLINE void Chip_SSP_DisableLoopBack (LPC_SSP_T *pSSP)
 Disable loopback mode. More...
 
STATIC INLINE FlagStatus Chip_SSP_GetStatus (LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
 Get the current status of SSP controller. More...
 
STATIC INLINE uint32_t Chip_SSP_GetIntStatus (LPC_SSP_T *pSSP)
 Get the masked interrupt status. More...
 
STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus (LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
 Get the raw interrupt status. More...
 
STATIC INLINE uint8_t Chip_SSP_GetDataSize (LPC_SSP_T *pSSP)
 Get the number of bits transferred in each frame. More...
 
STATIC INLINE void Chip_SSP_ClearIntPending (LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
 Clear the corresponding interrupt condition(s) in the SSP controller. More...
 
STATIC INLINE void Chip_SSP_Int_Enable (LPC_SSP_T *pSSP)
 Enable interrupt for the SSP. More...
 
STATIC INLINE void Chip_SSP_Int_Disable (LPC_SSP_T *pSSP)
 Disable interrupt for the SSP. More...
 
STATIC INLINE uint16_t Chip_SSP_ReceiveFrame (LPC_SSP_T *pSSP)
 Get received SSP data. More...
 
STATIC INLINE void Chip_SSP_SendFrame (LPC_SSP_T *pSSP, uint16_t tx_data)
 Send SSP 16-bit data. More...
 
void Chip_SSP_SetClockRate (LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
 Set up output clocks per bit for SSP bus. More...
 
STATIC INLINE void Chip_SSP_SetFormat (LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
 Set up the SSP frame format. More...
 
STATIC INLINE void Chip_SSP_Set_Mode (LPC_SSP_T *pSSP, uint32_t mode)
 Set the SSP working as master or slave mode. More...
 
STATIC INLINE void Chip_SSP_DMA_Enable (LPC_SSP_T *pSSP)
 Enable DMA for SSP. More...
 
STATIC INLINE void Chip_SSP_DMA_Disable (LPC_SSP_T *pSSP)
 Disable DMA for SSP. More...
 
void Chip_SSP_Int_FlushData (LPC_SSP_T *pSSP)
 Clean all data in RX FIFO of SSP. More...
 
Status Chip_SSP_Int_RWFrames8Bits (LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
 SSP Interrupt Read/Write with 8-bit frame width. More...
 
Status Chip_SSP_Int_RWFrames16Bits (LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
 SSP Interrupt Read/Write with 16-bit frame width. More...
 
uint32_t Chip_SSP_RWFrames_Blocking (LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
 SSP Polling Read/Write in blocking mode. More...
 
uint32_t Chip_SSP_WriteFrames_Blocking (LPC_SSP_T *pSSP, const uint8_t *buffer, uint32_t buffer_len)
 SSP Polling Write in blocking mode. More...
 
uint32_t Chip_SSP_ReadFrames_Blocking (LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
 SSP Polling Read in blocking mode. More...
 
void Chip_SSP_Init (LPC_SSP_T *pSSP)
 Initialize the SSP. More...
 
void Chip_SSP_DeInit (LPC_SSP_T *pSSP)
 Deinitialise the SSP. More...
 
void Chip_SSP_SetMaster (LPC_SSP_T *pSSP, bool master)
 Set the SSP operating modes, master or slave. More...
 
void Chip_SSP_SetBitRate (LPC_SSP_T *pSSP, uint32_t bitRate)
 Set the clock frequency for SSP interface. More...
 

Macro Definition Documentation

#define SSP_CPHA_FIRST   SSP_CR0_CPHA_FIRST

SSP configuration parameter defines Clock phase control bit

Definition at line 480 of file ssp_18xx_43xx.h.

#define SSP_CPHA_SECOND   SSP_CR0_CPHA_SECOND

Definition at line 481 of file ssp_18xx_43xx.h.

#define SSP_CPOL_HI   SSP_CR0_CPOL_LO

Clock polarity control bit

Definition at line 490 of file ssp_18xx_43xx.h.

#define SSP_CPOL_LO   SSP_CR0_CPOL_HI

Definition at line 491 of file ssp_18xx_43xx.h.

#define SSP_CPSR_BITMASK   ((uint32_t) (0xFF))

SSP CPSR bit mask

Definition at line 109 of file ssp_18xx_43xx.h.

#define SSP_CR0_BITMASK   ((uint32_t) (0xFFFF))

SSP CR0 bit mask

Definition at line 86 of file ssp_18xx_43xx.h.

#define SSP_CR0_BITMASK   ((uint32_t) (0xFFFF))

SSP CR0 bit mask

Definition at line 86 of file ssp_18xx_43xx.h.

#define SSP_CR0_CPHA_FIRST   ((uint32_t) (0))

SPI clock out phase bit (used in SPI mode only), (1) = captures data on the second clock transition of the frame, (0) = first

Definition at line 78 of file ssp_18xx_43xx.h.

#define SSP_CR0_CPHA_SECOND   ((uint32_t) (1 << 7))

Definition at line 79 of file ssp_18xx_43xx.h.

#define SSP_CR0_CPOL_HI   ((uint32_t) (1 << 6))

Definition at line 75 of file ssp_18xx_43xx.h.

#define SSP_CR0_CPOL_LO   ((uint32_t) (0))

SPI clock polarity bit (used in SPI mode only), (1) = maintains the bus clock high between frames, (0) = low

Definition at line 74 of file ssp_18xx_43xx.h.

#define SSP_CR0_DSS (   n)    ((uint32_t) ((n) & 0xF))

Macro defines for CR0 registerSSP data size select, must be 4 bits to 16 bits

Definition at line 65 of file ssp_18xx_43xx.h.

#define SSP_CR0_FRF_MICROWIRE   ((uint32_t) (2 << 4))

SSP control 0 National Micro-wire mode

Definition at line 71 of file ssp_18xx_43xx.h.

#define SSP_CR0_FRF_SPI   ((uint32_t) (0 << 4))

SSP control 0 Motorola SPI mode

Definition at line 67 of file ssp_18xx_43xx.h.

#define SSP_CR0_FRF_TI   ((uint32_t) (1 << 4))

SSP control 0 TI synchronous serial mode

Definition at line 69 of file ssp_18xx_43xx.h.

#define SSP_CR0_SCR (   n)    ((uint32_t) ((n & 0xFF) << 8))

SSP serial clock rate value load macro, divider rate is PERIPH_CLK / (cpsr * (SCR + 1))

Definition at line 89 of file ssp_18xx_43xx.h.

#define SSP_CR0_SCR (   n)    ((uint32_t) ((n & 0xFF) << 8))

SSP serial clock rate value load macro, divider rate is PERIPH_CLK / (cpsr * (SCR + 1))

Definition at line 89 of file ssp_18xx_43xx.h.

#define SSP_CR1_BITMASK   ((uint32_t) (0x0F))

SSP CR1 bit mask

Definition at line 106 of file ssp_18xx_43xx.h.

#define SSP_CR1_LBM_EN   ((uint32_t) (1 << 0))

Macro defines for CR1 registerSSP control 1 loopback mode enable bit

Definition at line 96 of file ssp_18xx_43xx.h.

#define SSP_CR1_MASTER_EN   ((uint32_t) (0))

Definition at line 101 of file ssp_18xx_43xx.h.

#define SSP_CR1_SLAVE_EN   ((uint32_t) (1 << 2))

SSP control 1 slave enable

Definition at line 100 of file ssp_18xx_43xx.h.

#define SSP_CR1_SO_DISABLE   ((uint32_t) (1 << 3))

SSP control 1 slave out disable bit, disables transmit line in slave mode

Definition at line 104 of file ssp_18xx_43xx.h.

#define SSP_CR1_SSP_EN   ((uint32_t) (1 << 1))

SSP control 1 enable bit

Definition at line 98 of file ssp_18xx_43xx.h.

#define SSP_DR_BITMASK (   n)    ((n) & 0xFFFF)

Macro defines for DR registerSSP data bit mask

Definition at line 115 of file ssp_18xx_43xx.h.

#define SSP_ICR_BITMASK   ((uint32_t) (0x03))

ICR bit mask

Definition at line 125 of file ssp_18xx_43xx.h.

#define SSP_MASTER_MODE   SSP_CR1_MASTER_EN

Definition at line 495 of file ssp_18xx_43xx.h.

#define SSP_SLAVE_MODE   SSP_CR1_SLAVE_EN

SSP master mode enable

Definition at line 494 of file ssp_18xx_43xx.h.

#define SSP_SR_BITMASK   ((uint32_t) (0x1F))

Macro defines for SR registerSSP SR bit mask

Definition at line 122 of file ssp_18xx_43xx.h.

Enumeration Type Documentation

Enumerator
SSP_BITS_4 

4 bits/frame

SSP_BITS_5 

5 bits/frame

SSP_BITS_6 

6 bits/frame

SSP_BITS_7 

7 bits/frame

SSP_BITS_8 

8 bits/frame

SSP_BITS_9 

9 bits/frame

SSP_BITS_10 

10 bits/frame

SSP_BITS_11 

11 bits/frame

SSP_BITS_12 

12 bits/frame

SSP_BITS_13 

13 bits/frame

SSP_BITS_14 

14 bits/frame

SSP_BITS_15 

15 bits/frame

SSP_BITS_16 

16 bits/frame

Definition at line 209 of file ssp_18xx_43xx.h.

Enumerator
SSP_CLOCK_CPHA0_CPOL0 

CPHA = 0, CPOL = 0

SSP_CLOCK_CPHA0_CPOL1 

CPHA = 0, CPOL = 1

SSP_CLOCK_CPHA1_CPOL0 

CPHA = 1, CPOL = 0

SSP_CLOCK_CPHA1_CPOL1 

CPHA = 1, CPOL = 1

SSP_CLOCK_MODE0 

alias

SSP_CLOCK_MODE1 

alias

SSP_CLOCK_MODE2 

alias

SSP_CLOCK_MODE3 

alias

Definition at line 186 of file ssp_18xx_43xx.h.

Enumerator
SSP_FRAMEFORMAT_SPI 

Frame format: SPI

CHIP_SSP_FRAME_FORMAT_TI 

Frame format: TI SSI

SSP_FRAMEFORMAT_MICROWIRE 

Frame format: Microwire

Definition at line 200 of file ssp_18xx_43xx.h.

Enumerator
SSP_MODE_MASTER 

Master mode

SSP_MODE_SLAVE 

Slave mode

Definition at line 454 of file ssp_18xx_43xx.h.

enum SSP_DMA_T
Enumerator
SSP_DMA_RX 

DMA RX Enable

SSP_DMA_TX 

DMA TX Enable

SSP_DMA_BITMASK 

Definition at line 177 of file ssp_18xx_43xx.h.

Enumerator
SSP_RORIC 
SSP_RTIC 
SSP_INT_CLEAR_BITMASK 

Definition at line 171 of file ssp_18xx_43xx.h.

SSP Type of Interrupt Mask.

Enumerator
SSP_RORIM 

Overun

SSP_RTIM 

TimeOut

SSP_RXIM 

Rx FIFO is at least half full

SSP_TXIM 

Tx FIFO is at least half empty

SSP_INT_MASK_BITMASK 

Definition at line 141 of file ssp_18xx_43xx.h.

SSP Type of Mask Interrupt Status.

Enumerator
SSP_RORMIS 

Overun

SSP_RTMIS 

TimeOut

SSP_RXMIS 

Rx FIFO is at least half full

SSP_TXMIS 

Tx FIFO is at least half empty

SSP_MASK_INT_STAT_BITMASK 

Definition at line 152 of file ssp_18xx_43xx.h.

SSP Type of Raw Interrupt Status.

Enumerator
SSP_RORRIS 

Overun

SSP_RTRIS 

TimeOut

SSP_RXRIS 

Rx FIFO is at least half full

SSP_TXRIS 

Tx FIFO is at least half empty

SSP_RAW_INT_STAT_BITMASK 

Definition at line 163 of file ssp_18xx_43xx.h.

SSP Type of Status.

Enumerator
SSP_STAT_TFE 

TX FIFO Empty

SSP_STAT_TNF 

TX FIFO not full

SSP_STAT_RNE 

RX FIFO not empty

SSP_STAT_RFF 

RX FIFO full

SSP_STAT_BSY 

SSP Busy

Definition at line 130 of file ssp_18xx_43xx.h.

Function Documentation

STATIC INLINE void Chip_SSP_ClearIntPending ( LPC_SSP_T pSSP,
SSP_INTCLEAR_T  IntClear 
)

Clear the corresponding interrupt condition(s) in the SSP controller.

Parameters
pSSP: The base of SSP peripheral on the chip
IntClear,:Type of cleared interrupt, should be :
  • SSP_RORIC
  • SSP_RTIC
Returns
Nothing
Note
Software can clear one or more interrupt condition(s) in the SSP controller

Definition at line 341 of file ssp_18xx_43xx.h.

void Chip_SSP_DeInit ( LPC_SSP_T pSSP)

Deinitialise the SSP.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing
Note
The SSP controller is disabled

Definition at line 461 of file ssp_18xx_43xx.c.

STATIC INLINE void Chip_SSP_Disable ( LPC_SSP_T pSSP)

Disable SSP operation.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing

Definition at line 249 of file ssp_18xx_43xx.h.

STATIC INLINE void Chip_SSP_DisableLoopBack ( LPC_SSP_T pSSP)

Disable loopback mode.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing
Note
Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin

Definition at line 273 of file ssp_18xx_43xx.h.

STATIC INLINE void Chip_SSP_DMA_Disable ( LPC_SSP_T pSSP)

Disable DMA for SSP.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing

Definition at line 446 of file ssp_18xx_43xx.h.

STATIC INLINE void Chip_SSP_DMA_Enable ( LPC_SSP_T pSSP)

Enable DMA for SSP.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing

Definition at line 436 of file ssp_18xx_43xx.h.

STATIC INLINE void Chip_SSP_Enable ( LPC_SSP_T pSSP)

Enable SSP operation.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing

Definition at line 239 of file ssp_18xx_43xx.h.

STATIC INLINE void Chip_SSP_EnableLoopBack ( LPC_SSP_T pSSP)

Enable loopback mode.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing
Note
Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin

Definition at line 261 of file ssp_18xx_43xx.h.

STATIC INLINE uint8_t Chip_SSP_GetDataSize ( LPC_SSP_T pSSP)

Get the number of bits transferred in each frame.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
the number of bits transferred in each frame minus one
Note
The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer

Definition at line 327 of file ssp_18xx_43xx.h.

STATIC INLINE uint32_t Chip_SSP_GetIntStatus ( LPC_SSP_T pSSP)

Get the masked interrupt status.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
SSP Masked Interrupt Status Register value
Note
The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)

Definition at line 300 of file ssp_18xx_43xx.h.

STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus ( LPC_SSP_T pSSP,
SSP_RAWINTSTATUS_T  RawInt 
)

Get the raw interrupt status.

Parameters
pSSP: The base of SSP peripheral on the chip
RawInt: Interrupt condition to be get status, shoud be :
  • SSP_RORRIS
  • SSP_RTRIS
  • SSP_RXRIS
  • SSP_TXRIS
Returns
Raw interrupt status corresponding to interrupt condition , SET or RESET
Note
Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled

Definition at line 316 of file ssp_18xx_43xx.h.

STATIC INLINE FlagStatus Chip_SSP_GetStatus ( LPC_SSP_T pSSP,
SSP_STATUS_T  Stat 
)

Get the current status of SSP controller.

Parameters
pSSP: The base of SSP peripheral on the chip
Stat: Type of status, should be :
  • SSP_STAT_TFE
  • SSP_STAT_TNF
  • SSP_STAT_RNE
  • SSP_STAT_RFF
  • SSP_STAT_BSY
Returns
SSP controller status, SET or RESET

Definition at line 289 of file ssp_18xx_43xx.h.

void Chip_SSP_Init ( LPC_SSP_T pSSP)

Initialize the SSP.

Parameters
pSSP: The base SSP peripheral on the chip
Returns
Nothing

Definition at line 450 of file ssp_18xx_43xx.c.

STATIC INLINE void Chip_SSP_Int_Disable ( LPC_SSP_T pSSP)

Disable interrupt for the SSP.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing

Definition at line 361 of file ssp_18xx_43xx.h.

STATIC INLINE void Chip_SSP_Int_Enable ( LPC_SSP_T pSSP)

Enable interrupt for the SSP.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
Nothing

Definition at line 351 of file ssp_18xx_43xx.h.

void Chip_SSP_Int_FlushData ( LPC_SSP_T pSSP)

Clean all data in RX FIFO of SSP.

Parameters
pSSP: The base SSP peripheral on the chip
Returns
Nothing

Definition at line 336 of file ssp_18xx_43xx.c.

Status Chip_SSP_Int_RWFrames16Bits ( LPC_SSP_T pSSP,
Chip_SSP_DATA_SETUP_T xf_setup 
)

SSP Interrupt Read/Write with 16-bit frame width.

Parameters
pSSP: The base SSP peripheral on the chip
xf_setup: Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration
Returns
SUCCESS or ERROR

Definition at line 383 of file ssp_18xx_43xx.c.

Status Chip_SSP_Int_RWFrames8Bits ( LPC_SSP_T pSSP,
Chip_SSP_DATA_SETUP_T xf_setup 
)

SSP Interrupt Read/Write with 8-bit frame width.

Parameters
pSSP: The base SSP peripheral on the chip
xf_setup: Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration
Returns
SUCCESS or ERROR

Definition at line 352 of file ssp_18xx_43xx.c.

uint32_t Chip_SSP_ReadFrames_Blocking ( LPC_SSP_T pSSP,
uint8_t *  buffer,
uint32_t  buffer_len 
)

SSP Polling Read in blocking mode.

Parameters
pSSP: The base SSP peripheral on the chip
buffer: Buffer address
buffer_len: The length of buffer
Returns
Actual data length has been transferred
Note
This function can be used in both master and slave mode. First, a dummy writing operation is generated to clear data buffer. After that, a reading operation will receive the needed data

Definition at line 268 of file ssp_18xx_43xx.c.

STATIC INLINE uint16_t Chip_SSP_ReceiveFrame ( LPC_SSP_T pSSP)

Get received SSP data.

Parameters
pSSP: The base of SSP peripheral on the chip
Returns
SSP 16-bit data received

Definition at line 371 of file ssp_18xx_43xx.h.

uint32_t Chip_SSP_RWFrames_Blocking ( LPC_SSP_T pSSP,
Chip_SSP_DATA_SETUP_T xf_setup 
)

SSP Polling Read/Write in blocking mode.

Parameters
pSSP: The base SSP peripheral on the chip
xf_setup: Pointer to a SSP_DATA_SETUP_T structure that contains specified information about transmit/receive data configuration
Returns
Actual data length has been transferred
Note
This function can be used in both master and slave mode. It starts with writing phase and after that, a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared through xf_setup param.

Definition at line 147 of file ssp_18xx_43xx.c.

STATIC INLINE void Chip_SSP_SendFrame ( LPC_SSP_T pSSP,
uint16_t  tx_data 
)

Send SSP 16-bit data.

Parameters
pSSP: The base of SSP peripheral on the chip
tx_data: SSP 16-bit data to be transmited
Returns
Nothing

Definition at line 382 of file ssp_18xx_43xx.h.

STATIC INLINE void Chip_SSP_Set_Mode ( LPC_SSP_T pSSP,
uint32_t  mode 
)

Set the SSP working as master or slave mode.

Parameters
pSSP: The base of SSP peripheral on the chip
mode: Operating mode, should be
  • SSP_MODE_MASTER
  • SSP_MODE_SLAVE
Returns
Nothing

Definition at line 426 of file ssp_18xx_43xx.h.

void Chip_SSP_SetBitRate ( LPC_SSP_T pSSP,
uint32_t  bitRate 
)

Set the clock frequency for SSP interface.

Parameters
pSSP: The base SSP peripheral on the chip
bitRate: The SSP bit rate
Returns
Nothing

Definition at line 425 of file ssp_18xx_43xx.c.

void Chip_SSP_SetClockRate ( LPC_SSP_T pSSP,
uint32_t  clk_rate,
uint32_t  prescale 
)

Set up output clocks per bit for SSP bus.

Parameters
pSSP: The base of SSP peripheral on the chip
clk_ratefs: The number of prescaler-output clocks per bit on the bus, minus one
prescale: The factor by which the Prescaler divides the SSP peripheral clock PCLK
Returns
Nothing
Note
The bit frequency is PCLK / (prescale x[clk_rate+1])

Definition at line 138 of file ssp_18xx_43xx.c.

STATIC INLINE void Chip_SSP_SetFormat ( LPC_SSP_T pSSP,
uint32_t  bits,
uint32_t  frameFormat,
uint32_t  clockMode 
)

Set up the SSP frame format.

Parameters
pSSP: The base of SSP peripheral on the chip
bits: The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
frameFormat: Frame format, should be :
  • SSP_FRAMEFORMAT_SPI
  • SSP_FRAME_FORMAT_TI
  • SSP_FRAMEFORMAT_MICROWIRE
clockMode: Select Clock polarity and Clock phase, should be :
  • SSP_CLOCK_CPHA0_CPOL0
  • SSP_CLOCK_CPHA0_CPOL1
  • SSP_CLOCK_CPHA1_CPOL0
  • SSP_CLOCK_CPHA1_CPOL1
Returns
Nothing
Note
Note: The clockFormat is only used in SPI mode

Definition at line 413 of file ssp_18xx_43xx.h.

void Chip_SSP_SetMaster ( LPC_SSP_T pSSP,
bool  master 
)

Set the SSP operating modes, master or slave.

Parameters
pSSP: The base SSP peripheral on the chip
master: 1 to set master, 0 to set slave
Returns
Nothing

Definition at line 414 of file ssp_18xx_43xx.c.

uint32_t Chip_SSP_WriteFrames_Blocking ( LPC_SSP_T pSSP,
const uint8_t *  buffer,
uint32_t  buffer_len 
)

SSP Polling Write in blocking mode.

Parameters
pSSP: The base SSP peripheral on the chip
buffer: Buffer address
buffer_len: Buffer length
Returns
Actual data length has been transferred
Note
This function can be used in both master and slave mode. First, a writing operation will send the needed data. After that, a dummy reading operation is generated to clear data buffer

Definition at line 200 of file ssp_18xx_43xx.c.