LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
Data Structures | Modules | Macros | Functions
CHIP: LPC18xx/43xx Clock Driver

Detailed Description

Data Structures

struct  PLL_PARAM_T
 PLL Parameter strucutre. More...
 
struct  CGU_USBAUDIO_PLL_SETUP_T
 

Modules

 CHIP: LPC18xx/43xx Clock Driver driver options
 

Macros

#define CGU_IRC_FREQ   (12000000)
 
#define MAX_CLOCK_FREQ   (180000000)
 
#define PLL_MIN_CCO_FREQ   156000000
 
#define PLL_MAX_CCO_FREQ   320000000
 
#define CGU_PLL_LOCKED   (1 << 0) /* PLL locked status */
 
#define CGU_PLL_FR   (1 << 1) /* PLL free running indicator status */
 

Functions

void Chip_Clock_EnableCrystal (void)
 Enables the crystal oscillator. More...
 
void Chip_Clock_DisableCrystal (void)
 Disables the crystal oscillator. More...
 
uint32_t Chip_Clock_SetupMainPLLHz (CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)
 Configures the main PLL. More...
 
uint32_t Chip_Clock_SetupMainPLLMult (CHIP_CGU_CLKIN_T Input, uint32_t mult)
 Directly set the PLL multipler. More...
 
uint32_t Chip_Clock_GetMainPLLHz (void)
 Returns the frequency of the main PLL. More...
 
__STATIC_INLINE void Chip_Clock_DisableMainPLL (void)
 Disables the main PLL. More...
 
__STATIC_INLINE void Chip_Clock_EnableMainPLL (void)
 Enbles the main PLL. More...
 
__STATIC_INLINE void Chip_Clock_SetupMainPLL (const PLL_PARAM_T *ppll)
 Sets-up the main PLL. More...
 
void Chip_Clock_SetDivider (CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor)
 Sets up a CGU clock divider and it's input clock. More...
 
CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource (CHIP_CGU_IDIV_T Divider)
 Gets a CGU clock divider source. More...
 
uint32_t Chip_Clock_GetDividerDivisor (CHIP_CGU_IDIV_T Divider)
 Gets a CGU clock divider divisor. More...
 
uint32_t Chip_Clock_GetClockInputHz (CHIP_CGU_CLKIN_T input)
 Returns the frequency of the specified input clock source. More...
 
uint32_t Chip_Clock_GetBaseClocktHz (CHIP_CGU_BASE_CLK_T clock)
 Returns the frequency of the specified base clock source. More...
 
void Chip_Clock_SetBaseClock (CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
 Sets a CGU Base Clock clock source. More...
 
void Chip_Clock_GetBaseClockOpts (CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken, bool *powerdn)
 Get CGU Base Clock clock source information. More...
 
CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
 Gets a CGU Base Clock clock source. More...
 
void Chip_Clock_EnableBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
 Enables a base clock source. More...
 
void Chip_Clock_DisableBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
 Disables a base clock source. More...
 
bool Chip_Clock_IsBaseClockEnabled (CHIP_CGU_BASE_CLK_T BaseClock)
 Returns base clock enable state. More...
 
void Chip_Clock_EnableOpts (CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div)
 Enables a peripheral clock and sets clock states. More...
 
void Chip_Clock_Enable (CHIP_CCU_CLK_T clk)
 Enables a peripheral clock. More...
 
void Chip_Clock_RTCEnable (void)
 Enables RTCclock. More...
 
void Chip_Clock_Disable (CHIP_CCU_CLK_T clk)
 Disables a peripheral clock. More...
 
uint32_t Chip_Clock_GetRate (CHIP_CCU_CLK_T clk)
 Returns a peripheral clock rate. More...
 
uint32_t Chip_Clock_GetEMCRate (void)
 Returns EMC clock rate. More...
 
void Chip_Clock_StartPowerDown (void)
 Start the power down sequence by disabling the branch output clocks with wake up mechanism (Only the clocks which wake up mechanism bit enabled will be disabled) More...
 
void Chip_Clock_ClearPowerDown (void)
 Clear the power down mode bit & proceed normal operation of branch output clocks (Only the clocks which wake up mechanism bit enabled will be enabled after the wake up event) More...
 
void Chip_Clock_SetupPLL (CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum, const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup)
 Sets up the audio or USB PLL. More...
 
void Chip_Clock_EnablePLL (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
 Enables the audio or USB PLL. More...
 
void Chip_Clock_DisablePLL (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
 Disables the audio or USB PLL. More...
 
uint32_t Chip_Clock_GetPLLStatus (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
 Returns the PLL status. More...
 
int Chip_Clock_CalcMainPLLValue (uint32_t freq, PLL_PARAM_T *ppll)
 Calculate main PLL Pre, Post and M div values. More...
 
__STATIC_INLINE int Chip_Clock_MainPLLLocked (void)
 Wait for Main PLL to be locked. More...
 

Macro Definition Documentation

#define CGU_IRC_FREQ   (12000000)

Definition at line 64 of file clock_18xx_43xx.h.

#define CGU_PLL_FR   (1 << 1) /* PLL free running indicator status */

Definition at line 353 of file clock_18xx_43xx.h.

#define CGU_PLL_LOCKED   (1 << 0) /* PLL locked status */

Definition at line 352 of file clock_18xx_43xx.h.

#define MAX_CLOCK_FREQ   (180000000)

Definition at line 70 of file clock_18xx_43xx.h.

#define PLL_MAX_CCO_FREQ   320000000

Max CCO frequency of main PLL

Definition at line 75 of file clock_18xx_43xx.h.

#define PLL_MIN_CCO_FREQ   156000000

Min CCO frequency of main PLL

Definition at line 74 of file clock_18xx_43xx.h.

Enumeration Type Documentation

CGU clock input list These are possible input clocks for the CGU and can come from both external (crystal) and internal (PLL) sources. These clock inputs can be routed to the base clocks (CHIP_CGU_BASE_CLK_T).

Enumerator
CLKIN_32K 

External 32KHz input

CLKIN_IRC 

Internal IRC (12MHz) input

CLKIN_ENET_RX 

External ENET_RX pin input

CLKIN_ENET_TX 

External ENET_TX pin input

CLKIN_CLKIN 

External GPCLKIN pin input

CLKIN_RESERVED1 
CLKIN_CRYSTAL 

External (main) crystal pin input

CLKIN_USBPLL 

Internal USB PLL input

CLKIN_AUDIOPLL 

Internal Audio PLL input

CLKIN_MAINPLL 

Internal Main PLL input

CLKIN_RESERVED2 
CLKIN_RESERVED3 
CLKIN_IDIVA 

Internal divider A input

CLKIN_IDIVB 

Internal divider B input

CLKIN_IDIVC 

Internal divider C input

CLKIN_IDIVD 

Internal divider D input

CLKIN_IDIVE 

Internal divider E input

CLKINPUT_PD 

External 32KHz input

Definition at line 49 of file chip_clocks.h.

Audio or USB PLL selection

Enumerator
CGU_USB_PLL 
CGU_AUDIO_PLL 

Definition at line 48 of file cguccu_18xx_43xx.h.

Function Documentation

int Chip_Clock_CalcMainPLLValue ( uint32_t  freq,
PLL_PARAM_T ppll 
)

Calculate main PLL Pre, Post and M div values.

Parameters
freq: Expected output frequency
ppll: Pointer to PLL_PARAM_T structure
Returns
0 on success; < 0 on failure
Note
ppll->srcin[IN] should have the appropriate Input clock source selected
ppll->fout[OUT] will have the actual output frequency
ppll->fcco[OUT] will have the frequency of CCO

Definition at line 252 of file clock_18xx_43xx.c.

void Chip_Clock_ClearPowerDown ( void  )

Clear the power down mode bit & proceed normal operation of branch output clocks (Only the clocks which wake up mechanism bit enabled will be enabled after the wake up event)

Returns
Nothing

Enable all branch output clocks after the wake up event. Only the clocks with wake up mechanism enabled will be enabled

Definition at line 724 of file clock_18xx_43xx.c.

void Chip_Clock_Disable ( CHIP_CCU_CLK_T  clk)

Disables a peripheral clock.

Parameters
clk: CHIP_CCU_CLK_T value indicating which clock to disable
Returns
Nothing

Definition at line 697 of file clock_18xx_43xx.c.

void Chip_Clock_DisableBaseClock ( CHIP_CGU_BASE_CLK_T  BaseClock)

Disables a base clock source.

Parameters
BaseClock: CHIP_CGU_BASE_CLK_T value indicating which base clock to disable
Returns
Nothing

Definition at line 609 of file clock_18xx_43xx.c.

void Chip_Clock_DisableCrystal ( void  )

Disables the crystal oscillator.

Returns
Nothing

Definition at line 288 of file clock_18xx_43xx.c.

__STATIC_INLINE void Chip_Clock_DisableMainPLL ( void  )

Disables the main PLL.

Returns
none Make sure the main PLL is not needed to clock the part before disabling it. Saves power if the main PLL is not needed.

Definition at line 137 of file clock_18xx_43xx.h.

void Chip_Clock_DisablePLL ( CHIP_CGU_USB_AUDIO_PLL_T  pllnum)

Disables the audio or USB PLL.

Parameters
pllnum: PLL identifier
Returns
Nothing

Definition at line 814 of file clock_18xx_43xx.c.

void Chip_Clock_Enable ( CHIP_CCU_CLK_T  clk)

Enables a peripheral clock.

Parameters
clk: CHIP_CCU_CLK_T value indicating which clock to enable
Returns
Nothing

Definition at line 678 of file clock_18xx_43xx.c.

void Chip_Clock_EnableBaseClock ( CHIP_CGU_BASE_CLK_T  BaseClock)

Enables a base clock source.

Parameters
BaseClock: CHIP_CGU_BASE_CLK_T value indicating which base clock to enable
Returns
Nothing

Definition at line 601 of file clock_18xx_43xx.c.

void Chip_Clock_EnableCrystal ( void  )

Enables the crystal oscillator.

Returns
Nothing

Definition at line 227 of file clock_18xx_43xx.c.

__STATIC_INLINE void Chip_Clock_EnableMainPLL ( void  )

Enbles the main PLL.

Returns
none Make sure the main PLL is enabled.

Definition at line 148 of file clock_18xx_43xx.h.

void Chip_Clock_EnableOpts ( CHIP_CCU_CLK_T  clk,
bool  autoen,
bool  wakeupen,
int  div 
)

Enables a peripheral clock and sets clock states.

Parameters
clk: CHIP_CCU_CLK_T value indicating which clock to enable
autoen: true to enable autoblocking on a clock rate change, false to disable
wakeupen: true to enable wakeup mechanism, false to disable
div: Divider for the clock, must be 1 for most clocks, 2 supported on others
Returns
Nothing

Definition at line 651 of file clock_18xx_43xx.c.

void Chip_Clock_EnablePLL ( CHIP_CGU_USB_AUDIO_PLL_T  pllnum)

Enables the audio or USB PLL.

Parameters
pllnum: PLL identifier
Returns
Nothing

Definition at line 808 of file clock_18xx_43xx.c.

CHIP_CGU_CLKIN_T Chip_Clock_GetBaseClock ( CHIP_CGU_BASE_CLK_T  BaseClock)

Gets a CGU Base Clock clock source.

Parameters
BaseClock: CHIP_CGU_BASE_CLK_T value indicating which base clock to get inpuot clock for
Returns
CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD

Definition at line 632 of file clock_18xx_43xx.c.

void Chip_Clock_GetBaseClockOpts ( CHIP_CGU_BASE_CLK_T  BaseClock,
CHIP_CGU_CLKIN_T Input,
bool *  autoblocken,
bool *  powerdn 
)

Get CGU Base Clock clock source information.

Parameters
BaseClock: CHIP_CGU_BASE_CLK_T value indicating which base clock to get
Input: Pointer to CHIP_CGU_CLKIN_T value of the base clock
autoblocken: Pointer to autoblocking value of the base clock
powerdn: Pointer to power down flag
Returns
Nothing

Definition at line 581 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetBaseClocktHz ( CHIP_CGU_BASE_CLK_T  clock)

Returns the frequency of the specified base clock source.

Parameters
clock: which base clock to return the frequency of.
Returns
Frequency of base source in Hz This function returns an ideal frequency and not the actual frequency. Returns zero if the clock source is disabled.

Definition at line 547 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetClockInputHz ( CHIP_CGU_CLKIN_T  input)

Returns the frequency of the specified input clock source.

Parameters
input: Which clock input to return the frequency of
Returns
Frequency of input source in Hz This function returns an ideal frequency and not the actual frequency. Returns zero if the clock source is disabled.

Definition at line 467 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetDividerDivisor ( CHIP_CGU_IDIV_T  Divider)

Gets a CGU clock divider divisor.

Parameters
Divider: CHIP_CGU_IDIV_T value indicating which divider to get the source of
Returns
the divider value for the divider

Definition at line 461 of file clock_18xx_43xx.c.

CHIP_CGU_CLKIN_T Chip_Clock_GetDividerSource ( CHIP_CGU_IDIV_T  Divider)

Gets a CGU clock divider source.

Parameters
Divider: CHIP_CGU_IDIV_T value indicating which divider to get the source of
Returns
CHIP_CGU_CLKIN_T indicating which clock source is set or CLOCKINPUT_PD

Definition at line 449 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetEMCRate ( void  )

Returns EMC clock rate.

Returns
0 if the clock is disabled, or the rate of the clock

Definition at line 771 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetMainPLLHz ( void  )

Returns the frequency of the main PLL.

Returns
Frequency of the PLL in Hz Returns zero if the main PLL is not running.

Definition at line 399 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetPLLStatus ( CHIP_CGU_USB_AUDIO_PLL_T  pllnum)

Returns the PLL status.

Parameters
pllnum: PLL identifier
Returns
An OR'ed value of CGU_PLL_LOCKED or CGU_PLL_FR

Definition at line 820 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_GetRate ( CHIP_CCU_CLK_T  clk)

Returns a peripheral clock rate.

Parameters
clk: CHIP_CCU_CLK_T value indicating which clock to get rate for
Returns
0 if the clock is disabled, or the rate of the clock

Definition at line 732 of file clock_18xx_43xx.c.

bool Chip_Clock_IsBaseClockEnabled ( CHIP_CGU_BASE_CLK_T  BaseClock)

Returns base clock enable state.

Parameters
BaseClock: CHIP_CGU_BASE_CLK_T value indicating which base clock to check
Returns
true if the base clock is enabled, false if disabled

Definition at line 617 of file clock_18xx_43xx.c.

__STATIC_INLINE int Chip_Clock_MainPLLLocked ( void  )

Wait for Main PLL to be locked.

Returns
1 - PLL is LOCKED; 0 - PLL is not locked
Note
The main PLL should be locked prior to using it as a clock input for a base clock.

Definition at line 380 of file clock_18xx_43xx.h.

void Chip_Clock_RTCEnable ( void  )

Enables RTCclock.

Returns
Nothing

Definition at line 690 of file clock_18xx_43xx.c.

void Chip_Clock_SetBaseClock ( CHIP_CGU_BASE_CLK_T  BaseClock,
CHIP_CGU_CLKIN_T  Input,
bool  autoblocken,
bool  powerdn 
)

Sets a CGU Base Clock clock source.

Parameters
BaseClock: CHIP_CGU_BASE_CLK_T value indicating which base clock to set
Input: CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down base clock
autoblocken: Enables autoblocking during frequency change if true
powerdn: The clock base is setup, but powered down if true
Returns
Nothing

Definition at line 553 of file clock_18xx_43xx.c.

void Chip_Clock_SetDivider ( CHIP_CGU_IDIV_T  Divider,
CHIP_CGU_CLKIN_T  Input,
uint32_t  Divisor 
)

Sets up a CGU clock divider and it's input clock.

Parameters
Divider: CHIP_CGU_IDIV_T value indicating which divider to configure
Input: CHIP_CGU_CLKIN_T value indicating which clock source to use or CLOCKINPUT_PD to power down divider
Divisor: value to divide Input clock by
Returns
Nothing Maximum divider on A = 4, B/C/D = 16, E = 256. See the user manual for allowable combinations for input clock.

Definition at line 430 of file clock_18xx_43xx.c.

__STATIC_INLINE void Chip_Clock_SetupMainPLL ( const PLL_PARAM_T ppll)

Sets-up the main PLL.

Parameters
ppll: Pointer to pll param structure PLL_PARAM_T
Returns
none Make sure the main PLL is enabled.

Definition at line 159 of file clock_18xx_43xx.h.

uint32_t Chip_Clock_SetupMainPLLHz ( CHIP_CGU_CLKIN_T  Input,
uint32_t  MinHz,
uint32_t  DesiredHz,
uint32_t  MaxHz 
)

Configures the main PLL.

Parameters
Input: Which clock input to use as the PLL input
MinHz: Minimum allowable PLL output frequency
DesiredHz: Desired PLL output frequency
MaxHz: Maximum allowable PLL output frequency
Returns
Frequency of the PLL in Hz Returns the configured PLL frequency or zero if the PLL can not be configured between MinHz and MaxHz. This will not wait for PLL lock. Call Chip_Clock_MainPLLLocked() to determine if the PLL is locked.

Definition at line 295 of file clock_18xx_43xx.c.

uint32_t Chip_Clock_SetupMainPLLMult ( CHIP_CGU_CLKIN_T  Input,
uint32_t  mult 
)

Directly set the PLL multipler.

Parameters
Input: Which clock input to use as the PLL input
mult: How many times to multiply the input clock
Returns
Frequency of the PLL in Hz

Definition at line 355 of file clock_18xx_43xx.c.

void Chip_Clock_SetupPLL ( CHIP_CGU_CLKIN_T  Input,
CHIP_CGU_USB_AUDIO_PLL_T  pllnum,
const CGU_USBAUDIO_PLL_SETUP_T pPLLSetup 
)

Sets up the audio or USB PLL.

Parameters
Input: Input clock
pllnum: PLL identifier
pPLLSetup: Pointer to PLL setup structure
Returns
Nothing Sets up the PLL with the passed structure values.

Definition at line 790 of file clock_18xx_43xx.c.

void Chip_Clock_StartPowerDown ( void  )

Start the power down sequence by disabling the branch output clocks with wake up mechanism (Only the clocks which wake up mechanism bit enabled will be disabled)

Returns
Nothing

Disable all branch output clocks with wake up mechanism enabled. Only the clocks with wake up mechanism enabled will be disabled & power down sequence started

Definition at line 713 of file clock_18xx_43xx.c.