LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
creg_18xx_43xx.h
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1 /*
2  * @brief LPC18XX/43XX CREG control functions
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __CREG_18XX_43XX_H_
33 #define __CREG_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef struct {
48  __I uint32_t RESERVED0;
49  __IO uint32_t CREG0;
50  __I uint32_t RESERVED1[62];
51  __IO uint32_t MXMEMMAP;
52 #if defined(CHIP_LPC18XX)
53  __I uint32_t RESERVED2[5];
54 #else
55  __I uint32_t RESERVED2;
56  __I uint32_t CREG1;
57  __I uint32_t CREG2;
58  __I uint32_t CREG3;
59  __I uint32_t CREG4;
60 #endif
61  __IO uint32_t CREG5;
62  __IO uint32_t DMAMUX;
63  __IO uint32_t FLASHCFGA;
64  __IO uint32_t FLASHCFGB;
65  __IO uint32_t ETBCFG;
66  __IO uint32_t CREG6;
67 #if defined(CHIP_LPC18XX)
68  __I uint32_t RESERVED4[52];
69 #else
70  __IO uint32_t M4TXEVENT;
71  __I uint32_t RESERVED4[51];
72 #endif
73  __I uint32_t CHIPID;
74 #if defined(CHIP_LPC18XX)
75  __I uint32_t RESERVED5[191];
76 #else
77  __I uint32_t RESERVED5[65];
78  __IO uint32_t M0SUBMEMMAP;
79  __I uint32_t RESERVED6[2];
80  __IO uint32_t M0SUBTXEVENT;
81  __I uint32_t RESERVED7[58];
82  __IO uint32_t M0APPTXEVENT;
83  __IO uint32_t M0APPMEMMAP;
84  __I uint32_t RESERVED8[62];
85 #endif
86  __IO uint32_t USB0FLADJ;
87  __I uint32_t RESERVED9[63];
88  __IO uint32_t USB1FLADJ;
89 } LPC_CREG_T;
90 
96 {
97  return LPC_CREG->CHIPID != 0x3284E02B;
98 }
99 
109 {
110  uint32_t FAValue = Hz / 21510000;
111 
112  LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~(0xF << 12))) | (FAValue << 12);
113  LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~(0xF << 12))) | (FAValue << 12);
114 }
115 
119 typedef enum {
131 
138 {
139  uint32_t tmpA, tmpB;
140 
141  /* Don't alter lower bits */
142  tmpA = LPC_CREG->FLASHCFGA & ~(0xF << 12);
143  LPC_CREG->FLASHCFGA = tmpA | ((uint32_t) clks << 12);
144  tmpB = LPC_CREG->FLASHCFGB & ~(0xF << 12);
145  LPC_CREG->FLASHCFGB = tmpB | ((uint32_t) clks << 12);
146 }
147 
155 {
156  LPC_CREG->CREG0 &= ~(1 << 5);
157 }
158 
166 {
167  LPC_CREG->CREG0 |= (1 << 5);
168 }
169 
176 STATIC INLINE void Chip_CREG_ConfigureBODaR(uint32_t BODVL, uint32_t BORVL)
177 {
178  LPC_CREG->CREG0 = (LPC_CREG->CREG0 & ~((3 << 8) | (3 << 10))) | (BODVL << 8) | (BORVL << 10);
179 }
180 
181 #if (defined(CHIP_LPC43XX) && defined(LPC_CREG))
182 
187 STATIC INLINE void Chip_CREG_SetM0AppMemMap(uint32_t memaddr)
188 {
189  LPC_CREG->M0APPMEMMAP = memaddr & ~0xFFF;
190 }
191 
197 STATIC INLINE void Chip_CREG_SetM0SubMemMap(uint32_t memaddr)
198 {
199  LPC_CREG->M0SUBMEMMAP = memaddr & ~0xFFF;
200 }
201 
206 STATIC INLINE void Chip_CREG_ClearM4Event(void)
207 {
208  LPC_CREG->M4TXEVENT = 0;
209 }
210 
215 STATIC INLINE void Chip_CREG_ClearM0AppEvent(void)
216 {
217  LPC_CREG->M0APPTXEVENT = 0;
218 }
219 
224 STATIC INLINE void Chip_CREG_ClearM0SubEvent(void)
225 {
226  LPC_CREG->M0SUBTXEVENT = 0;
227 }
228 #endif
229 
234 #ifdef __cplusplus
235 }
236 #endif
237 
238 #endif /* __CREG_18XX_43XX_H_ */