LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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lpc_core
lpc_board
boards_43xx
hitex_eva_4350
board_sysinit.c
Go to the documentation of this file.
1
/*
2
* Copyright(C) NXP Semiconductors, 2012
3
* All rights reserved.
4
*
5
* Software that is described herein is for illustrative purposes only
6
* which provides customers with programming information regarding the
7
* LPC products. This software is supplied "AS IS" without any warranties of
8
* any kind, and NXP Semiconductors and its licensor disclaim any and
9
* all warranties, express or implied, including all implied warranties of
10
* merchantability, fitness for a particular purpose and non-infringement of
11
* intellectual property rights. NXP Semiconductors assumes no responsibility
12
* or liability for the use of the software, conveys no license or rights under any
13
* patent, copyright, mask work right, or any other intellectual property rights in
14
* or to any products. NXP Semiconductors reserves the right to make changes
15
* in the software without notification. NXP Semiconductors also makes no
16
* representation or warranty that such application will be suitable for the
17
* specified use without further testing or modification.
18
*
19
* Permission to use, copy, modify, and distribute this software and its
20
* documentation is hereby granted, under NXP Semiconductors' and its
21
* licensor's relevant copyrights in the software, without fee, provided that it
22
* is used in conjunction with NXP Semiconductors microcontrollers. This
23
* copyright, permission, and disclaimer notice must appear in all copies of
24
* this code.
25
*/
26
27
#include "
board.h
"
28
29
/* The System initialization code is called prior to the application and
30
initializes the board for run-time operation. Board initialization
31
includes clock setup and default pin muxing configuration. */
32
33
/*****************************************************************************
34
* Private types/enumerations/variables
35
****************************************************************************/
36
37
/* Structure for initial base clock states */
38
struct
CLK_BASE_STATES
{
39
CHIP_CGU_BASE_CLK_T
clk
;
/* Base clock */
40
CHIP_CGU_CLKIN_T
clkin
;
/* Base clock source, see UM for allowable souorces per base clock */
41
bool
autoblock_enab
;
/* Set to true to enable autoblocking on frequency change */
42
bool
powerdn
;
/* Set to true if the base clock is initially powered down */
43
};
44
45
/* Initial base clock states are mostly on */
46
STATIC
const
struct
CLK_BASE_STATES
InitClkStates
[] = {
47
{
CLK_BASE_PHY_TX
,
CLKIN_ENET_TX
,
true
,
false
},
48
#if defined(USE_RMII)
49
{
CLK_BASE_PHY_RX
,
CLKIN_ENET_TX
,
true
,
false
},
50
#else
51
{
CLK_BASE_PHY_RX
,
CLKIN_ENET_RX
,
true
,
false
},
52
#endif
53
54
/* Clocks derived from dividers */
55
{
CLK_BASE_LCD
,
CLKIN_IDIVC
,
true
,
false
},
56
{
CLK_BASE_USB1
,
CLKIN_IDIVD
,
true
,
true
}
57
};
58
59
/* SPIFI high speed pin mode setup */
60
STATIC
const
PINMUX_GRP_T
spifipinmuxing
[] = {
61
{0x3, 3, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI CLK */
62
{0x3, 4, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D3 */
63
{0x3, 5, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D2 */
64
{0x3, 6, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D1 */
65
{0x3, 7, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D0 */
66
{0x3, 8, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)}
/* SPIFI CS/SSEL */
67
};
68
69
STATIC
const
PINMUX_GRP_T
pinmuxing
[] = {
70
#if defined(USE_RMII)
71
/* RMII pin group */
72
{0x1, 19,
73
(
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC0
)},
74
{0x0, 1, (
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC6
)},
75
{0x1, 18, (
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC3
)},
76
{0x1, 20, (
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC3
)},
77
{0x1, 17,
78
(
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC3
)},
79
{0xC, 1, (
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC3
)},
80
{0x1, 16,
81
(
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC7
)},
82
{0x1, 15,
83
(
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC3
)},
84
{0x0, 0,
85
(
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_FUNC2
)},
86
#
else
87
/* MII pin group */
88
{0x1, 19, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC0
)},
89
{0x0, 1, (
SCU_MODE_INACT
|
SCU_MODE_FUNC6
)},
90
{0x1, 18, (
SCU_MODE_INACT
|
SCU_MODE_FUNC3
)},
91
{0x1, 20, (
SCU_MODE_INACT
|
SCU_MODE_FUNC3
)},
92
{0x1, 17, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC3
)},
93
{0xC, 1, (
SCU_MODE_INACT
|
SCU_MODE_FUNC3
)},
94
{0x1, 16, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC7
)},
95
{0x1, 15, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC3
)},
96
{0x0, 0, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC2
)},
97
{0x9, 4, (
SCU_MODE_INACT
|
SCU_MODE_FUNC5
)},
98
{0x9, 5, (
SCU_MODE_INACT
|
SCU_MODE_FUNC5
)},
99
{0xC, 0, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC3
)},
100
{0x9, 0, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC5
)},
101
{0x9, 1, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC5
)},
102
{0x9, 6, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC5
)},
103
{0x9, 3, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC5
)},
104
{0x9, 2, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC5
)},
105
{0xC, 8, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC4
)},
106
#endif
107
/* External data lines D0 .. D15 */
108
{0x1, 7,
109
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
110
{0x1, 8,
111
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
112
{0x1, 9,
113
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
114
{0x1, 10,
115
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
116
{0x1, 11,
117
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
118
{0x1, 12,
119
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
120
{0x1, 13,
121
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
122
{0x1, 14,
123
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
124
{0x5, 4,
125
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
126
{0x5, 5,
127
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
128
{0x5, 6,
129
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
130
{0x5, 7,
131
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
132
{0x5, 0,
133
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
134
{0x5, 1,
135
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
136
{0x5, 2,
137
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
138
{0x5, 3,
139
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
140
/* Address lines A0 .. A23 */
141
{0x2, 9,
142
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
143
{0x2, 10,
144
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
145
{0x2, 11,
146
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
147
{0x2, 12,
148
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
149
{0x2, 13,
150
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
151
{0x1, 0,
152
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
153
{0x1, 1,
154
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
155
{0x1, 2,
156
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
157
{0x2, 8,
158
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
159
{0x2, 7,
160
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
161
{0x2, 6,
162
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
163
{0x2, 2,
164
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
165
{0x2, 1,
166
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
167
{0x2, 0,
168
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
169
{0x6, 8,
170
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC1
)},
171
{0x6, 7,
172
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC1
)},
173
{0xD, 16,
174
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
175
{0xD, 15,
176
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
177
{0xE, 0,
178
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
179
{0xE, 1,
180
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
181
{0xE, 2,
182
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
183
{0xE, 3,
184
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
185
{0xE, 4,
186
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
187
{0xA, 4,
188
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
189
/* EMC control signals */
190
{0x1, 4,
191
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
192
{0x6, 6,
193
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC1
)},
194
{0xD, 13,
195
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
196
{0xD, 10,
197
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
198
{0x6, 9,
199
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
200
{0x1, 6,
201
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
202
{0x6, 4,
203
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
204
{0x6, 5,
205
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
206
{0x6, 11,
207
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
208
{0x6, 12,
209
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
210
{0x6, 10,
211
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
212
{0xD, 0,
213
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC2
)},
214
{0xE, 13,
215
(
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC3
)},
216
{0x1, 3, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
217
{0x1, 4, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
218
{0x6, 6, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
219
{0x1, 5, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
220
/* LCD interface, 24bpp */
221
{0x7, 7, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
222
{0x4, 7, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC0
)},
223
{0x4, 5, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
224
{0x4, 6, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
225
{0x7, 6, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
226
{0x4, 1, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
227
{0x4, 4, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
228
{0x4, 2, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
229
{0x8, 7, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
230
{0x8, 6, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
231
{0x8, 5, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
232
{0x8, 4, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
233
{0x7, 5, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
234
{0x4, 8, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
235
{0x4, 10, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
236
{0x4, 9, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
237
{0x8, 3, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
238
{0xB, 6, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
239
{0xB, 5, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
240
{0xB, 4, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
241
{0x7, 4, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
242
{0x7, 2, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
243
{0x7, 1, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
244
{0xB, 3, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
245
{0xB, 2, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
246
{0xB, 1, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
247
{0xB, 0, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC2
)},
248
{0x7, 0, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC3
)},
249
{0x4, 4, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC0
)},
250
{0x7, 3, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC0
)},
251
{0x4, 1, (
SCU_MODE_PULLUP
|
SCU_MODE_FUNC0
)},
252
/* Board LEDs */
253
{0x8, 1, (
SCU_MODE_INBUFF_EN
|
SCU_MODE_PULLDOWN
|
SCU_MODE_FUNC0
)},
254
{0xE, 6, (
SCU_MODE_INBUFF_EN
|
SCU_MODE_PULLDOWN
|
SCU_MODE_FUNC4
)},
/* GPIO7.6, green */
255
{0xE, 8, (
SCU_MODE_INBUFF_EN
|
SCU_MODE_PULLDOWN
|
SCU_MODE_FUNC4
)},
/* GPIO7.8, blue */
256
{0xE, 5, (
SCU_MODE_INBUFF_EN
|
SCU_MODE_PULLDOWN
|
SCU_MODE_FUNC4
)},
/* GPIO7.5, red */
257
/* Board ADC */
258
{0xF, 9, (
SCU_MODE_INACT
|
SCU_MODE_FUNC7
)},
259
/* I2S */
260
{0x3, 0, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC2
)},
261
{0x6, 0, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC4
)},
262
{0x7, 2, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC2
)},
263
{0x6, 2, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
264
{0x7, 1, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC2
)},
265
{0x6, 1, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
266
/* CCAN */
267
{0x3, 2, (
SCU_MODE_INACT
|
SCU_MODE_FUNC2
)},
/* PE.3 CAN TD1 | SCU_MODE_FUNC1) */
268
{0x3, 1, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_FUNC2
)},
/* PE.2 CAN RD1 | SCU_MODE_FUNC1) */
269
};
270
271
/* Pin clock mux values, re-used structure, value in first index is meaningless */
272
STATIC
const
PINMUX_GRP_T
pinclockmuxing
[] = {
273
{0, 0, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC0
)},
274
{0, 1, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC0
)},
275
{0, 2, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC0
)},
276
{0, 3, (
SCU_MODE_INACT
|
SCU_MODE_INBUFF_EN
|
SCU_MODE_ZIF_DIS
|
SCU_MODE_HIGHSPEEDSLEW_EN
|
SCU_MODE_FUNC0
)},
277
};
278
279
280
/* EMC clock delay */
281
#define CLK0_DELAY 7
282
283
/* Hitex SDRAM timing and chip Config */
284
STATIC
const
IP_EMC_DYN_CONFIG_T
IS42S16400_config
= {
285
EMC_NANOSECOND
(64000000 / 4096),
/* Row refresh time */
286
0x01,
/* Command Delayed */
287
EMC_NANOSECOND
(20),
288
EMC_NANOSECOND
(60),
289
EMC_NANOSECOND
(63),
290
EMC_CLOCK
(0x05),
291
EMC_CLOCK
(0x05),
292
EMC_CLOCK
(0x04),
293
EMC_NANOSECOND
(63),
294
EMC_NANOSECOND
(63),
295
EMC_NANOSECOND
(63),
296
EMC_NANOSECOND
(14),
297
EMC_CLOCK
(0x02),
298
{
299
{
300
EMC_ADDRESS_DYCS0
,
/* Hitex Board uses DYCS0 for SDRAM */
301
3,
/* RAS */
302
303
EMC_DYN_MODE_WBMODE_PROGRAMMED
|
304
EMC_DYN_MODE_OPMODE_STANDARD
|
305
EMC_DYN_MODE_CAS_3
|
306
EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL
|
307
EMC_DYN_MODE_BURST_LEN_8
,
308
309
EMC_DYN_CONFIG_DATA_BUS_16
|
310
EMC_DYN_CONFIG_LPSDRAM
|
311
EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS
|
312
EMC_DYN_CONFIG_MD_SDRAM
313
},
314
{0, 0, 0, 0},
315
{0, 0, 0, 0},
316
{0, 0, 0, 0}
317
}
318
};
319
320
/* Hitex Static RAM timing and chip Config */
321
STATIC
const
IP_EMC_STATIC_CONFIG_T
IS62WV25616_config
= {
322
2,
323
EMC_STATIC_CONFIG_MEM_WIDTH_16
|
324
EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW
|
325
EMC_STATIC_CONFIG_BLS_HIGH
/* |
326
EMC_CONFIG_BUFFER_ENABLE*/
,
327
328
EMC_NANOSECOND
(0),
329
EMC_NANOSECOND
(30),
330
EMC_NANOSECOND
(90),
331
EMC_NANOSECOND
(55),
332
EMC_NANOSECOND
(55),
333
EMC_NANOSECOND
(55)
334
};
335
336
/* Hitex NorFlash timing and chip Config */
337
STATIC
const
IP_EMC_STATIC_CONFIG_T
SST39VF320_config
= {
338
0,
339
EMC_STATIC_CONFIG_MEM_WIDTH_16
|
340
EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW
|
341
EMC_STATIC_CONFIG_BLS_HIGH
/* |
342
EMC_CONFIG_BUFFER_ENABLE*/
,
343
344
EMC_NANOSECOND
(0),
345
EMC_NANOSECOND
(35),
346
EMC_NANOSECOND
(70),
347
EMC_NANOSECOND
(70),
348
EMC_NANOSECOND
(40),
349
EMC_CLOCK
(4)
350
};
351
352
/*****************************************************************************
353
* Public types/enumerations/variables
354
****************************************************************************/
355
356
/*****************************************************************************
357
* Private functions
358
****************************************************************************/
359
360
/*****************************************************************************
361
* Public functions
362
****************************************************************************/
363
364
/* Sets up system pin muxing */
365
void
Board_SetupMuxing
(
void
)
366
{
367
int
i;
368
369
/* Setup system level pin muxing */
370
Chip_SCU_SetPinMuxing
(pinmuxing,
sizeof
(pinmuxing) /
sizeof
(
PINMUX_GRP_T
));
371
372
/* Clock pins only, group field not used */
373
for
(i = 0; i < (
sizeof
(
pinclockmuxing
) /
sizeof
(pinclockmuxing[0])); i++) {
374
Chip_SCU_ClockPinMuxSet
(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
375
}
376
377
/* SPIFI pin setup is done prior to setting up system clocking */
378
Chip_SCU_SetPinMuxing
(
spifipinmuxing
,
sizeof
(
spifipinmuxing
) /
sizeof
(
PINMUX_GRP_T
));
379
}
380
381
/* Setup external memories */
382
void
Board_SetupExtMemory
(
void
)
383
{
384
/* Setup EMC Delays */
385
/* Move all clock delays together */
386
LPC_SCU
->EMCDELAYCLK = ((
CLK0_DELAY
) | (
CLK0_DELAY
<< 4) | (
CLK0_DELAY
<< 8) | (
CLK0_DELAY
<< 12));
387
388
/* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
389
and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
390
less than 120MHz, a divider of 1 or 2 is ok. */
391
Chip_Clock_EnableOpts
(
CLK_MX_EMC_DIV
,
true
,
true
, 2);
392
LPC_CREG
->CREG6 |= (1 << 16);
393
394
/* Enable EMC clock */
395
Chip_Clock_Enable
(
CLK_MX_EMC
);
396
397
/* Init EMC Controller -Enable-LE mode */
398
Chip_EMC_Init
(1, 0, 0);
399
/* Init EMC Dynamic Controller */
400
Chip_EMC_Dynamic_Init
((
IP_EMC_DYN_CONFIG_T
*) &IS42S16400_config);
401
/* Init EMC Static Controller CS2 */
402
Chip_EMC_Static_Init
((
IP_EMC_STATIC_CONFIG_T
*) &IS62WV25616_config);
403
/* Init EMC Static Controller CS0 */
404
Chip_EMC_Static_Init
((
IP_EMC_STATIC_CONFIG_T
*) &SST39VF320_config);
405
406
/* Enable Buffer for External Flash */
407
LPC_EMC
->STATICCONFIG0 |= 1 << 19;
408
}
409
410
/* Set up and initialize clocking prior to call to main */
411
void
Board_SetupClocking
(
void
)
412
{
413
int
i;
414
415
Chip_SetupCoreClock
(
CLKIN_CRYSTAL
,
MAX_CLOCK_FREQ
,
true
);
416
417
/* Setup system base clocks and initial states. This won't enable and
418
disable individual clocks, but sets up the base clock sources for
419
each individual peripheral clock. */
420
for
(i = 0; i < (
sizeof
(
InitClkStates
) /
sizeof
(InitClkStates[0])); i++) {
421
Chip_Clock_SetBaseClock
(InitClkStates[i].
clk
, InitClkStates[i].
clkin
,
422
InitClkStates[i].
autoblock_enab
, InitClkStates[i].
powerdn
);
423
}
424
425
/* Reset and enable 32Khz oscillator */
426
LPC_CREG
->CREG0 &= ~((1 << 3) | (1 << 2));
427
LPC_CREG
->CREG0 |= (1 << 1) | (1 << 0);
428
429
/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
430
Divide rate is based on CPU speed and speed of SPI FLASH part. */
431
#if (MAX_CLOCK_FREQ > 180000000)
432
Chip_Clock_SetDivider
(
CLK_IDIV_E
,
CLKIN_MAINPLL
, 5);
433
#else
434
Chip_Clock_SetDivider
(
CLK_IDIV_E
,
CLKIN_MAINPLL
, 4);
435
#endif
436
Chip_Clock_SetBaseClock
(
CLK_BASE_SPIFI
,
CLKIN_IDIVE
,
true
,
false
);
437
438
/* Attach main PLL clock to divider C with a divider of 2 */
439
Chip_Clock_SetDivider
(
CLK_IDIV_C
,
CLKIN_MAINPLL
, 2);
440
}
441
442
/* Set up and initialize hardware prior to call to main */
443
void
Board_SystemInit
(
void
)
444
{
445
/* Setup system clocking and memory. This is done early to allow the
446
application and tools to clear memory and use scatter loading to
447
external memory. */
448
Board_SetupMuxing
();
449
Board_SetupClocking
();
450
Board_SetupExtMemory
();
451
}
Generated on Fri Feb 20 2015 21:29:41 for LPCOpen Platform for LPC18XX/43XX microcontrollers by
1.8.3.1