LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/enet_18xx_43xx.h Source File

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enet_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx Ethernet driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __ENET_18XX_43XX_H_
33 #define __ENET_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t MAC_CONFIG;
49 __IO uint32_t MAC_FRAME_FILTER;
50 __IO uint32_t MAC_HASHTABLE_HIGH;
51 __IO uint32_t MAC_HASHTABLE_LOW;
52 __IO uint32_t MAC_MII_ADDR;
53 __IO uint32_t MAC_MII_DATA;
54 __IO uint32_t MAC_FLOW_CTRL;
55 __IO uint32_t MAC_VLAN_TAG;
56 __I uint32_t RESERVED0;
57 __I uint32_t MAC_DEBUG;
58 __IO uint32_t MAC_RWAKE_FRFLT;
59 __IO uint32_t MAC_PMT_CTRL_STAT;
60 __I uint32_t RESERVED1[2];
61 __I uint32_t MAC_INTR;
62 __IO uint32_t MAC_INTR_MASK;
63 __IO uint32_t MAC_ADDR0_HIGH;
64 __IO uint32_t MAC_ADDR0_LOW;
65 __I uint32_t RESERVED2[430];
66 __IO uint32_t MAC_TIMESTP_CTRL;
67 __IO uint32_t SUBSECOND_INCR;
68 __I uint32_t SECONDS;
69 __I uint32_t NANOSECONDS;
70 __IO uint32_t SECONDSUPDATE;
71 __IO uint32_t NANOSECONDSUPDATE;
72 __IO uint32_t ADDEND;
73 __IO uint32_t TARGETSECONDS;
74 __IO uint32_t TARGETNANOSECONDS;
75 __IO uint32_t HIGHWORD;
76 __I uint32_t TIMESTAMPSTAT;
77 __IO uint32_t PPSCTRL;
78 __I uint32_t AUXNANOSECONDS;
79 __I uint32_t AUXSECONDS;
80 __I uint32_t RESERVED3[562];
81 __IO uint32_t DMA_BUS_MODE;
82 __IO uint32_t DMA_TRANS_POLL_DEMAND;
83 __IO uint32_t DMA_REC_POLL_DEMAND;
84 __IO uint32_t DMA_REC_DES_ADDR;
85 __IO uint32_t DMA_TRANS_DES_ADDR;
86 __IO uint32_t DMA_STAT;
87 __IO uint32_t DMA_OP_MODE;
88 __IO uint32_t DMA_INT_EN;
89 __I uint32_t DMA_MFRM_BUFOF;
90 __IO uint32_t DMA_REC_INT_WDT;
91 __I uint32_t RESERVED4[8];
92 __I uint32_t DMA_CURHOST_TRANS_DES;
93 __I uint32_t DMA_CURHOST_REC_DES;
94 __I uint32_t DMA_CURHOST_TRANS_BUF;
95 __I uint32_t DMA_CURHOST_REC_BUF;
96 } LPC_ENET_T;
97
98 /*
99 * @brief MAC_CONFIG register bit defines
100 */
101 #define MAC_CFG_RE (1 << 2)
102 #define MAC_CFG_TE (1 << 3)
103 #define MAC_CFG_DF (1 << 4)
104 #define MAC_CFG_BL(n) ((n) << 5)
105 #define MAC_CFG_ACS (1 << 7)
106 #define MAC_CFG_LUD (1 << 8)
107 #define MAC_CFG_DR (1 << 9)
108 #define MAC_CFG_IPC (1 << 10)
109 #define MAC_CFG_DM (1 << 11)
110 #define MAC_CFG_LM (1 << 12)
111 #define MAC_CFG_DO (1 << 13)
112 #define MAC_CFG_FES (1 << 14)
113 #define MAC_CFG_PS (1 << 15)
114 #define MAC_CFG_DCRS (1 << 16)
115 #define MAC_CFG_IFG(n) ((n) << 17)
116 #define MAC_CFG_JE (1 << 20)
117 #define MAC_CFG_JD (1 << 22)
118 #define MAC_CFG_WD (1 << 23)
120 /*
121 * @brief MAC_FRAME_FILTER register bit defines
122 */
123 #define MAC_FF_PR (1 << 0)
124 #define MAC_FF_DAIF (1 << 3)
125 #define MAC_FF_PM (1 << 4)
126 #define MAC_FF_DBF (1 << 5)
127 #define MAC_FF_PCF(n) ((n) << 6)
128 #define MAC_FF_SAIF (1 << 8)
129 #define MAC_FF_SAF (1 << 9)
130 #define MAC_FF_RA (1UL << 31)
132 /*
133 * @brief MAC_MII_ADDR register bit defines
134 */
135 #define MAC_MIIA_GB (1 << 0)
136 #define MAC_MIIA_W (1 << 1)
137 #define MAC_MIIA_CR(n) ((n) << 2)
138 #define MAC_MIIA_GR(n) ((n) << 6)
139 #define MAC_MIIA_PA(n) ((n) << 11)
141 /*
142 * @brief MAC_MII_DATA register bit defines
143 */
144 #define MAC_MIID_GDMSK (0xFFFF)
149 #define MAC_FC_FCB (1 << 0)
150 #define MAC_FC_TFE (1 << 1)
151 #define MAC_FC_RFE (1 << 2)
152 #define MAC_FC_UP (1 << 3)
153 #define MAC_FC_PLT(n) ((n) << 4)
154 #define MAC_FC_DZPQ (1 << 7)
155 #define MAC_FC_PT(n) ((n) << 16)
157 /*
158 * @brief MAC_VLAN_TAG register bit defines
159 */
160 #define MAC_VT_VL(n) ((n) << 0)
161 #define MAC_VT_ETC (1 << 7)
163 /*
164 * @brief MAC_PMT_CTRL_STAT register bit defines
165 */
166 #define MAC_PMT_PD (1 << 0)
167 #define MAC_PMT_MPE (1 << 1)
168 #define MAC_PMT_WFE (1 << 2)
169 #define MAC_PMT_MPR (1 << 5)
170 #define MAC_PMT_WFR (1 << 6)
171 #define MAC_PMT_GU (1 << 9)
172 #define MAC_PMT_WFFRPR (1UL << 31)
174 /*
175 * @brief MAC_INTR_MASK register bit defines
176 */
177 #define MAC_IM_PMT (1 << 3)
179 /*
180 * @brief MAC_ADDR0_HIGH register bit defines
181 */
182 #define MAC_ADRH_MO (1UL << 31)
184 /*
185 * @brief MAC_ADDR0_HIGH register bit defines
186 */
187 #define MAC_ADRH_MO (1UL << 31)
189 /*
190 * @brief MAC_TIMESTAMP register bit defines
191 */
192 #define MAC_TS_TSENA (1 << 0)
193 #define MAC_TS_TSCFUP (1 << 1)
194 #define MAC_TS_TSINIT (1 << 2)
195 #define MAC_TS_TSUPDT (1 << 3)
196 #define MAC_TS_TSTRIG (1 << 4)
197 #define MAC_TS_TSADDR (1 << 5)
198 #define MAC_TS_TSENAL (1 << 8)
199 #define MAC_TS_TSCTRL (1 << 9)
200 #define MAC_TS_TSVER2 (1 << 10)
201 #define MAC_TS_TSIPENA (1 << 11)
202 #define MAC_TS_TSIPV6E (1 << 12)
203 #define MAC_TS_TSIPV4E (1 << 13)
204 #define MAC_TS_TSEVNT (1 << 14)
205 #define MAC_TS_TSMSTR (1 << 15)
206 #define MAC_TS_TSCLKT(n) ((n) << 16)
207 #define MAC_TS_TSENMA (1 << 18)
209 /*
210 * @brief DMA_BUS_MODE register bit defines
211 */
212 #define DMA_BM_SWR (1 << 0)
213 #define DMA_BM_DA (1 << 1)
214 #define DMA_BM_DSL(n) ((n) << 2)
215 #define DMA_BM_ATDS (1 << 7)
216 #define DMA_BM_PBL(n) ((n) << 8)
217 #define DMA_BM_PR(n) ((n) << 14)
218 #define DMA_BM_FB (1 << 16)
219 #define DMA_BM_RPBL(n) ((n) << 17)
220 #define DMA_BM_USP (1 << 23)
221 #define DMA_BM_PBL8X (1 << 24)
222 #define DMA_BM_AAL (1 << 25)
223 #define DMA_BM_MB (1 << 26)
224 #define DMA_BM_TXPR (1 << 27)
226 /*
227 * @brief DMA_STAT register bit defines
228 */
229 #define DMA_ST_TI (1 << 0)
230 #define DMA_ST_TPS (1 << 1)
231 #define DMA_ST_TU (1 << 2)
232 #define DMA_ST_TJT (1 << 3)
233 #define DMA_ST_OVF (1 << 4)
234 #define DMA_ST_UNF (1 << 5)
235 #define DMA_ST_RI (1 << 6)
236 #define DMA_ST_RU (1 << 7)
237 #define DMA_ST_RPS (1 << 8)
238 #define DMA_ST_RWT (1 << 9)
239 #define DMA_ST_ETI (1 << 10)
240 #define DMA_ST_FBI (1 << 13)
241 #define DMA_ST_ERI (1 << 14)
242 #define DMA_ST_AIE (1 << 15)
243 #define DMA_ST_NIS (1 << 16)
244 #define DMA_ST_ALL (0x1E7FF)
246 /*
247 * @brief DMA_OP_MODE register bit defines
248 */
249 #define DMA_OM_SR (1 << 1)
250 #define DMA_OM_OSF (1 << 2)
251 #define DMA_OM_RTC(n) ((n) << 3)
252 #define DMA_OM_FUF (1 << 6)
253 #define DMA_OM_FEF (1 << 7)
254 #define DMA_OM_ST (1 << 13)
255 #define DMA_OM_TTC(n) ((n) << 14)
256 #define DMA_OM_FTF (1 << 20)
257 #define DMA_OM_TSF (1 << 21)
258 #define DMA_OM_DFF (1 << 24)
259 #define DMA_OM_RSF (1 << 25)
260 #define DMA_OM_DT (1 << 26)
262 /*
263 * @brief DMA_INT_EN register bit defines
264 */
265 #define DMA_IE_TIE (1 << 0)
266 #define DMA_IE_TSE (1 << 1)
267 #define DMA_IE_TUE (1 << 2)
268 #define DMA_IE_TJE (1 << 3)
269 #define DMA_IE_OVE (1 << 4)
270 #define DMA_IE_UNE (1 << 5)
271 #define DMA_IE_RIE (1 << 6)
272 #define DMA_IE_RUE (1 << 7)
273 #define DMA_IE_RSE (1 << 8)
274 #define DMA_IE_RWE (1 << 9)
275 #define DMA_IE_ETE (1 << 10)
276 #define DMA_IE_FBE (1 << 13)
277 #define DMA_IE_ERE (1 << 14)
278 #define DMA_IE_AIE (1 << 15)
279 #define DMA_IE_NIE (1 << 16)
281 /*
282 * @brief DMA_MFRM_BUFOF register bit defines
283 */
284 #define DMA_MFRM_FMCMSK (0xFFFF)
285 #define DMA_MFRM_OC (1 << 16)
286 #define DMA_MFRM_FMA(n) (((n) & 0x0FFE0000) >> 17)
287 #define DMA_MFRM_OF (1 << 28)
289 /*
290 * @brief Common TRAN_DESC_T and TRAN_DESC_ENH_T CTRLSTAT field bit defines
291 */
292 #define TDES_DB (1 << 0)
293 #define TDES_UF (1 << 1)
294 #define TDES_ED (1 << 2)
295 #define TDES_CCMSK(n) (((n) & 0x000000F0) >> 3)
296 #define TDES_VF (1 << 7)
297 #define TDES_EC (1 << 8)
298 #define TDES_LC (1 << 9)
299 #define TDES_NC (1 << 10)
300 #define TDES_LCAR (1 << 11)
301 #define TDES_IPE (1 << 12)
302 #define TDES_FF (1 << 13)
303 #define TDES_JT (1 << 14)
304 #define TDES_ES (1 << 15)
305 #define TDES_IHE (1 << 16)
306 #define TDES_TTSS (1 << 17)
307 #define TDES_OWN (1UL << 31)
309 /*
310 * @brief TRAN_DESC_ENH_T only CTRLSTAT field bit defines
311 */
312 #define TDES_ENH_IC (1UL << 30)
313 #define TDES_ENH_LS (1 << 29)
314 #define TDES_ENH_FS (1 << 28)
315 #define TDES_ENH_DC (1 << 27)
316 #define TDES_ENH_DP (1 << 26)
317 #define TDES_ENH_TTSE (1 << 25)
318 #define TDES_ENH_CIC(n) ((n) << 22)
319 #define TDES_ENH_TER (1 << 21)
320 #define TDES_ENH_TCH (1 << 20)
322 /*
323 * @brief TRAN_DESC_T only BSIZE field bit defines
324 */
325 #define TDES_NORM_IC (1UL << 31)
326 #define TDES_NORM_FS (1 << 30)
327 #define TDES_NORM_LS (1 << 29)
328 #define TDES_NORM_CIC(n) ((n) << 27)
329 #define TDES_NORM_DC (1 << 26)
330 #define TDES_NORM_TER (1 << 25)
331 #define TDES_NORM_TCH (1 << 24)
332 #define TDES_NORM_DP (1 << 23)
333 #define TDES_NORM_TTSE (1 << 22)
334 #define TDES_NORM_BS2(n) (((n) & 0x3FF) << 11)
335 #define TDES_NORM_BS1(n) (((n) & 0x3FF) << 0)
337 /*
338 * @brief TRAN_DESC_ENH_T only BSIZE field bit defines
339 */
340 #define TDES_ENH_BS2(n) (((n) & 0xFFF) << 16)
341 #define TDES_ENH_BS1(n) (((n) & 0xFFF) << 0)
343 /*
344 * @brief Common REC_DESC_T and REC_DESC_ENH_T STATUS field bit defines
345 */
346 #define RDES_ESA (1 << 0)
347 #define RDES_CE (1 << 1)
348 #define RDES_DRE (1 << 2)
349 #define RDES_RE (1 << 3)
350 #define RDES_RWT (1 << 4)
351 #define RDES_FT (1 << 5)
352 #define RDES_LC (1 << 6)
353 #define RDES_TSA (1 << 7)
354 #define RDES_LS (1 << 8)
355 #define RDES_FS (1 << 9)
356 #define RDES_VLAN (1 << 10)
357 #define RDES_OE (1 << 11)
358 #define RDES_LE (1 << 12)
359 #define RDES_SAF (1 << 13)
360 #define RDES_DE (1 << 14)
361 #define RDES_ES (1 << 15)
362 #define RDES_FLMSK(n) (((n) & 0x3FFF0000) >> 16)
363 #define RDES_AFM (1 << 30)
364 #define RDES_OWN (1UL << 31)
366 /*
367 * @brief Common REC_DESC_T and REC_DESC_ENH_T CTRL field bit defines
368 */
369 #define RDES_DINT (1UL << 31)
371 /*
372 * @brief REC_DESC_T pnly CTRL field bit defines
373 */
374 #define RDES_NORM_RER (1 << 25)
375 #define RDES_NORM_RCH (1 << 24)
376 #define RDES_NORM_BS2(n) (((n) & 0x3FF) << 11)
377 #define RDES_NORM_BS1(n) (((n) & 0x3FF) << 0)
382 #define RDES_ENH_RER (1 << 15)
383 #define RDES_ENH_RCH (1 << 14)
384 #define RDES_ENH_BS2(n) (((n) & 0xFFF) << 16)
385 #define RDES_ENH_BS1(n) (((n) & 0xFFF) << 0)
387 /*
388 * @brief REC_DESC_ENH_T only EXTSTAT field bit defines
389 */
390 #define RDES_ENH_IPPL(n) (((n) & 0x7) >> 2)
391 #define RDES_ENH_IPHE (1 << 3)
392 #define RDES_ENH_IPPLE (1 << 4)
393 #define RDES_ENH_IPCSB (1 << 5)
394 #define RDES_ENH_IPV4 (1 << 6)
395 #define RDES_ENH_IPV6 (1 << 7)
396 #define RDES_ENH_MTMSK(n) (((n) & 0xF) >> 8)
398 /*
399 * @brief Maximum size of an ethernet buffer
400 */
401 #define EMAC_ETH_MAX_FLEN (1536)
402
406 typedef struct {
407 __IO uint32_t CTRLSTAT;
408 __IO uint32_t BSIZE;
409 __IO uint32_t B1ADD;
410 __IO uint32_t B2ADD;
411 } ENET_TXDESC_T;
412
416 typedef struct {
417 __IO uint32_t CTRLSTAT;
418 __IO uint32_t BSIZE;
419 __IO uint32_t B1ADD;
420 __IO uint32_t B2ADD;
421 __IO uint32_t TDES4;
422 __IO uint32_t TDES5;
423 __IO uint32_t TTSL;
424 __IO uint32_t TTSH;
425 } ENET_ENHTXDESC_T;
426
430 typedef struct {
431 __IO uint32_t STATUS;
432 __IO uint32_t CTRL;
433 __IO uint32_t B1ADD;
434 __IO uint32_t B2ADD;
435 } ENET_RXDESC_T;
436
440 typedef struct {
441 __IO uint32_t STATUS;
442 __IO uint32_t CTRL;
443 __IO uint32_t B1ADD;
444 __IO uint32_t B2ADD;
445 __IO uint32_t EXTSTAT;
446 __IO uint32_t RDES5;
447 __IO uint32_t RTSL;
448 __IO uint32_t RTSH;
449 } ENET_ENHRXDESC_T;
450
458 STATIC INLINE void Chip_ENET_Reset(LPC_ENET_T *pENET)
459 {
460 /* This should be called prior to IP_ENET_Init. The MAC controller may
461 not be ready for a call to init right away so a small delay should
462 occur after this call. */
463 pENET->DMA_BUS_MODE |= DMA_BM_SWR;
464 }
465
472 STATIC INLINE void Chip_ENET_SetADDR(LPC_ENET_T *pENET, const uint8_t *macAddr)
473 {
474 /* Save MAC address */
475 pENET->MAC_ADDR0_LOW = ((uint32_t) macAddr[3] << 24) |
476 ((uint32_t) macAddr[2] << 16) | ((uint32_t) macAddr[1] << 8) |
477 ((uint32_t) macAddr[0]);
478 pENET->MAC_ADDR0_HIGH = ((uint32_t) macAddr[5] << 8) |
479 ((uint32_t) macAddr[4]);
480 }
481
489 void Chip_ENET_SetupMII(LPC_ENET_T *pENET, uint32_t div, uint8_t addr);
490
500 void Chip_ENET_StartMIIWrite(LPC_ENET_T *pENET, uint8_t reg, uint16_t data);
501
511 void Chip_ENET_StartMIIRead(LPC_ENET_T *pENET, uint8_t reg);
512
518 STATIC INLINE bool Chip_ENET_IsMIIBusy(LPC_ENET_T *pENET)
519 {
520 return (pENET->MAC_MII_ADDR & MAC_MIIA_GB) ? true : false;
521 }
522
528 STATIC INLINE uint16_t Chip_ENET_ReadMIIData(LPC_ENET_T *pENET)
529 {
530 return pENET->MAC_MII_DATA;
531 }
532
538 STATIC INLINE void Chip_ENET_TXEnable(LPC_ENET_T *pENET)
539 {
540 pENET->MAC_CONFIG |= MAC_CFG_TE;
541 pENET->DMA_OP_MODE |= DMA_OM_ST;
542 }
543
549 STATIC INLINE void Chip_ENET_TXDisable(LPC_ENET_T *pENET)
550 {
551 pENET->MAC_CONFIG &= ~MAC_CFG_TE;
552 }
553
559 STATIC INLINE void Chip_ENET_RXEnable(LPC_ENET_T *pENET)
560 {
561 pENET->MAC_CONFIG |= MAC_CFG_RE;
562 pENET->DMA_OP_MODE |= DMA_OM_SR;
563 }
564
570 STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)
571 {
572 pENET->MAC_CONFIG &= ~MAC_CFG_RE;
573 }
574
583 STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET)
584 {
585 LPC_CREG->CREG6 |= 0x4;
586 }
587
596 STATIC INLINE void Chip_ENET_MIIEnable(LPC_ENET_T *pENET)
597 {
598 LPC_CREG->CREG6 &= ~0x7;
599 }
600
607 void Chip_ENET_SetDuplex(LPC_ENET_T *pENET, bool full);
608
615 void Chip_ENET_SetSpeed(LPC_ENET_T *pENET, bool speed100);
616
624 STATIC INLINE void Chip_ENET_InitDescriptors(LPC_ENET_T *pENET,
625 ENET_ENHTXDESC_T *pTXDescs, ENET_ENHRXDESC_T *pRXDescs)
626 {
627 /* Setup descriptor list base addresses */
628 pENET->DMA_TRANS_DES_ADDR = (uint32_t) pTXDescs;
629 pENET->DMA_REC_DES_ADDR = (uint32_t) pRXDescs;
630 }
631
637 STATIC INLINE void Chip_ENET_RXStart(LPC_ENET_T *pENET)
638 {
639 /* Start receive polling */
640 pENET->DMA_REC_POLL_DEMAND = 1;
641 }
642
648 STATIC INLINE void Chip_ENET_TXStart(LPC_ENET_T *pENET)
649 {
650 /* Start transmit polling */
651 pENET->DMA_TRANS_POLL_DEMAND = 1;
652 }
653
663 void Chip_ENET_Init(LPC_ENET_T *pENET, uint32_t phyAddr);
664
670 void Chip_ENET_DeInit(LPC_ENET_T *pENET);
671
676 #ifdef __cplusplus
677 }
678 #endif
679
680 #endif /* __ENET_18XX_43XX_H_ */