LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
Data Structures | Macros | Functions
CHIP: LPC18xx/43xx External Memory Controller driver

Detailed Description

The EMC interface clocks must be enabled outside this driver prior to calling any function of this driver.

Data Structures

struct  LPC_EMC_T
 External Memory Controller (EMC) register block structure. More...
 
struct  IP_EMC_DYN_DEVICE_CONFIG_T
 EMC Dynamic Device Configuration structure used for IP drivers. More...
 
struct  IP_EMC_DYN_CONFIG_T
 EMC Dynamic Configure Struct. More...
 
struct  IP_EMC_STATIC_CONFIG_T
 EMC Static Configure Structure. More...
 

Macros

#define EMC_ADDRESS_DYCS0   (0x28000000)
 
#define EMC_ADDRESS_DYCS1   (0x30000000)
 
#define EMC_ADDRESS_DYCS2   (0x60000000)
 
#define EMC_ADDRESS_DYCS3   (0x70000000)
 
#define EMC_ADDRESS_CS0   (0x1C000000)
 
#define EMC_ADDRESS_CS1   (0x1D000000)
 
#define EMC_ADDRESS_CS2   (0x1E000000)
 
#define EMC_ADDRESS_CS3   (0x1F000000)
 
#define EMC_SUPPORT_ONLY_PL172
 EMC register support bitfields and mask. More...
 
#define EMC_CONFIG_ENDIAN_LITTLE   (0)
 
#define EMC_CONFIG_ENDIAN_BIG   (1)
 
#define EMC_CONFIG_BUFFER_ENABLE   (1 << 19)
 
#define EMC_CONFIG_WRITE_PROTECT   (1 << 20)
 
#define EMC_DYN_CONFIG_MD_BIT   (3)
 
#define EMC_DYN_CONFIG_MD_SDRAM   (0 << EMC_DYN_CONFIG_MD_BIT)
 
#define EMC_DYN_CONFIG_MD_LPSDRAM   (1 << EMC_DYN_CONFIG_MD_BIT)
 
#define EMC_DYN_CONFIG_LPSDRAM_BIT   (12)
 
#define EMC_DYN_CONFIG_LPSDRAM   (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_BIT   (9)
 
#define EMC_DYN_CONFIG_DEV_SIZE_16Mb   (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_64Mb   (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_BIT   (7)
 
#define EMC_DYN_CONFIG_DEV_BUS_8   (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_16   (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DEV_BUS_32   (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)
 
#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)
 
#define EMC_DYN_CONFIG_DATA_BUS_16   (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
 
#define EMC_DYN_CONFIG_DATA_BUS_32   (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
 
#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS   ((0x0 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS   ((0x0 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS   ((0x1 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS   ((0x1 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS   ((0x1 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS   ((0x2 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS   ((0x2 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))
 
#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS   ((0x3 << 9) | (0x2 << 7))
 
#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))
 
#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS   ((0x4 << 9) | (0x1 << 7))
 
#define EMC_DYN_MODE_BURST_LEN_BIT   (0)
 
#define EMC_DYN_MODE_BURST_LEN_1   (0)
 
#define EMC_DYN_MODE_BURST_LEN_2   (1)
 
#define EMC_DYN_MODE_BURST_LEN_4   (2)
 
#define EMC_DYN_MODE_BURST_LEN_8   (3)
 
#define EMC_DYN_MODE_BURST_LEN_FULL   (7)
 
#define EMC_DYN_MODE_BURST_TYPE_BIT   (3)
 
#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL   (0 << EMC_DYN_MODE_BURST_TYPE_BIT)
 
#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE   (1 << EMC_DYN_MODE_BURST_TYPE_BIT)
 
#define EMC_DYN_MODE_CAS_BIT   (4)
 
#define EMC_DYN_MODE_CAS_1   (1 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_CAS_2   (2 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_CAS_3   (3 << EMC_DYN_MODE_CAS_BIT)
 
#define EMC_DYN_MODE_OPMODE_BIT   (7)
 
#define EMC_DYN_MODE_OPMODE_STANDARD   (0 << EMC_DYN_MODE_OPMODE_BIT)
 
#define EMC_DYN_MODE_WBMODE_BIT   (9)
 
#define EMC_DYN_MODE_WBMODE_PROGRAMMED   (0 << EMC_DYN_MODE_WBMODE_BIT)
 
#define EMC_DYN_MODE_WBMODE_SINGLE_LOC   (1 << EMC_DYN_MODE_WBMODE_BIT)
 
#define EMC_DYN_CONTROL_ENABLE   (0x03)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_8   (0)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_16   (1)
 
#define EMC_STATIC_CONFIG_MEM_WIDTH_32   (2)
 
#define EMC_STATIC_CONFIG_PAGE_MODE_BIT   (3)
 
#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE   (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)
 
#define EMC_STATIC_CONFIG_CS_POL_BIT   (6)
 
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH   (1 << EMC_STATIC_CONFIG_CS_POL_BIT)
 
#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW   (0 << EMC_STATIC_CONFIG_CS_POL_BIT)
 
#define EMC_STATIC_CONFIG_BLS_BIT   (7)
 
#define EMC_STATIC_CONFIG_BLS_HIGH   (1 << EMC_STATIC_CONFIG_BLS_BIT)
 
#define EMC_STATIC_CONFIG_BLS_LOW   (0 << EMC_STATIC_CONFIG_BLS_BIT)
 
#define EMC_STATIC_CONFIG_EW_BIT   (8)
 
#define EMC_STATIC_CONFIG_EW_ENABLE   (1 << EMC_STATIC_CONFIG_EW_BIT)
 
#define EMC_STATIC_CONFIG_EW_DISABLE   (0 << EMC_STATIC_CONFIG_EW_BIT)
 
#define Q24_8_FP(x)   ((x) * 256)
 
#define EMC_NANOSECOND(x)   Q24_8_FP(x)
 
#define EMC_CLOCK(x)   Q24_8_FP(-(x))
 

Functions

void Chip_EMC_Dynamic_Init (IP_EMC_DYN_CONFIG_T *Dynamic_Config)
 Dyanmic memory setup. More...
 
void Chip_EMC_Static_Init (IP_EMC_STATIC_CONFIG_T *Static_Config)
 Static memory setup. More...
 
void Chip_EMC_Dynamic_Enable (uint8_t Enable)
 Enable Dynamic Memory Controller. More...
 
void Chip_EMC_Mirror (uint8_t Enable)
 Mirror CS1 to CS0 and DYCS0. More...
 
void Chip_EMC_Enable (uint8_t Enable)
 Enable EMC. More...
 
void Chip_EMC_LowPowerMode (uint8_t Enable)
 Set EMC LowPower Mode. More...
 
void Chip_EMC_Init (uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode)
 Initialize EMC. More...
 
STATIC INLINE void Chip_EMC_SetStaticExtendedWait (uint32_t Wait16Clks)
 Set Static Memory Extended Wait in Clock. More...
 

Macro Definition Documentation

#define EMC_ADDRESS_CS0   (0x1C000000)

Static Chip Select Address

Definition at line 128 of file emc_18xx_43xx.h.

#define EMC_ADDRESS_CS1   (0x1D000000)

Definition at line 129 of file emc_18xx_43xx.h.

#define EMC_ADDRESS_CS2   (0x1E000000)

Definition at line 130 of file emc_18xx_43xx.h.

#define EMC_ADDRESS_CS3   (0x1F000000)

Definition at line 131 of file emc_18xx_43xx.h.

#define EMC_ADDRESS_DYCS0   (0x28000000)

Dynamic Chip Select Address

Definition at line 120 of file emc_18xx_43xx.h.

#define EMC_ADDRESS_DYCS1   (0x30000000)

Definition at line 121 of file emc_18xx_43xx.h.

#define EMC_ADDRESS_DYCS2   (0x60000000)

Definition at line 122 of file emc_18xx_43xx.h.

#define EMC_ADDRESS_DYCS3   (0x70000000)

Definition at line 123 of file emc_18xx_43xx.h.

#define EMC_CLOCK (   x)    Q24_8_FP(-(x))

Definition at line 237 of file emc_18xx_43xx.h.

#define EMC_CONFIG_BUFFER_ENABLE   (1 << 19)

EMC Buffer enable bit in EMC Dynamic Configuration register

Definition at line 142 of file emc_18xx_43xx.h.

#define EMC_CONFIG_ENDIAN_BIG   (1)

Value for EMC to operate in Big Endian Mode

Definition at line 140 of file emc_18xx_43xx.h.

#define EMC_CONFIG_ENDIAN_LITTLE   (0)

Value for EMC to operate in Little Endian Mode

Definition at line 139 of file emc_18xx_43xx.h.

#define EMC_CONFIG_WRITE_PROTECT   (1 << 20)

EMC Write protect bit in EMC Dynamic Configuration register

Definition at line 143 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS   ((0x3 << 9) | (0x1 << 7))

Value for Memory configuration - 16Mx16 4 Banks 13 Rows 8 Columns

Definition at line 179 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS   ((0x2 << 9) | (0x0 << 7))

Value for Memory configuration - 16Mx8 4 Banks 12 Rows 10 Columns

Definition at line 175 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS   ((0x0 << 9) | (0x1 << 7))

Value for Memory configuration - 1Mx16 2 Banks 11 Rows 8 Columns

Definition at line 171 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS   ((0x1 << 9) | (0x2 << 7))

Value for Memory configuration - 2Mx32 4 Banks 11 Rows 8 Columns

Definition at line 174 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS   ((0x0 << 9) | (0x0 << 7))

Value for Memory configuration - 2Mx8 2 Banks 11 Rows 9 Columns

Definition at line 170 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS   ((0x4 << 9) | (0x1 << 7))

Value for Memory configuration - 32Mx16 4 Banks 13 Rows 10 Columns Dynamic Memory Mode Register Bit Definition

Definition at line 182 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS   ((0x3 << 9) | (0x0 << 7))

Value for Memory configuration - 32Mx8 4 Banks 13 Rows 10 Columns

Definition at line 178 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS   ((0x1 << 9) | (0x1 << 7))

Value for Memory configuration - 4Mx16 4 Banks 12 Rows 8 Columns

Definition at line 173 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS   ((0x2 << 9) | (0x2 << 7))

Value for Memory configuration - 4Mx32 4 Banks 12 Rows 8 Columns

Definition at line 177 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS   ((0x4 << 9) | (0x0 << 7))

Value for Memory configuration - 64Mx8 4 Banks 13 Rows 11 Columns

Definition at line 181 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS   ((0x2 << 9) | (0x1 << 7))

Value for Memory configuration - 8Mx16 4 Banks 12 Rows 9 Columns

Definition at line 176 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS   ((0x3 << 9) | (0x2 << 7))

Value for Memory configuration - 8Mx32 4 Banks 13 Rows 8 Columns

Definition at line 180 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS   ((0x1 << 9) | (0x0 << 7))

Value for Memory configuration - 8Mx8 4 Banks 12 Rows 9 Columns

Definition at line 172 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DATA_BUS_16   (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)

Device 16-bit data bus width value in EMC Dynamic Configuration register

Definition at line 166 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DATA_BUS_32   (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)

Device 32-bit bus width value in EMC Dynamic Configuration register Memory configuration values in EMC Dynamic Configuration Register

Definition at line 167 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT   (14)

Device data bus width starting bit in EMC Dynamic Configuration register

Definition at line 165 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_BUS_16   (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)

Device 16-bit bus width value in EMC Dynamic Configuration register

Definition at line 162 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_BUS_32   (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)

Device 32-bit bus width value in EMC Dynamic Configuration register

Definition at line 163 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_BUS_8   (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)

Device 8-bit bus width value in EMC Dynamic Configuration register

Definition at line 161 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_BUS_BIT   (7)

Device bus width starting bit in EMC Dynamic Configuration register

Definition at line 160 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_SIZE_128Mb   (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

128Mb Device Size value in EMC Dynamic Configuration register

Definition at line 156 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_SIZE_16Mb   (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

16Mb Device Size value in EMC Dynamic Configuration register

Definition at line 154 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_SIZE_256Mb   (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

256Mb Device Size value in EMC Dynamic Configuration register

Definition at line 157 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_SIZE_512Mb   (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

512Mb Device Size value in EMC Dynamic Configuration register

Definition at line 158 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_SIZE_64Mb   (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)

64Mb Device Size value in EMC Dynamic Configuration register

Definition at line 155 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_DEV_SIZE_BIT   (9)

Device Size starting bit in EMC Dynamic Configuration register

Definition at line 153 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_LPSDRAM   (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)

LPSDRAM value in EMC Dynamic Configuration register

Definition at line 151 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_LPSDRAM_BIT   (12)

LPSDRAM bit in EMC Dynamic Configuration register

Definition at line 150 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_MD_BIT   (3)

Memory device bit in EMC Dynamic Configuration register

Definition at line 146 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_MD_LPSDRAM   (1 << EMC_DYN_CONFIG_MD_BIT)

Select device as LPSDRAM in EMC Dynamic Configuration register

Definition at line 148 of file emc_18xx_43xx.h.

#define EMC_DYN_CONFIG_MD_SDRAM   (0 << EMC_DYN_CONFIG_MD_BIT)

Select device as SDRAM in EMC Dynamic Configuration register

Definition at line 147 of file emc_18xx_43xx.h.

#define EMC_DYN_CONTROL_ENABLE   (0x03)

Control Enable value Static Memory Configuration Register Bit Definitions

Definition at line 212 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_LEN_1   (0)

Value to set Burst Length to 1 in Dynamic Memory Mode Register

Definition at line 186 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_LEN_2   (1)

Value to set Burst Length to 2 in Dynamic Memory Mode Register

Definition at line 187 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_LEN_4   (2)

Value to set Burst Length to 4 in Dynamic Memory Mode Register

Definition at line 188 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_LEN_8   (3)

Value to set Burst Length to 8 in Dynamic Memory Mode Register

Definition at line 189 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_LEN_BIT   (0)

Starting bit No. of Burst Length in Dynamic Memory Mode Register

Definition at line 185 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_LEN_FULL   (7)

Value to set Burst Length to Full in Dynamic Memory Mode Register

Definition at line 190 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_TYPE_BIT   (3)

Burst Type bit in Dynamic Memory Mode Register

Definition at line 192 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE   (1 << EMC_DYN_MODE_BURST_TYPE_BIT)

Burst Type Interleaved in Dynamic Memory Mode Register CAS Latency in Dynamic Mode Register

Definition at line 194 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL   (0 << EMC_DYN_MODE_BURST_TYPE_BIT)

Burst Type Sequential in Dynamic Memory Mode Register

Definition at line 193 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_CAS_1   (1 << EMC_DYN_MODE_CAS_BIT)

value for CAS latency of 1 cycle

Definition at line 198 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_CAS_2   (2 << EMC_DYN_MODE_CAS_BIT)

value for CAS latency of 2 cycle

Definition at line 199 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_CAS_3   (3 << EMC_DYN_MODE_CAS_BIT)

value for CAS latency of 3 cycle Operation Mode in Dynamic Mode register

Definition at line 200 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_CAS_BIT   (4)

CAS latency starting bit in Dynamic Memory Mode register

Definition at line 197 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_OPMODE_BIT   (7)

Dynamic Mode Operation bit

Definition at line 203 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_OPMODE_STANDARD   (0 << EMC_DYN_MODE_OPMODE_BIT)

Value for Dynamic standard operation Mode Write Burst Mode in Dynamic Mode register

Definition at line 204 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_WBMODE_BIT   (9)

Write Burst Mode bit

Definition at line 207 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_WBMODE_PROGRAMMED   (0 << EMC_DYN_MODE_WBMODE_BIT)

Write Burst Mode programmed

Definition at line 208 of file emc_18xx_43xx.h.

#define EMC_DYN_MODE_WBMODE_SINGLE_LOC   (1 << EMC_DYN_MODE_WBMODE_BIT)

Write Burst Mode Single LOC Dynamic Memory Control Register Bit Definitions

Definition at line 209 of file emc_18xx_43xx.h.

#define EMC_NANOSECOND (   x)    Q24_8_FP(x)

Definition at line 236 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_BLS_BIT   (7)

BLS Configuration bit No

Definition at line 226 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_BLS_HIGH   (1 << EMC_STATIC_CONFIG_BLS_BIT)

BLS High Configuration value

Definition at line 227 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_BLS_LOW   (0 << EMC_STATIC_CONFIG_BLS_BIT)

BLS Low Configuration value

Definition at line 228 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH   (1 << EMC_STATIC_CONFIG_CS_POL_BIT)

Chip Select polarity - Active High

Definition at line 223 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW   (0 << EMC_STATIC_CONFIG_CS_POL_BIT)

Chip Select polarity - Active Low

Definition at line 224 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_CS_POL_BIT   (6)

Chip Select bit No

Definition at line 222 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_EW_BIT   (8)

Ext Wait bit No

Definition at line 230 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_EW_DISABLE   (0 << EMC_STATIC_CONFIG_EW_BIT)

Ext Wait Diabled value Q24.8 Fixed Point Helper

Definition at line 232 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_EW_ENABLE   (1 << EMC_STATIC_CONFIG_EW_BIT)

Ext Wait Enabled value

Definition at line 231 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_MEM_WIDTH_16   (1)

Static Memory Configuration - 16-bit width

Definition at line 216 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_MEM_WIDTH_32   (2)

Static Memory Configuration - 32-bit width

Definition at line 217 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_MEM_WIDTH_8   (0)

Static Memory Configuration - 8-bit width

Definition at line 215 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_PAGE_MODE_BIT   (3)

Page Mode bit No

Definition at line 219 of file emc_18xx_43xx.h.

#define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE   (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)

Value to enable Page Mode

Definition at line 220 of file emc_18xx_43xx.h.

#define EMC_SUPPORT_ONLY_PL172

EMC register support bitfields and mask.

Reserve for extending support to ARM9 or nextgen LPC

Definition at line 137 of file emc_18xx_43xx.h.

#define Q24_8_FP (   x)    ((x) * 256)

Definition at line 235 of file emc_18xx_43xx.h.

Function Documentation

void Chip_EMC_Dynamic_Enable ( uint8_t  Enable)

Enable Dynamic Memory Controller.

Parameters
Enable: 1 = Enable Dynamic Memory Controller, 0 = Disable
Returns
None

Definition at line 227 of file emc_18xx_43xx.c.

void Chip_EMC_Dynamic_Init ( IP_EMC_DYN_CONFIG_T Dynamic_Config)

Dyanmic memory setup.

Parameters
Dynamic_Config: Pointer to dynamic memory setup data
Returns
None

Definition at line 216 of file emc_18xx_43xx.c.

void Chip_EMC_Enable ( uint8_t  Enable)

Enable EMC.

Parameters
Enable: 1 = Enable, 0 = Disable
Returns
None

Definition at line 260 of file emc_18xx_43xx.c.

void Chip_EMC_Init ( uint32_t  Enable,
uint32_t  ClockRatio,
uint32_t  EndianMode 
)

Initialize EMC.

Parameters
Enable: 1 = Enable, 0 = Disable
ClockRatio: clock out ratio, 0 = 1:1, 1 = 1:2
EndianMode: Endian Mode, 0 = Little, 1 = Big
Returns
None

Definition at line 282 of file emc_18xx_43xx.c.

void Chip_EMC_LowPowerMode ( uint8_t  Enable)

Set EMC LowPower Mode.

Parameters
Enable: 1 = Enable, 0 = Disable
Returns
None
Note
This function should only be called when the memory controller is not busy (bit 0 of the status register is not set).

Definition at line 271 of file emc_18xx_43xx.c.

void Chip_EMC_Mirror ( uint8_t  Enable)

Mirror CS1 to CS0 and DYCS0.

Parameters
Enable: 1 = Mirror, 0 = Normal Memory Map
Returns
None

Definition at line 249 of file emc_18xx_43xx.c.

STATIC INLINE void Chip_EMC_SetStaticExtendedWait ( uint32_t  Wait16Clks)

Set Static Memory Extended Wait in Clock.

Parameters
Wait16Clks: Number of '16 clock' delay cycles
Returns
None

Definition at line 341 of file emc_18xx_43xx.h.

void Chip_EMC_Static_Init ( IP_EMC_STATIC_CONFIG_T Static_Config)

Static memory setup.

Parameters
Static_Config: Pointer to static memory setup data
Returns
None

Definition at line 238 of file emc_18xx_43xx.c.