LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_board/boards_43xx/nxp_lpclink2_4370/board_sysinit.c Source File

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board_sysinit.c
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1 /*
2 * Copyright(C) NXP Semiconductors, 2012
3 * All rights reserved.
4 *
5 * Software that is described herein is for illustrative purposes only
6 * which provides customers with programming information regarding the
7 * LPC products. This software is supplied "AS IS" without any warranties of
8 * any kind, and NXP Semiconductors and its licensor disclaim any and
9 * all warranties, express or implied, including all implied warranties of
10 * merchantability, fitness for a particular purpose and non-infringement of
11 * intellectual property rights. NXP Semiconductors assumes no responsibility
12 * or liability for the use of the software, conveys no license or rights under any
13 * patent, copyright, mask work right, or any other intellectual property rights in
14 * or to any products. NXP Semiconductors reserves the right to make changes
15 * in the software without notification. NXP Semiconductors also makes no
16 * representation or warranty that such application will be suitable for the
17 * specified use without further testing or modification.
18 *
19 * Permission to use, copy, modify, and distribute this software and its
20 * documentation is hereby granted, under NXP Semiconductors' and its
21 * licensor's relevant copyrights in the software, without fee, provided that it
22 * is used in conjunction with NXP Semiconductors microcontrollers. This
23 * copyright, permission, and disclaimer notice must appear in all copies of
24 * this code.
25 */
26
27 #include "board.h"
28
29 /* The System initialization code is called prior to the application and
30 initializes the board for run-time operation. Board initialization
31 includes clock setup and default pin muxing configuration. */
32
33 /*****************************************************************************
34 * Private types/enumerations/variables
35 ****************************************************************************/
36
37 #if defined(CORE_M4)
38 /* Structure for initial base clock states */
39 struct CLK_BASE_STATES {
40 CHIP_CGU_BASE_CLK_T clk; /* Base clock */
41 CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
42 bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
43 bool powerdn; /* Set to true if the base clock is initially powered down */
44 };
45
46 /* Initial base clock states are mostly on */
47 STATIC const struct CLK_BASE_STATES InitClkStates[] = {
48 {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
49 #if defined(USE_RMII)
50 {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
51 #else
52 {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
53 #endif
54
55 /* Clocks derived from dividers */
56 {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
57 {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
58 };
59
60 /* SPIFI high speed pin mode setup */
61 STATIC const PINMUX_GRP_T spifipinmuxing[] = {
62 {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */
63 {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */
64 {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */
65 {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */
66 {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */
67 {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */
68 };
69
70 STATIC const PINMUX_GRP_T pinmuxing[] = {
71 /* Board LEDs */
72 {0x1, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
73 };
74 #endif /* defined(CORE_M4) */
75
76 /*****************************************************************************
77 * Public types/enumerations/variables
78 ****************************************************************************/
79
80 /*****************************************************************************
81 * Private functions
82 ****************************************************************************/
83
84 /*****************************************************************************
85 * Public functions
86 ****************************************************************************/
87
88 /* Sets up system pin muxing */
89 void Board_SetupMuxing(void)
90 {
91 #if defined(CORE_M4)
92 /* Setup system level pin muxing */
93 Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
94
95 /* SPIFI pin setup is done prior to setting up system clocking */
96 Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T));
97 #endif /* defined(CORE_M4) */
98 }
99
100 /* Set up and initialize clocking prior to call to main */
101 void Board_SetupClocking(void)
102 {
103 #if defined(CORE_M4)
104 int i;
105
106 Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
107
108 /* Setup system base clocks and initial states. This won't enable and
109 disable individual clocks, but sets up the base clock sources for
110 each individual peripheral clock. */
111 for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
112 Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
113 InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
114 }
115
116 /* Reset and enable 32Khz oscillator */
117 LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
118 LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
119
120 /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
121 Divide rate is based on CPU speed and speed of SPI FLASH part. */
122 #if (MAX_CLOCK_FREQ > 180000000)
123 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
124 #else
125 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
126 #endif
127 Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
128
129 /* Attach main PLL clock to divider C with a divider of 2 */
130 Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
131 #endif /* defined(CORE_M4) */
132 }
133
134 /* Set up and initialize hardware prior to call to main */
135 void Board_SystemInit(void)
136 {
137 #if defined(CORE_M4)
138 /* Setup system clocking and memory. This is done early to allow the
139 application and tools to clear memory and use scatter loading to
140 external memory. */
141 Board_SetupMuxing();
142 Board_SetupClocking();
143 #endif /* defined(CORE_M4) */
144 }