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LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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| LPC18XX_43XX AES API structure | |
| CCAN message interface register block structure | |
| CAN message object structure | |
| CCU clock config/status register pair | |
| DMA channel handle structure | |
| Transfer Descriptor structure typedef | |
| Structure of a enhanced receive descriptor (with timestamp) | |
| Structure of a enhanced transmit descriptor (with timestamp) | |
| Structure of a receive descriptor (without timestamp) | |
| Structure of a transmit descriptor (without timestamp) | |
| GPDMA structure using for DMA configuration | |
| GPDMA Channel register block structure | |
| High speed ADC interrupt control structure | |
| Master transfer data structure definitions | |
| Master transfer data structure definitions | |
| I2S Audio Format Structure | |
| EMC Dynamic Configure Struct | |
| EMC Dynamic Device Configuration structure used for IP drivers | |
| EMC Static Configure Structure | |
| A structure for LCD Configuration | |
| LCD Palette entry format | |
| 10 or 12-bit ADC register block structure | |
| Alarm Timer register block structure | |
| CCAN Controller Area Network register block structure | |
| CCU1 register block structure | |
| CCU2 register block structure | |
| LPC18XX/43XX CGU register block structure | |
| CREG Register Block | |
| DAC register block structure | |
| EEPROM register block structure | |
| External Memory Controller (EMC) register block structure | |
| 10/100 MII & RMII Ethernet with timestamping register block structure | |
| Event Router register structure | |
| FLASH Memory Controller Unit register block structure | |
| Global Input Multiplexer Array (GIMA) register block structure | |
| GPDMA register block | |
| GPIO port register block structure | |
| GPIO grouped interrupt register block structure | |
| HSADC register block structure | |
| I2C register block structure | |
| I2S register block structure | |
| LCD Controller register block structure | |
| Motor Control PWM register block structure | |
| NAND Flash Size structure | |
| OTP Register block | |
| LPC18xx/43xx Pin Interrupt and Pattern Match register block structure | |
| Power Management Controller register block structure | |
| Quadrature Encoder Interface register block structure | |
| Register File register block structure | |
| RGU register structure | |
| Repetitive Interrupt Timer register block structure | |
| LPC18XX High level ROM API structure | |
| Real Time Clock register block structure | |
| State Configurable Timer register block structure | |
| System Control Unit register block | |
| SD/MMC & SDIO register block structure | |
| SSP register block structure | |
| 32-bit Standard timer register block structure | |
| USART register block structure | |
| USB High-Speed register block structure | |
| Windowed Watchdog register block structure | |
| Memory test address/size and result structure | |
| LPC18XX_43XX OTP API structure | |
| Array of pin definitions passed to Chip_SCU_SetPinMuxing() must be in this format | |
| PLL Parameter strucutre | |
| SDIO chained DMA descriptor | |
| Ring buffer structure | |
| Event Monitor/Recorder Timestamp structure | |
| SDIO device type | |
| SD/MMC Card specific setup data structure | |
| Context for enumerating devices | |
| Register device data node | |
| Register device data | |
| Device identification data | |
| LPCSPIFILIB family descriptor, used to describe devices to non-device specific functions | |
| Device specific function pointers | |
| LPCSPIFILIB family data | |
| LPCSPIFILIB device handle, used with all device and info functions | |
| Common data applicable to all devices | |
1.8.3.1