LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/clock_18xx_43xx.c File Reference

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clock_18xx_43xx.c File Reference
`#include "chip.h"`

Go to the source code of this file.

## Data Structures
struct | CLK_PERIPH_TO_BASE_T

## Macros
#define | CRYSTAL_32K_FREQ_IN (32 * 1024)

## Functions
__STATIC_INLINE uint32_t | ABS (int val)
static void | pll_calc_divs (uint32_t freq, PLL_PARAM_T *ppll)
static void | pll_get_frac (uint32_t freq, PLL_PARAM_T *ppll)
static uint32_t | Chip_Clock_TestMainPLLMultiplier (uint32_t InputHz, uint32_t TestMult, uint32_t MinHz, uint32_t MaxHz)
static uint32_t | Chip_Clock_GetDivRate (CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider)
static CHIP_CGU_BASE_CLK_T | Chip_Clock_FindBaseClock (CHIP_CCU_CLK_T clk)
void | Chip_Clock_EnableCrystal (void)
| Enables the crystal oscillator. More...
int | Chip_Clock_CalcMainPLLValue (uint32_t freq, PLL_PARAM_T *ppll)
| Calculate main PLL Pre, Post and M div values. More...
void | Chip_Clock_DisableCrystal (void)
| Disables the crystal oscillator. More...
uint32_t | Chip_Clock_SetupMainPLLHz (CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz)
| Configures the main PLL. More...
uint32_t | Chip_Clock_SetupMainPLLMult (CHIP_CGU_CLKIN_T Input, uint32_t mult)
| Directly set the PLL multipler. More...
uint32_t | Chip_Clock_GetMainPLLHz (void)
| Returns the frequency of the main PLL. More...
void | Chip_Clock_SetDivider (CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor)
| Sets up a CGU clock divider and it's input clock. More...
CHIP_CGU_CLKIN_T | Chip_Clock_GetDividerSource (CHIP_CGU_IDIV_T Divider)
| Gets a CGU clock divider source. More...
uint32_t | Chip_Clock_GetDividerDivisor (CHIP_CGU_IDIV_T Divider)
| Gets a CGU clock divider divisor. More...
uint32_t | Chip_Clock_GetClockInputHz (CHIP_CGU_CLKIN_T input)
| Returns the frequency of the specified input clock source. More...
uint32_t | Chip_Clock_GetBaseClocktHz (CHIP_CGU_BASE_CLK_T clock)
| Returns the frequency of the specified base clock source. More...
void | Chip_Clock_SetBaseClock (CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
| Sets a CGU Base Clock clock source. More...
void | Chip_Clock_GetBaseClockOpts (CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken, bool *powerdn)
| Get CGU Base Clock clock source information. More...
void | Chip_Clock_EnableBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
| Enables a base clock source. More...
void | Chip_Clock_DisableBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
| Disables a base clock source. More...
bool | Chip_Clock_IsBaseClockEnabled (CHIP_CGU_BASE_CLK_T BaseClock)
| Returns base clock enable state. More...
CHIP_CGU_CLKIN_T | Chip_Clock_GetBaseClock (CHIP_CGU_BASE_CLK_T BaseClock)
| Gets a CGU Base Clock clock source. More...
void | Chip_Clock_EnableOpts (CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div)
| Enables a peripheral clock and sets clock states. More...
void | Chip_Clock_Enable (CHIP_CCU_CLK_T clk)
| Enables a peripheral clock. More...
void | Chip_Clock_RTCEnable (void)
| Enables RTCclock. More...
void | Chip_Clock_Disable (CHIP_CCU_CLK_T clk)
| Disables a peripheral clock. More...
void | Chip_Clock_StartPowerDown (void)
| Start the power down sequence by disabling the branch output clocks with wake up mechanism (Only the clocks which wake up mechanism bit enabled will be disabled) More...
void | Chip_Clock_ClearPowerDown (void)
| Clear the power down mode bit & proceed normal operation of branch output clocks (Only the clocks which wake up mechanism bit enabled will be enabled after the wake up event) More...
uint32_t | Chip_Clock_GetRate (CHIP_CCU_CLK_T clk)
| Returns a peripheral clock rate. More...
uint32_t | Chip_Clock_GetEMCRate (void)
| Returns EMC clock rate. More...
void | Chip_Clock_SetupPLL (CHIP_CGU_CLKIN_T Input, CHIP_CGU_USB_AUDIO_PLL_T pllnum, const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup)
| Sets up the audio or USB PLL. More...
void | Chip_Clock_EnablePLL (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
| Enables the audio or USB PLL. More...
void | Chip_Clock_DisablePLL (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
| Disables the audio or USB PLL. More...
uint32_t | Chip_Clock_GetPLLStatus (CHIP_CGU_USB_AUDIO_PLL_T pllnum)
| Returns the PLL status. More...

## Variables
static const CLK_PERIPH_TO_BASE_T | periph_to_base []
static uint32_t | audio_usb_pll_freq [CGU_AUDIO_PLL+1]

## Macro Definition Documentation

#define CRYSTAL_32K_FREQ_IN (32 * 1024)

Definition at line 68 of file clock_18xx_43xx.c.

## Function Documentation

__STATIC_INLINE uint32_t ABS | ( | int | val | ) |

Definition at line 80 of file clock_18xx_43xx.c.

static CHIP_CGU_BASE_CLK_T Chip_Clock_FindBaseClock | ( | CHIP_CCU_CLK_T | clk | ) |
| static

Definition at line 205 of file clock_18xx_43xx.c.

static uint32_t Chip_Clock_GetDivRate | ( | CHIP_CGU_CLKIN_T | clock,
|  | CHIP_CGU_IDIV_T | divider
| ) |  |
| static

Definition at line 194 of file clock_18xx_43xx.c.

static uint32_t Chip_Clock_TestMainPLLMultiplier | ( | uint32_t | InputHz,
|  | uint32_t | TestMult,
|  | uint32_t | MinHz,
|  | uint32_t | MaxHz
| ) |  |
| static

Definition at line 182 of file clock_18xx_43xx.c.

static void pll_calc_divs | ( | uint32_t | freq,
|  | PLL_PARAM_T * | ppll
| ) |  |
| static

Definition at line 87 of file clock_18xx_43xx.c.

static void pll_get_frac | ( | uint32_t | freq,
|  | PLL_PARAM_T * | ppll
| ) |  |
| static

Definition at line 127 of file clock_18xx_43xx.c.

## Variable Documentation

uint32_t audio_usb_pll_freq[CGU_AUDIO_PLL+1]
| static

Definition at line 71 of file clock_18xx_43xx.c.

const CLK_PERIPH_TO_BASE_T periph_to_base[]
| static

Initial value:
= {
{CLK_APB3_BUS, CLK_APB3_CAN0, CLK_BASE_APB3},
{CLK_APB1_BUS, CLK_APB1_CAN1, CLK_BASE_APB1},
{CLK_SPIFI, CLK_SPIFI, CLK_BASE_SPIFI},
{CLK_MX_BUS, CLK_MX_QEI, CLK_BASE_MX},
{CLK_USB0, CLK_USB0, CLK_BASE_USB0},
{CLK_USB1, CLK_USB1, CLK_BASE_USB1},
{CLK_APLL, CLK_APLL, CLK_BASE_APLL},
{CLK_APB2_UART3, CLK_APB2_UART3, CLK_BASE_UART3},
{CLK_APB2_UART2, CLK_APB2_UART2, CLK_BASE_UART2},
{CLK_APB0_UART1, CLK_APB0_UART1, CLK_BASE_UART1},
{CLK_APB0_UART0, CLK_APB0_UART0, CLK_BASE_UART0},
{CLK_APB2_SSP1, CLK_APB2_SSP1, CLK_BASE_SSP1},
{CLK_APB0_SSP0, CLK_APB0_SSP0, CLK_BASE_SSP0},
{CLK_APB2_SDIO, CLK_APB2_SDIO, CLK_BASE_SDIO},
{CLK_CCU2_LAST, CLK_CCU2_LAST, CLK_BASE_NONE}
}

Definition at line 43 of file clock_18xx_43xx.c.