LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/emc_18xx_43xx.h Source File

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emc_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx EMC driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __EMC_18XX_43XX_H_
33 #define __EMC_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
49 typedef struct {
50 __IO uint32_t CONTROL;
51 __I uint32_t STATUS;
52 __IO uint32_t CONFIG;
53 __I uint32_t RESERVED0[5];
54 __IO uint32_t DYNAMICCONTROL;
55 __IO uint32_t DYNAMICREFRESH;
56 __IO uint32_t DYNAMICREADCONFIG;
57 __I uint32_t RESERVED1;
58 __IO uint32_t DYNAMICRP;
59 __IO uint32_t DYNAMICRAS;
60 __IO uint32_t DYNAMICSREX;
61 __IO uint32_t DYNAMICAPR;
62 __IO uint32_t DYNAMICDAL;
63 __IO uint32_t DYNAMICWR;
64 __IO uint32_t DYNAMICRC;
65 __IO uint32_t DYNAMICRFC;
66 __IO uint32_t DYNAMICXSR;
67 __IO uint32_t DYNAMICRRD;
68 __IO uint32_t DYNAMICMRD;
69 __I uint32_t RESERVED2[9];
70 __IO uint32_t STATICEXTENDEDWAIT;
71 __I uint32_t RESERVED3[31];
72 __IO uint32_t DYNAMICCONFIG0;
73 __IO uint32_t DYNAMICRASCAS0;
74 __I uint32_t RESERVED4[6];
75 __IO uint32_t DYNAMICCONFIG1;
76 __IO uint32_t DYNAMICRASCAS1;
77 __I uint32_t RESERVED5[6];
78 __IO uint32_t DYNAMICCONFIG2;
79 __IO uint32_t DYNAMICRASCAS2;
80 __I uint32_t RESERVED6[6];
81 __IO uint32_t DYNAMICCONFIG3;
82 __IO uint32_t DYNAMICRASCAS3;
83 __I uint32_t RESERVED7[38];
84 __IO uint32_t STATICCONFIG0;
85 __IO uint32_t STATICWAITWEN0;
86 __IO uint32_t STATICWAITOEN0;
87 __IO uint32_t STATICWAITRD0;
88 __IO uint32_t STATICWAITPAG0;
89 __IO uint32_t STATICWAITWR0;
90 __IO uint32_t STATICWAITTURN0;
91 __I uint32_t RESERVED8;
92 __IO uint32_t STATICCONFIG1;
93 __IO uint32_t STATICWAITWEN1;
94 __IO uint32_t STATICWAITOEN1;
95 __IO uint32_t STATICWAITRD1;
96 __IO uint32_t STATICWAITPAG1;
97 __IO uint32_t STATICWAITWR1;
98 __IO uint32_t STATICWAITTURN1;
99 __I uint32_t RESERVED9;
100 __IO uint32_t STATICCONFIG2;
101 __IO uint32_t STATICWAITWEN2;
102 __IO uint32_t STATICWAITOEN2;
103 __IO uint32_t STATICWAITRD2;
104 __IO uint32_t STATICWAITPAG2;
105 __IO uint32_t STATICWAITWR2;
106 __IO uint32_t STATICWAITTURN2;
107 __I uint32_t RESERVED10;
108 __IO uint32_t STATICCONFIG3;
109 __IO uint32_t STATICWAITWEN3;
110 __IO uint32_t STATICWAITOEN3;
111 __IO uint32_t STATICWAITRD3;
112 __IO uint32_t STATICWAITPAG3;
113 __IO uint32_t STATICWAITWR3;
114 __IO uint32_t STATICWAITTURN3;
115 } LPC_EMC_T;
116
120 #define EMC_ADDRESS_DYCS0 (0x28000000)
121 #define EMC_ADDRESS_DYCS1 (0x30000000)
122 #define EMC_ADDRESS_DYCS2 (0x60000000)
123 #define EMC_ADDRESS_DYCS3 (0x70000000)
124
128 #define EMC_ADDRESS_CS0 (0x1C000000)
129 #define EMC_ADDRESS_CS1 (0x1D000000)
130 #define EMC_ADDRESS_CS2 (0x1E000000)
131 #define EMC_ADDRESS_CS3 (0x1F000000)
132
136 /* Reserve for extending support to ARM9 or nextgen LPC */
137 #define EMC_SUPPORT_ONLY_PL172
139 #define EMC_CONFIG_ENDIAN_LITTLE (0)
140 #define EMC_CONFIG_ENDIAN_BIG (1)
142 #define EMC_CONFIG_BUFFER_ENABLE (1 << 19)
143 #define EMC_CONFIG_WRITE_PROTECT (1 << 20)
145 /* Dynamic Memory Configuration Register Bit Definitions */
146 #define EMC_DYN_CONFIG_MD_BIT (3)
147 #define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT)
148 #define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT)
150 #define EMC_DYN_CONFIG_LPSDRAM_BIT (12)
151 #define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)
153 #define EMC_DYN_CONFIG_DEV_SIZE_BIT (9)
154 #define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
155 #define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
156 #define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
157 #define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
158 #define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
160 #define EMC_DYN_CONFIG_DEV_BUS_BIT (7)
161 #define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)
162 #define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)
163 #define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)
165 #define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14)
166 #define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
167 #define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
170 #define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7))
171 #define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7))
172 #define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7))
173 #define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7))
174 #define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7))
175 #define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7))
176 #define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7))
177 #define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7))
178 #define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7))
179 #define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7))
180 #define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7))
181 #define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7))
182 #define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7))
185 #define EMC_DYN_MODE_BURST_LEN_BIT (0)
186 #define EMC_DYN_MODE_BURST_LEN_1 (0)
187 #define EMC_DYN_MODE_BURST_LEN_2 (1)
188 #define EMC_DYN_MODE_BURST_LEN_4 (2)
189 #define EMC_DYN_MODE_BURST_LEN_8 (3)
190 #define EMC_DYN_MODE_BURST_LEN_FULL (7)
192 #define EMC_DYN_MODE_BURST_TYPE_BIT (3)
193 #define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT)
194 #define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT)
197 #define EMC_DYN_MODE_CAS_BIT (4)
198 #define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT)
199 #define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT)
200 #define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT)
203 #define EMC_DYN_MODE_OPMODE_BIT (7)
204 #define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT)
207 #define EMC_DYN_MODE_WBMODE_BIT (9)
208 #define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT)
209 #define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT)
212 #define EMC_DYN_CONTROL_ENABLE (0x03)
215 #define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0)
216 #define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1)
217 #define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2)
219 #define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3)
220 #define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)
222 #define EMC_STATIC_CONFIG_CS_POL_BIT (6)
223 #define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT)
224 #define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT)
226 #define EMC_STATIC_CONFIG_BLS_BIT (7)
227 #define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT)
228 #define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT)
230 #define EMC_STATIC_CONFIG_EW_BIT (8)
231 #define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT)
232 #define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT)
235 #define Q24_8_FP(x) ((x) * 256)
236 #define EMC_NANOSECOND(x) Q24_8_FP(x)
237 #define EMC_CLOCK(x) Q24_8_FP(-(x))
238
242 typedef struct {
243 uint32_t BaseAddr;
244 uint8_t RAS;
245 uint32_t ModeRegister;
246 uint32_t DynConfig;
247 } IP_EMC_DYN_DEVICE_CONFIG_T;
248
252 typedef struct {
253 int32_t RefreshPeriod;
254 uint32_t ReadConfig;
255 int32_t tRP;
256 int32_t tRAS;
257 int32_t tSREX;
258 int32_t tAPR;
259 int32_t tDAL;
260 int32_t tWR;
261 int32_t tRC;
262 int32_t tRFC;
263 int32_t tXSR;
264 int32_t tRRD;
265 int32_t tMRD;
266 IP_EMC_DYN_DEVICE_CONFIG_T DevConfig[4];
267 } IP_EMC_DYN_CONFIG_T;
268
272 typedef struct {
273 uint8_t ChipSelect;
274 uint32_t Config;
275 int32_t WaitWen;
276 int32_t WaitOen;
277 int32_t WaitRd;
278 int32_t WaitPage;
279 int32_t WaitWr;
280 int32_t WaitTurn;
281 } IP_EMC_STATIC_CONFIG_T;
282
288 void Chip_EMC_Dynamic_Init(IP_EMC_DYN_CONFIG_T *Dynamic_Config);
289
295 void Chip_EMC_Static_Init(IP_EMC_STATIC_CONFIG_T *Static_Config);
296
302 void Chip_EMC_Dynamic_Enable(uint8_t Enable);
303
309 void Chip_EMC_Mirror(uint8_t Enable);
310
316 void Chip_EMC_Enable(uint8_t Enable);
317
325 void Chip_EMC_LowPowerMode(uint8_t Enable);
326
334 void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
335
341 STATIC INLINE void Chip_EMC_SetStaticExtendedWait(uint32_t Wait16Clks)
342 {
343 LPC_EMC->STATICEXTENDEDWAIT = Wait16Clks;
344 }
345
350 #ifdef __cplusplus
351 }
352 #endif
353
354 #endif /* __EMC_18XX_43XX_H_ */