LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/hsadc_18xx_43xx.h Source File

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hsadc_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx High speed ADC driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __HSADC_18XX_43XX_H_
33 #define __HSADC_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __O uint32_t CLR_EN;
49 __O uint32_t SET_EN;
50 __I uint32_t MASK;
51 __I uint32_t STATUS;
52 __O uint32_t CLR_STAT;
53 __O uint32_t SET_STAT;
54 uint32_t RESERVED[2];
55 } HSADCINTCTRL_T;
56
60 typedef struct {
61 __O uint32_t FLUSH;
62 __IO uint32_t DMA_REQ;
63 __I uint32_t FIFO_STS;
64 __IO uint32_t FIFO_CFG;
65 __O uint32_t TRIGGER;
66 __IO uint32_t DSCR_STS;
67 __IO uint32_t POWER_DOWN;
68 __IO uint32_t CONFIG;
69 __IO uint32_t THR[2];
70 __I uint32_t LAST_SAMPLE[6];
71 uint32_t RESERVED0[49];
72 __IO uint32_t ADC_SPEED;
73 __IO uint32_t POWER_CONTROL;
74 uint32_t RESERVED1[61];
75 __I uint32_t FIFO_OUTPUT[16];
76 uint32_t RESERVED2[48];
77 __IO uint32_t DESCRIPTOR[2][8];
78 uint32_t RESERVED3[752];
79 HSADCINTCTRL_T INTS[2];
80 } LPC_HSADC_T;
81
82 #define HSADC_MAX_SAMPLEVAL 0xFFF
83
89 void Chip_HSADC_Init(LPC_HSADC_T *pHSADC);
90
96 void Chip_HSADC_DeInit(LPC_HSADC_T *pHSADC);
97
103 STATIC INLINE void Chip_HSADC_FlushFIFO(LPC_HSADC_T *pHSADC)
104 {
105 pHSADC->FLUSH = 1;
106 }
107
114 STATIC INLINE void Chip_HSADC_LoadDMADesc(LPC_HSADC_T *pHSADC)
115 {
116 pHSADC->DMA_REQ = 1;
117 }
118
125 STATIC INLINE uint32_t Chip_HSADC_GetFIFOLevel(LPC_HSADC_T *pHSADC)
126 {
127 return pHSADC->FIFO_STS;
128 }
129
140 void Chip_HSADC_SetupFIFO(LPC_HSADC_T *pHSADC, uint8_t trip, bool packed);
141
147 STATIC INLINE void Chip_HSADC_SWTrigger(LPC_HSADC_T *pHSADC)
148 {
149 pHSADC->TRIGGER = 1;
150 }
151
163 STATIC INLINE void Chip_HSADC_SetActiveDescriptor(LPC_HSADC_T *pHSADC, uint8_t table, uint8_t desc)
164 {
165 pHSADC->DSCR_STS = (uint32_t) ((desc << 1) | table);
166 }
167
173 STATIC INLINE uint8_t Chip_HSADC_GetActiveDescriptorIndex(LPC_HSADC_T *pHSADC)
174 {
175 return (uint8_t) ((pHSADC->DSCR_STS >> 1) & 0x7);
176 }
177
183 STATIC INLINE uint8_t Chip_HSADC_GetActiveDescriptorTable(LPC_HSADC_T *pHSADC)
184 {
185 return (uint8_t) (pHSADC->DSCR_STS & 1);
186 }
187
195 STATIC INLINE void Chip_HSADC_EnablePowerDownMode(LPC_HSADC_T *pHSADC)
196 {
197 pHSADC->POWER_DOWN = 1;
198 }
199
207 STATIC INLINE void Chip_HSADC_DisablePowerDownMode(LPC_HSADC_T *pHSADC)
208 {
209 pHSADC->POWER_DOWN = 0;
210 }
211
212 /* HSADC trigger configuration mask types */
213 typedef enum {
214 HSADC_CONFIG_TRIGGER_OFF = 0,
215 HSADC_CONFIG_TRIGGER_SW = 1,
216 HSADC_CONFIG_TRIGGER_EXT = 2,
217 HSADC_CONFIG_TRIGGER_BOTH = 3
218 } HSADC_TRIGGER_MASK_T;
219
220 /* HSADC trigger configuration mode types */
221 typedef enum {
222 HSADC_CONFIG_TRIGGER_RISEEXT = (0 << 2),
223 HSADC_CONFIG_TRIGGER_FALLEXT = (1 << 2),
224 HSADC_CONFIG_TRIGGER_LOWEXT = (2 << 2),
225 HSADC_CONFIG_TRIGGER_HIGHEXT = (3 << 2)
226 } HSADC_TRIGGER_MODE_T;
227
228 /* HSADC trigger configuration sync types */
229 typedef enum {
230 HSADC_CONFIG_TRIGGER_NOEXTSYNC = (0 << 4),
231 HSADC_CONFIG_TRIGGER_EXTSYNC = (1 << 4),
232 } HSADC_TRIGGER_SYNC_T;
233
234 /* HSADC trigger configuration channel ID */
235 typedef enum {
236 HSADC_CHANNEL_ID_EN_NONE = (0 << 5),
237 HSADC_CHANNEL_ID_EN_ADD = (1 << 5),
238 } HSADC_CHANNEL_ID_EN_T;
239
250 STATIC INLINE void Chip_HSADC_ConfigureTrigger(LPC_HSADC_T *pHSADC,
251 HSADC_TRIGGER_MASK_T mask,
252 HSADC_TRIGGER_MODE_T mode,
253 HSADC_TRIGGER_SYNC_T sync,
254 HSADC_CHANNEL_ID_EN_T chID, uint16_t recoveryTime)
255 {
256 pHSADC->CONFIG = (uint32_t) mask | (uint32_t) mode | (uint32_t) sync |
257 (uint32_t) chID | (uint32_t) (recoveryTime << 6);
258 }
259
267 void Chip_HSADC_SetThrLowValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value);
268
276 void Chip_HSADC_SetThrHighValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value);
277
279 #define HSADC_LS_DONE (1 << 0)
280 #define HSADC_LS_OVERRUN (1 << 1)
281 #define HSADC_LS_RANGE_IN (0 << 2)
282 #define HSADC_LS_RANGE_BELOW (1 << 2)
283 #define HSADC_LS_RANGE_ABOVE (2 << 2)
284 #define HSADC_LS_RANGE(val) ((val) & 0xC)
285 #define HSADC_LS_CROSSING_NONE (0 << 4)
286 #define HSADC_LS_CROSSING_DOWN (1 << 4)
287 #define HSADC_LS_CROSSING_UP (2 << 4)
288 #define HSADC_LS_CROSSING(val) ((val) & 0x30)
289 #define HSADC_LS_DATA(val) ((val) >> 6)
305 STATIC INLINE uint32_t Chip_HSADC_GetLastSample(LPC_HSADC_T *pHSADC, uint8_t channel)
306 {
307 return pHSADC->LAST_SAMPLE[channel];
308 }
309
319 void Chip_HSADC_SetSpeed(LPC_HSADC_T *pHSADC, uint8_t channel, uint8_t speed);
320
333 void Chip_HSADC_SetPowerSpeed(LPC_HSADC_T *pHSADC, bool comp2);
334
335 /* AC-DC coupling selection for vin_neg and vin_pos sides */
336 typedef enum {
337 HSADC_CHANNEL_NODCBIAS = 0,
338 HSADC_CHANNEL_DCBIAS = 1,
339 } HSADC_DCBIAS_T;
340
355 void Chip_HSADC_SetACDCBias(LPC_HSADC_T *pHSADC, uint8_t channel,
356 HSADC_DCBIAS_T dcInNeg, HSADC_DCBIAS_T dcInPos);
357
365 STATIC INLINE void Chip_HSADC_EnablePower(LPC_HSADC_T *pHSADC)
366 {
367 pHSADC->POWER_CONTROL |= (1 << 17) | (1 << 18);
368 }
369
377 STATIC INLINE void Chip_HSADC_DisablePower(LPC_HSADC_T *pHSADC)
378 {
379 pHSADC->POWER_CONTROL &= ~((1 << 17) | (1 << 18));
380 }
381
383 #define HSADC_FIFO_SAMPLE_MASK (0xFFF)
384 #define HSADC_FIFO_SAMPLE(val) ((val) & 0xFFF)
385 #define HSADC_FIFO_CHAN_ID_MASK (0x7000)
386 #define HSADC_FIFO_CHAN_ID(val) (((val) >> 12) & 0x7)
387 #define HSADC_FIFO_EMPTY (0x1 << 15)
388 #define HSADC_FIFO_SHIFTPACKED(val) ((val) >> 16)
389 #define HSADC_FIFO_PACKEDMASK (1UL << 31)
402 STATIC INLINE uint32_t Chip_HSADC_GetFIFO(LPC_HSADC_T *pHSADC)
403 {
404 return pHSADC->FIFO_OUTPUT[0];
405 }
406
408 #define HSADC_DESC_CH(ch) (ch)
409 #define HSADC_DESC_HALT (1 << 3)
410 #define HSADC_DESC_INT (1 << 4)
411 #define HSADC_DESC_POWERDOWN (1 << 5)
412 #define HSADC_DESC_BRANCH_NEXT (0 << 6)
413 #define HSADC_DESC_BRANCH_FIRST (1 << 6)
414 #define HSADC_DESC_BRANCH_SWAP (2 << 6)
415 #define HSADC_DESC_MATCH(val) ((val) << 8)
416 #define HSADC_DESC_THRESH_NONE (0 << 22)
417 #define HSADC_DESC_THRESH_A (1 << 22)
418 #define HSADC_DESC_THRESH_B (2 << 22)
419 #define HSADC_DESC_RESET_TIMER (1 << 24)
420 #define HSADC_DESC_UPDATE_TABLE (1UL << 31)
438 STATIC INLINE void Chip_HSADC_SetupDescEntry(LPC_HSADC_T *pHSADC, uint8_t table,
439 uint8_t descNo, uint32_t desc)
440 {
441 pHSADC->DESCRIPTOR[table][descNo] = desc;
442 }
443
453 STATIC INLINE void Chip_HSADC_UpdateDescTable(LPC_HSADC_T *pHSADC, uint8_t table)
454 {
455 pHSADC->DESCRIPTOR[table][0] |= HSADC_DESC_UPDATE_TABLE;
456 }
457
458 /* Interrupt selection for interrupt 0 set - these interrupts and statuses
459 should only be used with the interrupt 0 register set */
460 #define HSADC_INT0_FIFO_FULL (1 << 0)
461 #define HSADC_INT0_FIFO_EMPTY (1 << 1)
462 #define HSADC_INT0_FIFO_OVERFLOW (1 << 2)
463 #define HSADC_INT0_DSCR_DONE (1 << 3)
464 #define HSADC_INT0_DSCR_ERROR (1 << 4)
465 #define HSADC_INT0_ADC_OVF (1 << 5)
466 #define HSADC_INT0_ADC_UNF (1 << 6)
468 /* Interrupt selection for interrupt 1 set - these interrupts and statuses
469 should only be used with the interrupt 1 register set */
470 #define HSADC_INT1_THCMP_BRANGE(ch) (1 << ((ch * 5) + 0))
471 #define HSADC_INT1_THCMP_ARANGE(ch) (1 << ((ch * 5) + 1))
472 #define HSADC_INT1_THCMP_DCROSS(ch) (1 << ((ch * 5) + 2))
473 #define HSADC_INT1_THCMP_UCROSS(ch) (1 << ((ch * 5) + 3))
474 #define HSADC_INT1_OVERRUN(ch) (1 << ((ch * 5) + 4))
484 STATIC INLINE void Chip_HSADC_EnableInts(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t intMask)
485 {
486 pHSADC->INTS[intGrp].SET_EN = intMask;
487 }
488
497 STATIC INLINE void Chip_HSADC_DisableInts(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t intMask)
498 {
499 pHSADC->INTS[intGrp].CLR_EN = intMask;
500 }
501
510 STATIC INLINE uint32_t Chip_HSADC_GetEnabledInts(LPC_HSADC_T *pHSADC, uint8_t intGrp)
511 {
512 return pHSADC->INTS[intGrp].MASK;
513 }
514
523 STATIC INLINE uint32_t Chip_HSADC_GetIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp)
524 {
525 return pHSADC->INTS[intGrp].STATUS;
526 }
527
536 STATIC INLINE void Chip_HSADC_ClearIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t stsMask)
537 {
538 pHSADC->INTS[intGrp].CLR_STAT = stsMask;
539 }
540
549 STATIC INLINE void Chip_HSADC_SetIntStatus(LPC_HSADC_T *pHSADC, uint8_t intGrp, uint32_t stsMask)
550 {
551 pHSADC->INTS[intGrp].SET_STAT = stsMask;
552 }
553
559 STATIC INLINE uint32_t Chip_HSADC_GetBaseClockRate(LPC_HSADC_T *pHSADC)
560 {
561 (void) pHSADC;
562
563 /* Return computed sample rate for the high speed ADC peripheral */
564 return Chip_Clock_GetRate(CLK_ADCHS);
565 }
566
571 #ifdef __cplusplus
572 }
573 #endif
574
575 #endif /* __HSADC_18XX_43XX_H_ */