32 #ifndef __SDIO_18XX_43XX_H_
33 #define __SDIO_18XX_43XX_H_
62 #define SDIO_CMD_RESP_R1 (1UL << 6)
63 #define SDIO_CMD_RESP_R2 (3UL << 6)
64 #define SDIO_CMD_RESP_R3 (1UL << 6)
65 #define SDIO_CMD_RESP_R4 (1UL << 6)
66 #define SDIO_CMD_RESP_R5 (1UL << 6)
67 #define SDIO_CMD_RESP_R6 (1UL << 6)
70 #define SDIO_CMD_CRC (1UL << 8)
71 #define SDIO_CMD_DATA (1UL << 9)
74 #define CMD0 (0 | (1 << 15))
75 #define CMD5 (5 | SDIO_CMD_RESP_R4)
76 #define CMD3 (3 | SDIO_CMD_RESP_R6)
77 #define CMD7 (7 | SDIO_CMD_RESP_R1)
78 #define CMD52 (52 | SDIO_CMD_RESP_R5 | SDIO_CMD_CRC)
79 #define CMD53 (53 | SDIO_CMD_RESP_R5 | SDIO_CMD_DATA | SDIO_CMD_CRC)
83 #define SDIO_ERR_FNUM -2
84 #define SDIO_ERR_READWRITE -3
85 #define SDIO_ERR_VOLT -4
86 #define SDIO_ERR_RCA -5
87 #define SDIO_ERR_INVFUNC -6
88 #define SDIO_ERR_INVARG -7
90 #define SDIO_VOLT_3_3 0x00100000UL
99 #define SDIO_MODE_BLOCK (1UL << 27)
111 #define SDIO_MODE_BUFFER (1UL << 26)
114 #define SDIO_AREA_CIA 0
117 #define SDIO_CCCR_LSC 0x40u
118 #define SDIO_CCCR_4BLS 0x80u
120 #define SDIO_POWER_INIT 1
122 #define SDIO_CLK_HISPEED 33000000UL
123 #define SDIO_CLK_FULLSPEED 16000000UL
124 #define SDIO_CLK_LOWSPEED 400000
235 uint32_t dest_addr,
const uint8_t *src_addr,
236 uint32_t size, uint32_t flags);
252 uint8_t *dest_addr, uint32_t src_addr,
253 uint32_t size, uint32_t flags);