LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_board/boards_18xx/keil_mcb_1857/board_sysinit.c Source File

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board_sysinit.c
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1 /*
2 * Copyright(C) NXP Semiconductors, 2012
3 * All rights reserved.
4 *
5 * Software that is described herein is for illustrative purposes only
6 * which provides customers with programming information regarding the
7 * LPC products. This software is supplied "AS IS" without any warranties of
8 * any kind, and NXP Semiconductors and its licensor disclaim any and
9 * all warranties, express or implied, including all implied warranties of
10 * merchantability, fitness for a particular purpose and non-infringement of
11 * intellectual property rights. NXP Semiconductors assumes no responsibility
12 * or liability for the use of the software, conveys no license or rights under any
13 * patent, copyright, mask work right, or any other intellectual property rights in
14 * or to any products. NXP Semiconductors reserves the right to make changes
15 * in the software without notification. NXP Semiconductors also makes no
16 * representation or warranty that such application will be suitable for the
17 * specified use without further testing or modification.
18 *
19 * Permission to use, copy, modify, and distribute this software and its
20 * documentation is hereby granted, under NXP Semiconductors' and its
21 * licensor's relevant copyrights in the software, without fee, provided that it
22 * is used in conjunction with NXP Semiconductors microcontrollers. This
23 * copyright, permission, and disclaimer notice must appear in all copies of
24 * this code.
25 */
26
27 #include "board.h"
28
29 /* The System initialization code is called prior to the application and
30 initializes the board for run-time operation. Board initialization
31 includes clock setup and default pin muxing configuration. */
32
33 /*****************************************************************************
34 * Private types/enumerations/variables
35 ****************************************************************************/
36
37 /* Structure for initial base clock states */
38 struct CLK_BASE_STATES {
39 CHIP_CGU_BASE_CLK_T clk; /* Base clock */
40 CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
41 bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
42 bool powerdn; /* Set to true if the base clock is initially powered down */
43 };
44
45 /* Initial base clock states are mostly on */
46 STATIC const struct CLK_BASE_STATES InitClkStates[] = {
47 {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
48 #if defined(USE_RMII)
49 {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
50 #else
51 {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
52 #endif
53
54 /* Clocks derived from dividers */
55 {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
56 {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
57 };
58
59 /* SPIFI high speed pin mode setup */
60 STATIC const PINMUX_GRP_T spifipinmuxing[] = {
61 {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
62 {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
63 {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
64 {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
65 {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
66 {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}
67 };
68
69 STATIC const PINMUX_GRP_T pinmuxing[] = {
70 /* RMII pin group */
71 {0x1, 19,
72 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
73 {0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
74 {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
75 {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
76 {0x1, 17,
77 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
78 {0xC, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
79 {0x1, 16,
80 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
81 {0x1, 15,
82 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
83 {0x0, 0,
84 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
85 /* External data lines D0 .. D15 */
86 {0x1, 7,
87 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
88 {0x1, 8,
89 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
90 {0x1, 9,
91 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
92 {0x1, 10,
93 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
94 {0x1, 11,
95 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
96 {0x1, 12,
97 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
98 {0x1, 13,
99 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
100 {0x1, 14,
101 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
102 {0x5, 4,
103 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
104 {0x5, 5,
105 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
106 {0x5, 6,
107 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
108 {0x5, 7,
109 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
110 {0x5, 0,
111 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
112 {0x5, 1,
113 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
114 {0x5, 2,
115 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
116 {0x5, 3,
117 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
118 {0xD, 2,
119 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
120 {0xD, 3,
121 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
122 {0xD, 4,
123 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
124 {0xD, 5,
125 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
126 {0xD, 6,
127 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
128 {0xD, 7,
129 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
130 {0xD, 8,
131 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
132 {0xD, 9,
133 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
134 {0xE, 5,
135 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
136 {0xE, 6,
137 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
138 {0xE, 7,
139 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
140 {0xE, 8,
141 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
142 {0xE, 9,
143 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
144 {0xE, 10,
145 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
146 {0xE, 11,
147 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
148 {0xE, 12,
149 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
150 /* Address lines A0 .. A23 */
151 {0x2, 9,
152 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
153 {0x2, 10,
154 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
155 {0x2, 11,
156 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
157 {0x2, 12,
158 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
159 {0x2, 13,
160 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
161 {0x1, 0,
162 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
163 {0x1, 1,
164 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
165 {0x1, 2,
166 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
167 {0x2, 8,
168 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
169 {0x2, 7,
170 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
171 {0x2, 6,
172 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
173 {0x2, 2,
174 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
175 {0x2, 1,
176 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
177 {0x2, 0,
178 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
179 {0x6, 8,
180 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
181 {0x6, 7,
182 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
183 {0xD, 16,
184 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
185 {0xD, 15,
186 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
187 {0xE, 0,
188 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
189 {0xE, 1,
190 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
191 {0xE, 2,
192 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
193 {0xE, 3,
194 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
195 {0xE, 4,
196 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
197 {0xA, 4,
198 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
199 /* EMC control signals */
200 {0x1, 4,
201 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
202 {0x6, 6,
203 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC1)},
204 {0xD, 13,
205 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
206 {0xD, 10,
207 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
208 {0x6, 9,
209 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
210 {0x1, 6,
211 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
212 {0x6, 4,
213 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
214 {0x6, 5,
215 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
216 {0x6, 11,
217 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
218 {0x6, 12,
219 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
220 {0x6, 10,
221 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
222 {0xD, 0,
223 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC2)},
224 {0xE, 13,
225 (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC3)},
226 {0x1, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
227 {0x1, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
228 {0x6, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC1)},
229 {0x1, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
230 {0x1, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
231 /* Board LEDs */
232 {0xD, 10, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
233 {0xD, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
234 {0xD, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
235 {0xD, 13, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
236 {0xD, 14, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC4)},
237 {0x9, 0, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
238 {0x9, 1, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
239 {0x9, 2, (SCU_MODE_INBUFF_EN | SCU_MODE_INACT | SCU_MODE_FUNC0)},
240 /* SSP0 */
241 {0xF, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC0)},
242 {0xF, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
243 {0xF, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
244 {0xF, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
245 /* LCD interface, 16bpp */
246 {0x4, 1, ( SCU_MODE_PULLUP | SCU_MODE_FUNC5)},
247 {0x4, 2, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
248 {0x4, 5, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
249 {0x4, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
250 {0x4, 7, ( SCU_MODE_PULLUP | SCU_MODE_FUNC0)},
251 {0x4, 9, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
252 {0x4, 10, (SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
253 {0x7, 0, ( SCU_MODE_PULLUP | SCU_MODE_FUNC0)},
254 {0x7, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
255 {0x8, 3, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
256 {0x8, 4, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
257 {0x8, 5, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
258 {0x8, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
259 {0x8, 7, ( SCU_MODE_PULLUP | SCU_MODE_FUNC3)},
260 {0xB, 0, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
261 {0xB, 1, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
262 {0xB, 2, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
263 {0xB, 3, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
264 {0xB, 4, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
265 {0xB, 5, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
266 {0xB, 6, ( SCU_MODE_PULLUP | SCU_MODE_FUNC2)},
267 /* I2S */
268 {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
269 {0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
270 {0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
271 {0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
272 {0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
273 {0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
274 /* CCAN */
275 {0x3, 2, (SCU_MODE_INACT | SCU_MODE_FUNC2)}, /* PE.3 CAN TD1 | SCU_MODE_FUNC1) */
276 {0x3, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC2)}, /* PE.2 CAN RD1 | SCU_MODE_FUNC1) */
277 };
278
279 /* Pin clock mux values, re-used structure, value in first index is meaningless */
280 STATIC const PINMUX_GRP_T pinclockmuxing[] = {
281 {0, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
282 {0, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
283 {0, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
284 {0, 3, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_FUNC0)},
285 };
286
287 /* EMC clock delay */
288 #define CLK0_DELAY 7
289
290 /* Keil SDRAM timing and chip Config */
291 STATIC const IP_EMC_DYN_CONFIG_T MT48LC4M32_config = {
292 EMC_NANOSECOND(64000000 / 4096), /* Row refresh time */
293 0x01, /* Command Delayed */
294 EMC_NANOSECOND(18),
295 EMC_NANOSECOND(42),
296 EMC_NANOSECOND(70),
297 EMC_CLOCK(0x01),
298 EMC_CLOCK(0x05),
299 EMC_NANOSECOND(12),
300 EMC_NANOSECOND(60),
301 EMC_NANOSECOND(60),
302 EMC_NANOSECOND(70),
303 EMC_NANOSECOND(12),
304 EMC_CLOCK(0x02),
305 {
306 {
307 EMC_ADDRESS_DYCS0, /* Keil Board uses DYCS0 for SDRAM */
308 3, /* RAS */
309
310 EMC_DYN_MODE_WBMODE_PROGRAMMED |
311 EMC_DYN_MODE_OPMODE_STANDARD |
312 EMC_DYN_MODE_CAS_3 |
313 EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
314 EMC_DYN_MODE_BURST_LEN_4,
315
316 EMC_DYN_CONFIG_DATA_BUS_32 |
317 EMC_DYN_CONFIG_LPSDRAM |
318 EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS |
319 EMC_DYN_CONFIG_MD_SDRAM
320 },
321 {0, 0, 0, 0},
322 {0, 0, 0, 0},
323 {0, 0, 0, 0}
324 }
325 };
326
327 /* Keil NorFlash timing and chip Config */
328 /* FIXME : Keil NOR FLASH not yet tested */
329 STATIC const IP_EMC_STATIC_CONFIG_T S29GL64N90_config = {
330 0,
331 EMC_STATIC_CONFIG_MEM_WIDTH_32 |
332 EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |
333 EMC_STATIC_CONFIG_BLS_HIGH /* |
334 EMC_CONFIG_BUFFER_ENABLE*/,
335
336 EMC_NANOSECOND(0),
337 EMC_NANOSECOND(65),
338 EMC_NANOSECOND(90),
339 EMC_NANOSECOND(90),
340 EMC_NANOSECOND(35),
341 EMC_CLOCK(4)
342 };
343
344 /*****************************************************************************
345 * Public types/enumerations/variables
346 ****************************************************************************/
347
348 /*****************************************************************************
349 * Private functions
350 ****************************************************************************/
351
352 /*****************************************************************************
353 * Public functions
354 ****************************************************************************/
355
356 /* Sets up system pin muxing */
357 void Board_SetupMuxing(void)
358 {
359 int i;
360
361 /* Setup system level pin muxing */
362 Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
363
364 /* Clock pins only, group field not used */
365 for (i = 0; i < (sizeof(pinclockmuxing) / sizeof(pinclockmuxing[0])); i++) {
366 Chip_SCU_ClockPinMuxSet(pinclockmuxing[i].pinnum, pinclockmuxing[i].modefunc);
367 }
368
369 /* SPIFI pin setup is done prior to setting up system clocking */
370 Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T));
371 }
372
373 /* Setup external memories */
374 void Board_SetupExtMemory(void)
375 {
376 /* Setup EMC Delays */
377 /* Move all clock delays together */
378 LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY) | (CLK0_DELAY << 4) | (CLK0_DELAY << 8) | (CLK0_DELAY << 12));
379
380 /* Setup EMC Clock Divider for divide by 2 - this is done in both the CCU (clocking)
381 and CREG. For frequencies over 120MHz, a divider of 2 must be used. For frequencies
382 less than 120MHz, a divider of 1 or 2 is ok. */
383 Chip_Clock_EnableOpts(CLK_MX_EMC_DIV, true, true, 2);
384 LPC_CREG->CREG6 |= (1 << 16);
385
386 /* Enable EMC clock */
387 Chip_Clock_Enable(CLK_MX_EMC);
388
389 /* Init EMC Controller -Enable-LE mode */
390 Chip_EMC_Init(1, 0, 0);
391 /* Init EMC Dynamic Controller */
392 Chip_EMC_Dynamic_Init((IP_EMC_DYN_CONFIG_T *) &MT48LC4M32_config);
393 /* Init EMC Static Controller CS0 */
394 Chip_EMC_Static_Init((IP_EMC_STATIC_CONFIG_T *) &S29GL64N90_config);
395
396 /* Enable Buffer for External Flash */
397 LPC_EMC->STATICCONFIG0 |= 1 << 19;
398 }
399
400 /* Set up and initialize clocking prior to call to main */
401 void Board_SetupClocking(void)
402 {
403 int i;
404
405 /* Setup FLASH acceleration to target clock rate prior to clock switch */
406 Chip_CREG_SetFlashAcceleration(MAX_CLOCK_FREQ);
407
408 Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
409
410 /* Setup system base clocks and initial states. This won't enable and
411 disable individual clocks, but sets up the base clock sources for
412 each individual peripheral clock. */
413 for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
414 Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
415 InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
416 }
417
418 /* Reset and enable 32Khz oscillator */
419 LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
420 LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
421
422 /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
423 Divide rate is based on CPU speed and speed of SPI FLASH part. */
424 #if (MAX_CLOCK_FREQ > 180000000)
425 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
426 #else
427 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
428 #endif
429 Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
430
431 /* LCD with HX8347-D LCD Controller */
432 /* Attach main PLL clock to divider C with a divider of 2 */
433 Chip_Clock_SetDivider(CLK_IDIV_C, CLKIN_MAINPLL, 2);
434 }
435
436 /* Set up and initialize hardware prior to call to main */
437 void Board_SystemInit(void)
438 {
439 /* Setup system clocking and memory. This is done early to allow the
440 application and tools to clear memory and use scatter loading to
441 external memory. */
442 Board_SetupMuxing();
443 Board_SetupClocking();
444 Board_SetupExtMemory();
445 }