LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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chip_18xx_43xx
enet_18xx_43xx.c
Go to the documentation of this file.
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/*
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* @brief LPC18xx/43xx Ethernet driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "
chip.h
"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/* Saved address for PHY and clock divider */
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STATIC
uint32_t
phyCfg
;
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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STATIC
INLINE
void
reset
(
LPC_ENET_T
*pENET)
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{
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Chip_RGU_TriggerReset
(
RGU_ETHERNET_RST
);
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while
(
Chip_RGU_InReset
(
RGU_ETHERNET_RST
))
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{}
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/* Reset ethernet peripheral */
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Chip_ENET_Reset
(pENET);
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}
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STATIC
uint32_t
Chip_ENET_CalcMDCClock
(
void
)
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{
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uint32_t val =
SystemCoreClock
/ 1000000UL;
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if
(val >= 20 && val < 35)
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return
2;
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if
(val >= 35 && val < 60)
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return
3;
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if
(val >= 60 && val < 100)
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return
0;
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if
(val >= 100 && val < 150)
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return
1;
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if
(val >= 150 && val < 250)
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return
4;
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if
(val >= 250 && val < 300)
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return
5;
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/* Code should never reach here
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unless there is BUG in frequency settings
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*/
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return
0;
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}
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Basic Ethernet interface initialization */
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void
Chip_ENET_Init
(
LPC_ENET_T
*pENET, uint32_t phyAddr)
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{
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Chip_Clock_EnableOpts
(
CLK_MX_ETHERNET
,
true
,
true
, 1);
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reset
(pENET);
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/* Setup MII link divider to /102 and PHY address 1 */
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Chip_ENET_SetupMII
(pENET,
Chip_ENET_CalcMDCClock
(), phyAddr);
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/* Enhanced descriptors, burst length = 1 */
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pENET->
DMA_BUS_MODE
=
DMA_BM_ATDS
|
DMA_BM_PBL
(1) |
DMA_BM_RPBL
(1);
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/* Initial MAC configuration for checksum offload, full duplex,
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100Mbps, disable receive own in half duplex, inter-frame gap
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of 64-bits */
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pENET->
MAC_CONFIG
=
MAC_CFG_BL
(0) |
MAC_CFG_IPC
|
MAC_CFG_DM
|
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MAC_CFG_DO
|
MAC_CFG_FES
|
MAC_CFG_PS
|
MAC_CFG_IFG
(3);
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/* Setup default filter */
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pENET->
MAC_FRAME_FILTER
=
MAC_FF_PR
|
MAC_FF_RA
;
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/* Flush transmit FIFO */
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pENET->
DMA_OP_MODE
=
DMA_OM_FTF
;
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/* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at
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64 bytes */
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pENET->
DMA_OP_MODE
|=
DMA_OM_RTC
(1) |
DMA_OM_TTC
(0);
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/* Clear all MAC interrupts */
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pENET->
DMA_STAT
=
DMA_ST_ALL
;
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/* Enable MAC interrupts */
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pENET->
DMA_INT_EN
= 0;
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}
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/* Ethernet interface shutdown */
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void
Chip_ENET_DeInit
(
LPC_ENET_T
*pENET)
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{
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/* Disable packet reception */
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pENET->
MAC_CONFIG
= 0;
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/* Flush transmit FIFO */
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pENET->
DMA_OP_MODE
=
DMA_OM_FTF
;
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/* Disable receive and transmit DMA processes */
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pENET->
DMA_OP_MODE
= 0;
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Chip_Clock_Disable
(
CLK_MX_ETHERNET
);
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}
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/* Sets up the PHY link clock divider and PHY address */
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void
Chip_ENET_SetupMII
(
LPC_ENET_T
*pENET, uint32_t div, uint8_t addr)
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{
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/* Save clock divider and PHY address in MII address register */
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phyCfg
=
MAC_MIIA_PA
(addr) |
MAC_MIIA_CR
(div);
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}
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/* Starts a PHY write via the MII */
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void
Chip_ENET_StartMIIWrite
(
LPC_ENET_T
*pENET, uint8_t reg, uint16_t data)
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{
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/* Write value at PHY address and register */
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pENET->
MAC_MII_ADDR
=
phyCfg
|
MAC_MIIA_GR
(reg) |
MAC_MIIA_W
;
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pENET->
MAC_MII_DATA
= (uint32_t) data;
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pENET->
MAC_MII_ADDR
|=
MAC_MIIA_GB
;
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}
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/*Starts a PHY read via the MII */
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void
Chip_ENET_StartMIIRead
(
LPC_ENET_T
*pENET, uint8_t reg)
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{
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/* Read value at PHY address and register */
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pENET->
MAC_MII_ADDR
=
phyCfg
|
MAC_MIIA_GR
(reg);
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pENET->
MAC_MII_ADDR
|=
MAC_MIIA_GB
;
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}
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/* Sets full or half duplex for the interface */
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void
Chip_ENET_SetDuplex
(
LPC_ENET_T
*pENET,
bool
full)
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{
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if
(full) {
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pENET->
MAC_CONFIG
|=
MAC_CFG_DM
;
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}
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else
{
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pENET->
MAC_CONFIG
&= ~
MAC_CFG_DM
;
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}
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}
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/* Sets speed for the interface */
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void
Chip_ENET_SetSpeed
(
LPC_ENET_T
*pENET,
bool
speed100)
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{
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if
(speed100) {
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pENET->
MAC_CONFIG
|=
MAC_CFG_FES
;
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}
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else
{
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pENET->
MAC_CONFIG
&= ~
MAC_CFG_FES
;
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}
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}
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