LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
Data Fields

Detailed Description

Motor Control PWM register block structure.

Definition at line 47 of file mcpwm_18xx_43xx.h.

#include "mcpwm_18xx_43xx.h"

Data Fields

__I uint32_t CON
 
__O uint32_t CON_SET
 
__O uint32_t CON_CLR
 
__I uint32_t CAPCON
 
__O uint32_t CAPCON_SET
 
__O uint32_t CAPCON_CLR
 
__IO uint32_t TC [3]
 
__IO uint32_t LIM [3]
 
__IO uint32_t MAT [3]
 
__IO uint32_t DT
 
__IO uint32_t CCP
 
__I uint32_t CAP [3]
 
__I uint32_t INTEN
 
__O uint32_t INTEN_SET
 
__O uint32_t INTEN_CLR
 
__I uint32_t CNTCON
 
__O uint32_t CNTCON_SET
 
__O uint32_t CNTCON_CLR
 
__I uint32_t INTF
 
__O uint32_t INTF_SET
 
__O uint32_t INTF_CLR
 
__O uint32_t CAP_CLR
 

Field Documentation

__I uint32_t CAP[3]

Capture register

Definition at line 59 of file mcpwm_18xx_43xx.h.

__O uint32_t CAP_CLR

Capture clear address

Definition at line 69 of file mcpwm_18xx_43xx.h.

__I uint32_t CAPCON

Capture Control read address

Definition at line 51 of file mcpwm_18xx_43xx.h.

__O uint32_t CAPCON_CLR

Event Control clear address

Definition at line 53 of file mcpwm_18xx_43xx.h.

__O uint32_t CAPCON_SET

Capture Control set address

Definition at line 52 of file mcpwm_18xx_43xx.h.

__IO uint32_t CCP

Communication Pattern register

Definition at line 58 of file mcpwm_18xx_43xx.h.

__I uint32_t CNTCON

Count Control read address

Definition at line 63 of file mcpwm_18xx_43xx.h.

__O uint32_t CNTCON_CLR

Count Control clear address

Definition at line 65 of file mcpwm_18xx_43xx.h.

__O uint32_t CNTCON_SET

Count Control set address

Definition at line 64 of file mcpwm_18xx_43xx.h.

__I uint32_t CON

< MCPWM Structure PWM Control read address

Definition at line 48 of file mcpwm_18xx_43xx.h.

__O uint32_t CON_CLR

PWM Control clear address

Definition at line 50 of file mcpwm_18xx_43xx.h.

__O uint32_t CON_SET

PWM Control set address

Definition at line 49 of file mcpwm_18xx_43xx.h.

__IO uint32_t DT

Dead time register

Definition at line 57 of file mcpwm_18xx_43xx.h.

__I uint32_t INTEN

Interrupt Enable read address

Definition at line 60 of file mcpwm_18xx_43xx.h.

__O uint32_t INTEN_CLR

Interrupt Enable clear address

Definition at line 62 of file mcpwm_18xx_43xx.h.

__O uint32_t INTEN_SET

Interrupt Enable set address

Definition at line 61 of file mcpwm_18xx_43xx.h.

__I uint32_t INTF

Interrupt flags read address

Definition at line 66 of file mcpwm_18xx_43xx.h.

__O uint32_t INTF_CLR

Interrupt flags clear address

Definition at line 68 of file mcpwm_18xx_43xx.h.

__O uint32_t INTF_SET

Interrupt flags set address

Definition at line 67 of file mcpwm_18xx_43xx.h.

__IO uint32_t LIM[3]

Limit register

Definition at line 55 of file mcpwm_18xx_43xx.h.

__IO uint32_t MAT[3]

Match register

Definition at line 56 of file mcpwm_18xx_43xx.h.

__IO uint32_t TC[3]

Timer Counter register

Definition at line 54 of file mcpwm_18xx_43xx.h.


The documentation for this struct was generated from the following file: