LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/chip_clocks.h File Reference

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chip_clocks.h File Reference

Go to the source code of this file.

## Macro Definition Documentation

#define CHIP_CGU_IDIV_MASK | ( |  | x | ) | ("\x03\x0F\x0F\x0F\xFF"[x])

Definition at line 140 of file chip_clocks.h.

## Enumeration Type Documentation

enum CHIP_CCU_CLK_T

Peripheral clocks Peripheral clocks are individual clocks routed to peripherals. Although multiple peripherals may share a same base clock, each peripheral's clock can be enabled or disabled individually. Some peripheral clocks also have additional dividers associated with them.

Enumerator
CLK_APB3_BUS | APB3 bus clock from base clock CLK_BASE_APB3
CLK_APB3_I2C1 | I2C1 register/perigheral clock from base clock CLK_BASE_APB3
CLK_APB3_DAC | DAC peripheral clock from base clock CLK_BASE_APB3
CLK_APB3_ADC0 | ADC0 register/perigheral clock from base clock CLK_BASE_APB3
CLK_APB3_ADC1 | ADC1 register/perigheral clock from base clock CLK_BASE_APB3
CLK_APB3_CAN0 | CAN0 register/perigheral clock from base clock CLK_BASE_APB3
CLK_APB1_BUS | APB1 bus clock clock from base clock CLK_BASE_APB1
CLK_APB1_MOTOCON | Motor controller register/perigheral clock from base clock CLK_BASE_APB1
CLK_APB1_I2C0 | I2C0 register/perigheral clock from base clock CLK_BASE_APB1
CLK_APB1_I2S | I2S register/perigheral clock from base clock CLK_BASE_APB1
CLK_APB1_CAN1 | CAN1 register/perigheral clock from base clock CLK_BASE_APB1
CLK_SPIFI | SPIFI SCKI input clock from base clock CLK_BASE_SPIFI
CLK_MX_BUS | M3/M4 BUS core clock from base clock CLK_BASE_MX
CLK_MX_SPIFI | SPIFI register clock from base clock CLK_BASE_MX
CLK_MX_GPIO | GPIO register clock from base clock CLK_BASE_MX
CLK_MX_LCD | LCD register clock from base clock CLK_BASE_MX
CLK_MX_ETHERNET | ETHERNET register clock from base clock CLK_BASE_MX
CLK_MX_USB0 | USB0 register clock from base clock CLK_BASE_MX
CLK_MX_EMC | EMC clock from base clock CLK_BASE_MX
CLK_MX_SDIO | SDIO register clock from base clock CLK_BASE_MX
CLK_MX_DMA | DMA register clock from base clock CLK_BASE_MX
CLK_MX_MXCORE | M3/M4 CPU core clock from base clock CLK_BASE_MX
RESERVED_ALIGN |
CLK_MX_SCT | SCT register clock from base clock CLK_BASE_MX
CLK_MX_USB1 | USB1 register clock from base clock CLK_BASE_MX
CLK_MX_EMC_DIV | ENC divider clock from base clock CLK_BASE_MX
CLK_MX_FLASHA | FLASHA bank clock from base clock CLK_BASE_MX
CLK_MX_FLASHB | FLASHB bank clock from base clock CLK_BASE_MX
CLK_RESERVED1 |
CLK_RESERVED2 |
CLK_MX_EEPROM | EEPROM clock from base clock CLK_BASE_MX
CLK_MX_WWDT | WWDT register clock from base clock CLK_BASE_MX
CLK_MX_UART0 | UART0 register clock from base clock CLK_BASE_MX
CLK_MX_UART1 | UART1 register clock from base clock CLK_BASE_MX
CLK_MX_SSP0 | SSP0 register clock from base clock CLK_BASE_MX
CLK_MX_TIMER0 | TIMER0 register/perigheral clock from base clock CLK_BASE_MX
CLK_MX_TIMER1 | TIMER1 register/perigheral clock from base clock CLK_BASE_MX
CLK_MX_SCU | SCU register/perigheral clock from base clock CLK_BASE_MX
CLK_MX_CREG | CREG clock from base clock CLK_BASE_MX
CLK_MX_RITIMER | RITIMER register/perigheral clock from base clock CLK_BASE_MX
CLK_MX_UART2 | UART3 register clock from base clock CLK_BASE_MX
CLK_MX_UART3 | UART4 register clock from base clock CLK_BASE_MX
CLK_MX_TIMER2 | TIMER2 register/perigheral clock from base clock CLK_BASE_MX
CLK_MX_TIMER3 | TIMER3 register/perigheral clock from base clock CLK_BASE_MX
CLK_MX_SSP1 | SSP1 register clock from base clock CLK_BASE_MX
CLK_MX_QEI | QEI register/perigheral clock from base clock CLK_BASE_MX
CLK_RESERVED3 |
CLK_RESERVED3A |
CLK_RESERVED4 |
CLK_RESERVED5 |
CLK_USB0 | USB0 clock from base clock CLK_BASE_USB0
CLK_USB1 | USB1 clock from base clock CLK_BASE_USB1
CLK_RESERVED7 |
CLK_RESERVED8 |
CLK_CCU1_LAST |
CLK_CCU2_START |
CLK_APLL | Audio PLL clock from base clock CLK_BASE_APLL
RESERVED_ALIGNB |
CLK_APB2_UART3 | UART3 clock from base clock CLK_BASE_UART3
RESERVED_ALIGNC |
CLK_APB2_UART2 | UART2 clock from base clock CLK_BASE_UART2
RESERVED_ALIGND |
CLK_APB0_UART1 | UART1 clock from base clock CLK_BASE_UART1
RESERVED_ALIGNE |
CLK_APB0_UART0 | UART0 clock from base clock CLK_BASE_UART0
RESERVED_ALIGNF |
CLK_APB2_SSP1 | SSP1 clock from base clock CLK_BASE_SSP1
RESERVED_ALIGNG |
CLK_APB0_SSP0 | SSP0 clock from base clock CLK_BASE_SSP0
RESERVED_ALIGNH |
CLK_APB2_SDIO | SDIO clock from base clock CLK_BASE_SDIO
CLK_CCU2_LAST |

Definition at line 149 of file chip_clocks.h.

enum CHIP_CGU_BASE_CLK_T

CGU base clocks CGU base clocks are clocks that are associated with a single input clock and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH clock can be configured to use the CLKIN_MAINPLL input clock, which will in turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and CLK_PERIPH_SGPIO periphral clocks.

Enumerator
CLK_BASE_SAFE | Base clock for WDT oscillator, IRC input only
CLK_BASE_USB0 | Base USB clock for USB0, USB PLL input only
CLK_BASE_RESERVED1 |
CLK_BASE_USB1 | Base USB clock for USB1
CLK_BASE_MX | Base clock for CPU core
CLK_BASE_SPIFI | Base clock for SPIFI
CLK_BASE_RESERVED2 |
CLK_BASE_PHY_RX | Base clock for PHY RX
CLK_BASE_PHY_TX | Base clock for PHY TX
CLK_BASE_APB1 | Base clock for APB1 group
CLK_BASE_APB3 | Base clock for APB3 group
CLK_BASE_LCD | Base clock for LCD pixel clock
CLK_BASE_RESERVED3 |
CLK_BASE_SDIO | Base clock for SDIO
CLK_BASE_SSP0 | Base clock for SSP0
CLK_BASE_SSP1 | Base clock for SSP1
CLK_BASE_UART0 | Base clock for UART0
CLK_BASE_UART1 | Base clock for UART1
CLK_BASE_UART2 | Base clock for UART2
CLK_BASE_UART3 | Base clock for UART3
CLK_BASE_OUT | Base clock for CLKOUT pin
CLK_BASE_RESERVED4 |
CLK_BASE_RESERVED5 |
CLK_BASE_RESERVED6 |
CLK_BASE_RESERVED7 |
CLK_BASE_APLL | Base clock for audio PLL
CLK_BASE_CGU_OUT0 | Base clock for CGUOUT0 pin
CLK_BASE_CGU_OUT1 | Base clock for CGUOUT1 pin
CLK_BASE_LAST |
CLK_BASE_NONE |

Definition at line 78 of file chip_clocks.h.

enum CHIP_CGU_IDIV_T

CGU dividers CGU dividers provide an extra clock state where a specific clock can be divided before being routed to a peripheral group. A divider accepts an input clock and then divides it. To use the divided clock for a base clock group, use the divider as the input clock for the base clock (for example, use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).

Enumerator
CLK_IDIV_A | CGU clock divider A
CLK_IDIV_B | CGU clock divider B
CLK_IDIV_C | CGU clock divider A
CLK_IDIV_D | CGU clock divider D
CLK_IDIV_E | CGU clock divider E
CLK_IDIV_LAST |

Definition at line 131 of file chip_clocks.h.