32 #ifndef __SSP_18XX_43XX_H_
33 #define __SSP_18XX_43XX_H_
65 #define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
67 #define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
69 #define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
71 #define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
74 #define SSP_CR0_CPOL_LO ((uint32_t) (0))
75 #define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
78 #define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
79 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
82 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
84 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
86 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
89 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
96 #define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
98 #define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
100 #define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
101 #define SSP_CR1_MASTER_EN ((uint32_t) (0))
104 #define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
106 #define SSP_CR1_BITMASK ((uint32_t) (0x0F))
109 #define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
115 #define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
122 #define SSP_SR_BITMASK ((uint32_t) (0x1F))
125 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
130 typedef enum _SSP_STATUS {
141 typedef enum _SSP_INTMASK {
152 typedef enum _SSP_MASKINTSTATUS {
163 typedef enum _SSP_RAWINTSTATUS {
171 typedef enum _SSP_INTCLEAR {
177 typedef enum _SSP_DMA {
186 typedef enum CHIP_SSP_CLOCK_FORMAT {
200 typedef enum CHIP_SSP_FRAME_FORMAT {
209 typedef enum CHIP_SSP_BITS {
343 pSSP->
ICR = IntClear;
415 pSSP->
CR0 = (pSSP->
CR0 & ~0xFF) | bits | frameFormat | clockMode;
428 pSSP->
CR1 = (pSSP->
CR1 & ~(1 << 2)) | mode;
454 typedef enum CHIP_SSP_MODE {
480 #define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
481 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
490 #define SSP_CPOL_HI SSP_CR0_CPOL_LO
491 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
494 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
495 #define SSP_MASTER_MODE SSP_CR1_MASTER_EN