LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/sysinit_18xx_43xx.c Source File

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sysinit_18xx_43xx.c
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1 /*
2 * @brief LPC18xx/LPC43xx Chip specific SystemInit
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #include "chip.h"
33
34 /*****************************************************************************
35 * Private types/enumerations/variables
36 ****************************************************************************/
37
38 /* Structure for initial base clock states */
39 struct CLK_BASE_STATES {
40 CHIP_CGU_BASE_CLK_T clk; /* Base clock */
41 CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
42 bool autoblock_enab; /* Set to true to enable autoblocking on frequency change */
43 bool powerdn; /* Set to true if the base clock is initially powered down */
44 };
45
46 static const struct CLK_BASE_STATES InitClkStates[] = {
47 {CLK_BASE_SAFE, CLKIN_IRC, true, false},
48 {CLK_BASE_APB1, CLKIN_MAINPLL, true, false},
49 {CLK_BASE_APB3, CLKIN_MAINPLL, true, false},
50 {CLK_BASE_USB0, CLKIN_USBPLL, true, true},
51 #if defined(CHIP_LPC43XX)
52 {CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false},
53 {CLK_BASE_SPI, CLKIN_MAINPLL, true, false},
54 {CLK_BASE_ADCHS, CLKIN_MAINPLL, true, true},
55 #endif
56 {CLK_BASE_SDIO, CLKIN_MAINPLL, true, false},
57 {CLK_BASE_SSP0, CLKIN_MAINPLL, true, false},
58 {CLK_BASE_SSP1, CLKIN_MAINPLL, true, false},
59 {CLK_BASE_UART0, CLKIN_MAINPLL, true, false},
60 {CLK_BASE_UART1, CLKIN_MAINPLL, true, false},
61 {CLK_BASE_UART2, CLKIN_MAINPLL, true, false},
62 {CLK_BASE_UART3, CLKIN_MAINPLL, true, false},
63 {CLK_BASE_OUT, CLKINPUT_PD, true, false},
64 {CLK_BASE_APLL, CLKINPUT_PD, true, false},
65 {CLK_BASE_CGU_OUT0, CLKINPUT_PD, true, false},
66 {CLK_BASE_CGU_OUT1, CLKINPUT_PD, true, false},
67 };
68
69 /*****************************************************************************
70 * Public types/enumerations/variables
71 ****************************************************************************/
72
73 /*****************************************************************************
74 * Private functions
75 ****************************************************************************/
76
77 /*****************************************************************************
78 * Public functions
79 ****************************************************************************/
80 /* Setup Chip Core clock */
81 void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbase)
82 {
83 int i;
84 volatile uint32_t delay = 500;
85 uint32_t direct = 0;
86 PLL_PARAM_T ppll;
87
88 if (clkin == CLKIN_CRYSTAL) {
89 /* Switch main system clocking to crystal */
90 Chip_Clock_EnableCrystal();
91 }
92 Chip_Clock_SetBaseClock(CLK_BASE_MX, clkin, true, false);
93 Chip_Clock_DisableMainPLL(); /* Disable PLL */
94
95 /* Calculate the PLL Parameters */
96 ppll.srcin = clkin;
97 Chip_Clock_CalcMainPLLValue(core_freq, &ppll);
98
99 if (core_freq > 110000000UL) {
100 if (!(ppll.ctrl & (1 << 7)) || ppll.psel) {
101 PLL_PARAM_T lpll;
102 /* Calculate the PLL Parameters */
103 lpll.srcin = clkin;
104 Chip_Clock_CalcMainPLLValue(110000000UL, &lpll);
105 Chip_Clock_SetupMainPLL(&lpll);
106 /* Wait for the PLL to lock */
107 while(!Chip_Clock_MainPLLLocked()) {}
108 Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
109 while(delay --){}
110 delay = 500;
111 } else {
112 direct = 1;
113 ppll.ctrl &= ~(1 << 7);
114 }
115 }
116
117 /* Setup and start the PLL */
118 Chip_Clock_SetupMainPLL(&ppll);
119
120 /* Wait for the PLL to lock */
121 while(!Chip_Clock_MainPLLLocked()) {}
122
123 /* Set core clock base as PLL1 */
124 Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
125
126 while(delay --){} /* Wait for approx 50 uSec */
127 if (direct) {
128 delay = 500;
129 ppll.ctrl |= 1 << 7;
130 Chip_Clock_SetupMainPLL(&ppll); /* Set DIRECT to operate at full frequency */
131 while(delay --){} /* Wait for approx 50 uSec */
132 }
133
134 if (setbase) {
135 /* Setup system base clocks and initial states. This won't enable and
136 disable individual clocks, but sets up the base clock sources for
137 each individual peripheral clock. */
138 for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
139 Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
140 InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
141 }
142 }
143 }
144
145 /* Setup system clocking */
146 void Chip_SetupXtalClocking(void)
147 {
148 Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
149 }
150
151 /* Set up and initialize hardware prior to call to main */
152 void Chip_SetupIrcClocking(void)
153 {
154 Chip_SetupCoreClock(CLKIN_IRC, MAX_CLOCK_FREQ, true);
155 }
156
157 /* Set up and initialize hardware prior to call to main */
158 void Chip_SystemInit(void)
159 {
160 /* Initial internal clocking */
161 Chip_SetupIrcClocking();
162 }