LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/sdif_18xx_43xx.h Source File

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sdif_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx SD/SDIO driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __SDIF_18XX_43XX_H_
33 #define __SDIF_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t CTRL;
49 __IO uint32_t PWREN;
50 __IO uint32_t CLKDIV;
51 __IO uint32_t CLKSRC;
52 __IO uint32_t CLKENA;
53 __IO uint32_t TMOUT;
54 __IO uint32_t CTYPE;
55 __IO uint32_t BLKSIZ;
56 __IO uint32_t BYTCNT;
57 __IO uint32_t INTMASK;
58 __IO uint32_t CMDARG;
59 __IO uint32_t CMD;
60 __I uint32_t RESP0;
61 __I uint32_t RESP1;
62 __I uint32_t RESP2;
63 __I uint32_t RESP3;
64 __I uint32_t MINTSTS;
65 __IO uint32_t RINTSTS;
66 __I uint32_t STATUS;
67 __IO uint32_t FIFOTH;
68 __I uint32_t CDETECT;
69 __I uint32_t WRTPRT;
70 __IO uint32_t GPIO;
71 __I uint32_t TCBCNT;
72 __I uint32_t TBBCNT;
73 __IO uint32_t DEBNCE;
74 __IO uint32_t USRID;
75 __I uint32_t VERID;
76 __I uint32_t RESERVED0;
77 __IO uint32_t UHS_REG;
78 __IO uint32_t RST_N;
79 __I uint32_t RESERVED1;
80 __IO uint32_t BMOD;
81 __O uint32_t PLDMND;
82 __IO uint32_t DBADDR;
83 __IO uint32_t IDSTS;
84 __IO uint32_t IDINTEN;
85 __I uint32_t DSCADDR;
86 __I uint32_t BUFADDR;
87 } LPC_SDMMC_T;
88
91 #define MCI_DMADES0_OWN (1UL << 31)
92 #define MCI_DMADES0_CES (1 << 30)
93 #define MCI_DMADES0_ER (1 << 5)
94 #define MCI_DMADES0_CH (1 << 4)
95 #define MCI_DMADES0_FS (1 << 3)
96 #define MCI_DMADES0_LD (1 << 2)
97 #define MCI_DMADES0_DIC (1 << 1)
101 #define MCI_DMADES1_BS1(x) (x)
102 #define MCI_DMADES1_BS2(x) ((x) << 13)
103 #define MCI_DMADES1_MAXTR 4096
107 #define MCI_CTRL_USE_INT_DMAC (1 << 25)
108 #define MCI_CTRL_CARDV_MASK (0x7 << 16)
109 #define MCI_CTRL_CEATA_INT_EN (1 << 11)
110 #define MCI_CTRL_SEND_AS_CCSD (1 << 10)
111 #define MCI_CTRL_SEND_CCSD (1 << 9)
112 #define MCI_CTRL_ABRT_READ_DATA (1 << 8)
113 #define MCI_CTRL_SEND_IRQ_RESP (1 << 7)
114 #define MCI_CTRL_READ_WAIT (1 << 6)
115 #define MCI_CTRL_INT_ENABLE (1 << 4)
116 #define MCI_CTRL_DMA_RESET (1 << 2)
117 #define MCI_CTRL_FIFO_RESET (1 << 1)
118 #define MCI_CTRL_RESET (1 << 0)
122 #define MCI_POWER_ENABLE 0x1
126 #define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8))
130 #define MCI_CLKSRC_CLKDIV0 0
131 #define MCI_CLKSRC_CLKDIV1 1
132 #define MCI_CLKSRC_CLKDIV2 2
133 #define MCI_CLKSRC_CLKDIV3 3
134 #define MCI_CLK_SOURCE(clksrc) (clksrc)
138 #define MCI_CLKEN_LOW_PWR (1 << 16)
139 #define MCI_CLKEN_ENABLE (1 << 0)
143 #define MCI_TMOUT_DATA(clks) ((clks) << 8)
144 #define MCI_TMOUT_DATA_MSK 0xFFFFFF00
145 #define MCI_TMOUT_RESP(clks) ((clks) & 0xFF)
146 #define MCI_TMOUT_RESP_MSK 0xFF
147
150 #define MCI_CTYPE_8BIT (1 << 16)
151 #define MCI_CTYPE_4BIT (1 << 0)
155 #define MCI_INT_SDIO (1 << 16)
156 #define MCI_INT_EBE (1 << 15)
157 #define MCI_INT_ACD (1 << 14)
158 #define MCI_INT_SBE (1 << 13)
159 #define MCI_INT_HLE (1 << 12)
160 #define MCI_INT_FRUN (1 << 11)
161 #define MCI_INT_HTO (1 << 10)
162 #define MCI_INT_DTO (1 << 9)
163 #define MCI_INT_RTO (1 << 8)
164 #define MCI_INT_DCRC (1 << 7)
165 #define MCI_INT_RCRC (1 << 6)
166 #define MCI_INT_RXDR (1 << 5)
167 #define MCI_INT_TXDR (1 << 4)
168 #define MCI_INT_DATA_OVER (1 << 3)
169 #define MCI_INT_CMD_DONE (1 << 2)
170 #define MCI_INT_RESP_ERR (1 << 1)
171 #define MCI_INT_CD (1 << 0)
175 #define MCI_CMD_START (1UL << 31)
176 #define MCI_CMD_VOLT_SWITCH (1 << 28)
177 #define MCI_CMD_BOOT_MODE (1 << 27)
178 #define MCI_CMD_DISABLE_BOOT (1 << 26)
179 #define MCI_CMD_EXPECT_BOOT_ACK (1 << 25)
180 #define MCI_CMD_ENABLE_BOOT (1 << 24)
181 #define MCI_CMD_CCS_EXP (1 << 23)
182 #define MCI_CMD_CEATA_RD (1 << 22)
183 #define MCI_CMD_UPD_CLK (1 << 21)
184 #define MCI_CMD_INIT (1 << 15)
185 #define MCI_CMD_STOP (1 << 14)
186 #define MCI_CMD_PRV_DAT_WAIT (1 << 13)
187 #define MCI_CMD_SEND_STOP (1 << 12)
188 #define MCI_CMD_STRM_MODE (1 << 11)
189 #define MCI_CMD_DAT_WR (1 << 10)
190 #define MCI_CMD_DAT_EXP (1 << 9)
191 #define MCI_CMD_RESP_CRC (1 << 8)
192 #define MCI_CMD_RESP_LONG (1 << 7)
193 #define MCI_CMD_RESP_EXP (1 << 6)
194 #define MCI_CMD_INDX(n) ((n) & 0x1F)
195
198 #define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
199
202 #define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
203 #define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
204 #define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
205 #define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
206 #define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
207 #define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
208 #define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
209 #define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
210 #define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
211 #define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
212
215 #define MCI_BMOD_PBL1 (0 << 8)
216 #define MCI_BMOD_PBL4 (1 << 8)
217 #define MCI_BMOD_PBL8 (2 << 8)
218 #define MCI_BMOD_PBL16 (3 << 8)
219 #define MCI_BMOD_PBL32 (4 << 8)
220 #define MCI_BMOD_PBL64 (5 << 8)
221 #define MCI_BMOD_PBL128 (6 << 8)
222 #define MCI_BMOD_PBL256 (7 << 8)
223 #define MCI_BMOD_DE (1 << 7)
224 #define MCI_BMOD_DSL(len) ((len) << 2)
225 #define MCI_BMOD_FB (1 << 1)
226 #define MCI_BMOD_SWR (1 << 0)
230 #define SD_FIFO_SZ 32
233 typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
234
236 typedef int32_t (*PSCHECK_FUNC_T)(void);
237
239 typedef void (*PS_POWER_FUNC_T)(int32_t enable);
240
243 typedef struct {
244 volatile uint32_t des0;
245 volatile uint32_t des1;
246 volatile uint32_t des2;
247 volatile uint32_t des3;
248 } pSDMMC_DMA_T;
249
252 typedef struct _sdif_device {
253 /* MCI_IRQ_CB_FUNC_T irq_cb; */
254 pSDMMC_DMA_T mci_dma_dd[1 + (0x10000 / MCI_DMADES1_MAXTR)];
255 /* uint32_t sdio_clk_rate; */
256 /* uint32_t sdif_slot_clk_rate; */
257 /* int32_t clock_enabled; */
258 } sdif_device;
259
262 #define US_TIMEOUT 1000000
263 #define MS_ACQUIRE_DELAY (10)
264 #define INIT_OP_RETRIES 50
265 #define SET_OP_RETRIES 1000
266 #define SDIO_BUS_WIDTH 4
267 #define SD_MMC_ENUM_CLOCK 400000
268 #define MMC_MAX_CLOCK 20000000
269 #define MMC_LOW_BUS_MAX_CLOCK 26000000
270 #define MMC_HIGH_BUS_MAX_CLOCK 52000000
271 #define SD_MAX_CLOCK 25000000
279 STATIC INLINE void Chip_SDIF_SetBlkSize(LPC_SDMMC_T *pSDMMC, uint32_t bytes)
280 {
281 pSDMMC->BLKSIZ = bytes;
282 }
283
292 STATIC INLINE void Chip_SDIF_Reset(LPC_SDMMC_T *pSDMMC, int32_t reset)
293 {
294 if (reset) {
295 pSDMMC->RST_N = 1;
296 }
297 else {
298 pSDMMC->RST_N = 0;
299 }
300 }
301
309 STATIC INLINE int32_t Chip_SDIF_CardNDetect(LPC_SDMMC_T *pSDMMC)
310 {
311 return (pSDMMC->CDETECT & 1);
312 }
313
321 STATIC INLINE int32_t Chip_SDIF_CardWpOn(LPC_SDMMC_T *pSDMMC)
322 {
323 return (pSDMMC->WRTPRT & 1);
324 }
325
332 STATIC INLINE void Chip_SDIF_PowerOff(LPC_SDMMC_T *pSDMMC)
333 {
334 pSDMMC->PWREN = 0;
335 }
336
343 STATIC INLINE void Chip_SDIF_PowerOn(LPC_SDMMC_T *pSDMMC)
344 {
345 pSDMMC->PWREN = 1;
346 }
347
354 STATIC INLINE void Chip_SDIF_SetCardType(LPC_SDMMC_T *pSDMMC, uint32_t ctype)
355 {
356 pSDMMC->CTYPE = ctype;
357 }
358
364 STATIC INLINE uint32_t Chip_SDIF_GetIntStatus(LPC_SDMMC_T *pSDMMC)
365 {
366 return pSDMMC->RINTSTS;
367 }
368
375 STATIC INLINE void Chip_SDIF_ClrIntStatus(LPC_SDMMC_T *pSDMMC, uint32_t iVal)
376 {
377 pSDMMC->RINTSTS = iVal;
378 }
379
386 STATIC INLINE void Chip_SDIF_SetIntMask(LPC_SDMMC_T *pSDMMC, uint32_t iVal)
387 {
388 pSDMMC->INTMASK = iVal;
389 }
390
397 STATIC INLINE void Chip_SDIF_SetBlkSizeByteCnt(LPC_SDMMC_T *pSDMMC, uint32_t blk_size)
398 {
399 pSDMMC->BLKSIZ = blk_size;
400 pSDMMC->BYTCNT = blk_size;
401 }
402
409 STATIC INLINE void Chip_SDIF_SetByteCnt(LPC_SDMMC_T *pSDMMC, uint32_t bytes)
410 {
411 pSDMMC->BYTCNT = bytes;
412 }
413
419 void Chip_SDIF_Init(LPC_SDMMC_T *pSDMMC);
420
426 void Chip_SDIF_DeInit(LPC_SDMMC_T *pSDMMC);
427
435 int32_t Chip_SDIF_SendCmd(LPC_SDMMC_T *pSDMMC, uint32_t cmd, uint32_t arg);
436
443 void Chip_SDIF_GetResponse(LPC_SDMMC_T *pSDMMC, uint32_t *resp);
444
452 void Chip_SDIF_SetClock(LPC_SDMMC_T *pSDMMC, uint32_t clk_rate, uint32_t speed);
453
459 void Chip_SDIF_SetClearIntFifo(LPC_SDMMC_T *pSDMMC);
460
469 void Chip_SDIF_DmaSetup(LPC_SDMMC_T *pSDMMC, sdif_device *psdif_dev, uint32_t addr, uint32_t size);
470
475 #ifdef __cplusplus
476 }
477 #endif
478
479 #endif /* __SDIF_18XX_43XX_H_ */