LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
gpiogroup_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx GPIO group driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2013
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __GPIOGROUP_18XX_43XX_H_
33 #define __GPIOGROUP_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef struct {
48  __IO uint32_t CTRL;
49  __I uint32_t RESERVED0[7];
50  __IO uint32_t PORT_POL[8];
51  __IO uint32_t PORT_ENA[8];
52  uint32_t RESERVED1[1000];
54 
58 #define GPIOGR_INT (1 << 0)
59 #define GPIOGR_COMB (1 << 1)
60 #define GPIOGR_TRIG (1 << 2)
68 STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
69 {
70  uint32_t temp;
71 
72  temp = pGPIOGPINT[group].CTRL;
73  pGPIOGPINT[group].CTRL = temp | GPIOGR_INT;
74 }
75 
82 STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
83 {
84  return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0);
85 }
86 
93 STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
94 {
95  pGPIOGPINT[group].CTRL &= ~GPIOGR_COMB;
96 }
97 
105 {
106  pGPIOGPINT[group].CTRL |= GPIOGR_COMB;
107 }
108 
116 {
117  pGPIOGPINT[group].CTRL &= ~GPIOGR_TRIG;
118 }
119 
127 {
128  pGPIOGPINT[group].CTRL |= GPIOGR_TRIG;
129 }
130 
140  uint8_t group,
141  uint8_t port,
142  uint32_t pinMask)
143 {
144  pGPIOGPINT[group].PORT_POL[port] &= ~pinMask;
145 }
146 
156  uint8_t group,
157  uint8_t port,
158  uint32_t pinMask)
159 {
160  pGPIOGPINT[group].PORT_POL[port] |= pinMask;
161 }
162 
173  uint8_t group,
174  uint8_t port,
175  uint32_t pinMask)
176 {
177  pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask;
178 }
179 
190  uint8_t group,
191  uint8_t port,
192  uint32_t pinMask)
193 {
194  pGPIOGPINT[group].PORT_ENA[port] |= pinMask;
195 }
196 
201 #ifdef __cplusplus
202 }
203 #endif
204 
205 #endif /* __GPIOGROUP_18XX_43XX_H_ */