Peripheral clocks Peripheral clocks are individual clocks routed to peripherals. Although multiple peripherals may share a same base clock, each peripheral's clock can be enabled or disabled individually. Some peripheral clocks also have additional dividers associated with them.
| Enumerator |
|---|
| CLK_APB3_BUS |
APB3 bus clock from base clock CLK_BASE_APB3
|
| CLK_APB3_I2C1 |
I2C1 register/perigheral clock from base clock CLK_BASE_APB3
|
| CLK_APB3_DAC |
DAC peripheral clock from base clock CLK_BASE_APB3
|
| CLK_APB3_ADC0 |
ADC0 register/perigheral clock from base clock CLK_BASE_APB3
|
| CLK_APB3_ADC1 |
ADC1 register/perigheral clock from base clock CLK_BASE_APB3
|
| CLK_APB3_CAN0 |
CAN0 register/perigheral clock from base clock CLK_BASE_APB3
|
| CLK_APB1_BUS |
APB1 bus clock clock from base clock CLK_BASE_APB1
|
| CLK_APB1_MOTOCON |
Motor controller register/perigheral clock from base clock CLK_BASE_APB1
|
| CLK_APB1_I2C0 |
I2C0 register/perigheral clock from base clock CLK_BASE_APB1
|
| CLK_APB1_I2S |
I2S register/perigheral clock from base clock CLK_BASE_APB1
|
| CLK_APB1_CAN1 |
CAN1 register/perigheral clock from base clock CLK_BASE_APB1
|
| CLK_SPIFI |
SPIFI SCKI input clock from base clock CLK_BASE_SPIFI
|
| CLK_MX_BUS |
M3/M4 BUS core clock from base clock CLK_BASE_MX
|
| CLK_MX_SPIFI |
SPIFI register clock from base clock CLK_BASE_MX
|
| CLK_MX_GPIO |
GPIO register clock from base clock CLK_BASE_MX
|
| CLK_MX_LCD |
LCD register clock from base clock CLK_BASE_MX
|
| CLK_MX_ETHERNET |
ETHERNET register clock from base clock CLK_BASE_MX
|
| CLK_MX_USB0 |
USB0 register clock from base clock CLK_BASE_MX
|
| CLK_MX_EMC |
EMC clock from base clock CLK_BASE_MX
|
| CLK_MX_SDIO |
SDIO register clock from base clock CLK_BASE_MX
|
| CLK_MX_DMA |
DMA register clock from base clock CLK_BASE_MX
|
| CLK_MX_MXCORE |
M3/M4 CPU core clock from base clock CLK_BASE_MX
|
| RESERVED_ALIGN |
|
| CLK_MX_SCT |
SCT register clock from base clock CLK_BASE_MX
|
| CLK_MX_USB1 |
USB1 register clock from base clock CLK_BASE_MX
|
| CLK_MX_EMC_DIV |
ENC divider clock from base clock CLK_BASE_MX
|
| CLK_MX_FLASHA |
FLASHA bank clock from base clock CLK_BASE_MX
|
| CLK_MX_FLASHB |
FLASHB bank clock from base clock CLK_BASE_MX
|
| CLK_RESERVED1 |
|
| CLK_RESERVED2 |
|
| CLK_MX_EEPROM |
EEPROM clock from base clock CLK_BASE_MX
|
| CLK_MX_WWDT |
WWDT register clock from base clock CLK_BASE_MX
|
| CLK_MX_UART0 |
UART0 register clock from base clock CLK_BASE_MX
|
| CLK_MX_UART1 |
UART1 register clock from base clock CLK_BASE_MX
|
| CLK_MX_SSP0 |
SSP0 register clock from base clock CLK_BASE_MX
|
| CLK_MX_TIMER0 |
TIMER0 register/perigheral clock from base clock CLK_BASE_MX
|
| CLK_MX_TIMER1 |
TIMER1 register/perigheral clock from base clock CLK_BASE_MX
|
| CLK_MX_SCU |
SCU register/perigheral clock from base clock CLK_BASE_MX
|
| CLK_MX_CREG |
CREG clock from base clock CLK_BASE_MX
|
| CLK_MX_RITIMER |
RITIMER register/perigheral clock from base clock CLK_BASE_MX
|
| CLK_MX_UART2 |
UART3 register clock from base clock CLK_BASE_MX
|
| CLK_MX_UART3 |
UART4 register clock from base clock CLK_BASE_MX
|
| CLK_MX_TIMER2 |
TIMER2 register/perigheral clock from base clock CLK_BASE_MX
|
| CLK_MX_TIMER3 |
TIMER3 register/perigheral clock from base clock CLK_BASE_MX
|
| CLK_MX_SSP1 |
SSP1 register clock from base clock CLK_BASE_MX
|
| CLK_MX_QEI |
QEI register/perigheral clock from base clock CLK_BASE_MX
|
| CLK_RESERVED3 |
|
| CLK_RESERVED3A |
|
| CLK_RESERVED4 |
|
| CLK_RESERVED5 |
|
| CLK_USB0 |
USB0 clock from base clock CLK_BASE_USB0
|
| CLK_USB1 |
USB1 clock from base clock CLK_BASE_USB1
|
| CLK_RESERVED7 |
|
| CLK_RESERVED8 |
|
| CLK_CCU1_LAST |
|
| CLK_CCU2_START |
|
| CLK_APLL |
Audio PLL clock from base clock CLK_BASE_APLL
|
| RESERVED_ALIGNB |
|
| CLK_APB2_UART3 |
UART3 clock from base clock CLK_BASE_UART3
|
| RESERVED_ALIGNC |
|
| CLK_APB2_UART2 |
UART2 clock from base clock CLK_BASE_UART2
|
| RESERVED_ALIGND |
|
| CLK_APB0_UART1 |
UART1 clock from base clock CLK_BASE_UART1
|
| RESERVED_ALIGNE |
|
| CLK_APB0_UART0 |
UART0 clock from base clock CLK_BASE_UART0
|
| RESERVED_ALIGNF |
|
| CLK_APB2_SSP1 |
SSP1 clock from base clock CLK_BASE_SSP1
|
| RESERVED_ALIGNG |
|
| CLK_APB0_SSP0 |
SSP0 clock from base clock CLK_BASE_SSP0
|
| RESERVED_ALIGNH |
|
| CLK_APB2_SDIO |
SDIO clock from base clock CLK_BASE_SDIO
|
| CLK_CCU2_LAST |
|