LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
Data Structures | Macros | Functions
CHIP: LPC18xx/43xx Ethernet driver

Detailed Description

Data Structures

struct  LPC_ENET_T
 10/100 MII & RMII Ethernet with timestamping register block structure More...
 
struct  ENET_TXDESC_T
 Structure of a transmit descriptor (without timestamp) More...
 
struct  ENET_ENHTXDESC_T
 Structure of a enhanced transmit descriptor (with timestamp) More...
 
struct  ENET_RXDESC_T
 Structure of a receive descriptor (without timestamp) More...
 
struct  ENET_ENHRXDESC_T
 Structure of a enhanced receive descriptor (with timestamp) More...
 

Macros

#define MAC_CFG_RE   (1 << 2)
 
#define MAC_CFG_TE   (1 << 3)
 
#define MAC_CFG_DF   (1 << 4)
 
#define MAC_CFG_BL(n)   ((n) << 5)
 
#define MAC_CFG_ACS   (1 << 7)
 
#define MAC_CFG_LUD   (1 << 8)
 
#define MAC_CFG_DR   (1 << 9)
 
#define MAC_CFG_IPC   (1 << 10)
 
#define MAC_CFG_DM   (1 << 11)
 
#define MAC_CFG_LM   (1 << 12)
 
#define MAC_CFG_DO   (1 << 13)
 
#define MAC_CFG_FES   (1 << 14)
 
#define MAC_CFG_PS   (1 << 15)
 
#define MAC_CFG_DCRS   (1 << 16)
 
#define MAC_CFG_IFG(n)   ((n) << 17)
 
#define MAC_CFG_JE   (1 << 20)
 
#define MAC_CFG_JD   (1 << 22)
 
#define MAC_CFG_WD   (1 << 23)
 
#define MAC_FF_PR   (1 << 0)
 
#define MAC_FF_DAIF   (1 << 3)
 
#define MAC_FF_PM   (1 << 4)
 
#define MAC_FF_DBF   (1 << 5)
 
#define MAC_FF_PCF(n)   ((n) << 6)
 
#define MAC_FF_SAIF   (1 << 8)
 
#define MAC_FF_SAF   (1 << 9)
 
#define MAC_FF_RA   (1UL << 31)
 
#define MAC_MIIA_GB   (1 << 0)
 
#define MAC_MIIA_W   (1 << 1)
 
#define MAC_MIIA_CR(n)   ((n) << 2)
 
#define MAC_MIIA_GR(n)   ((n) << 6)
 
#define MAC_MIIA_PA(n)   ((n) << 11)
 
#define MAC_MIID_GDMSK   (0xFFFF)
 
#define MAC_FC_FCB   (1 << 0)
 MAC_FLOW_CONTROL register bit defines. More...
 
#define MAC_FC_TFE   (1 << 1)
 
#define MAC_FC_RFE   (1 << 2)
 
#define MAC_FC_UP   (1 << 3)
 
#define MAC_FC_PLT(n)   ((n) << 4)
 
#define MAC_FC_DZPQ   (1 << 7)
 
#define MAC_FC_PT(n)   ((n) << 16)
 
#define MAC_VT_VL(n)   ((n) << 0)
 
#define MAC_VT_ETC   (1 << 7)
 
#define MAC_PMT_PD   (1 << 0)
 
#define MAC_PMT_MPE   (1 << 1)
 
#define MAC_PMT_WFE   (1 << 2)
 
#define MAC_PMT_MPR   (1 << 5)
 
#define MAC_PMT_WFR   (1 << 6)
 
#define MAC_PMT_GU   (1 << 9)
 
#define MAC_PMT_WFFRPR   (1UL << 31)
 
#define MAC_IM_PMT   (1 << 3)
 
#define MAC_ADRH_MO   (1UL << 31)
 
#define MAC_ADRH_MO   (1UL << 31)
 
#define MAC_TS_TSENA   (1 << 0)
 
#define MAC_TS_TSCFUP   (1 << 1)
 
#define MAC_TS_TSINIT   (1 << 2)
 
#define MAC_TS_TSUPDT   (1 << 3)
 
#define MAC_TS_TSTRIG   (1 << 4)
 
#define MAC_TS_TSADDR   (1 << 5)
 
#define MAC_TS_TSENAL   (1 << 8)
 
#define MAC_TS_TSCTRL   (1 << 9)
 
#define MAC_TS_TSVER2   (1 << 10)
 
#define MAC_TS_TSIPENA   (1 << 11)
 
#define MAC_TS_TSIPV6E   (1 << 12)
 
#define MAC_TS_TSIPV4E   (1 << 13)
 
#define MAC_TS_TSEVNT   (1 << 14)
 
#define MAC_TS_TSMSTR   (1 << 15)
 
#define MAC_TS_TSCLKT(n)   ((n) << 16)
 
#define MAC_TS_TSENMA   (1 << 18)
 
#define DMA_BM_SWR   (1 << 0)
 
#define DMA_BM_DA   (1 << 1)
 
#define DMA_BM_DSL(n)   ((n) << 2)
 
#define DMA_BM_ATDS   (1 << 7)
 
#define DMA_BM_PBL(n)   ((n) << 8)
 
#define DMA_BM_PR(n)   ((n) << 14)
 
#define DMA_BM_FB   (1 << 16)
 
#define DMA_BM_RPBL(n)   ((n) << 17)
 
#define DMA_BM_USP   (1 << 23)
 
#define DMA_BM_PBL8X   (1 << 24)
 
#define DMA_BM_AAL   (1 << 25)
 
#define DMA_BM_MB   (1 << 26)
 
#define DMA_BM_TXPR   (1 << 27)
 
#define DMA_ST_TI   (1 << 0)
 
#define DMA_ST_TPS   (1 << 1)
 
#define DMA_ST_TU   (1 << 2)
 
#define DMA_ST_TJT   (1 << 3)
 
#define DMA_ST_OVF   (1 << 4)
 
#define DMA_ST_UNF   (1 << 5)
 
#define DMA_ST_RI   (1 << 6)
 
#define DMA_ST_RU   (1 << 7)
 
#define DMA_ST_RPS   (1 << 8)
 
#define DMA_ST_RWT   (1 << 9)
 
#define DMA_ST_ETI   (1 << 10)
 
#define DMA_ST_FBI   (1 << 13)
 
#define DMA_ST_ERI   (1 << 14)
 
#define DMA_ST_AIE   (1 << 15)
 
#define DMA_ST_NIS   (1 << 16)
 
#define DMA_ST_ALL   (0x1E7FF)
 
#define DMA_OM_SR   (1 << 1)
 
#define DMA_OM_OSF   (1 << 2)
 
#define DMA_OM_RTC(n)   ((n) << 3)
 
#define DMA_OM_FUF   (1 << 6)
 
#define DMA_OM_FEF   (1 << 7)
 
#define DMA_OM_ST   (1 << 13)
 
#define DMA_OM_TTC(n)   ((n) << 14)
 
#define DMA_OM_FTF   (1 << 20)
 
#define DMA_OM_TSF   (1 << 21)
 
#define DMA_OM_DFF   (1 << 24)
 
#define DMA_OM_RSF   (1 << 25)
 
#define DMA_OM_DT   (1 << 26)
 
#define DMA_IE_TIE   (1 << 0)
 
#define DMA_IE_TSE   (1 << 1)
 
#define DMA_IE_TUE   (1 << 2)
 
#define DMA_IE_TJE   (1 << 3)
 
#define DMA_IE_OVE   (1 << 4)
 
#define DMA_IE_UNE   (1 << 5)
 
#define DMA_IE_RIE   (1 << 6)
 
#define DMA_IE_RUE   (1 << 7)
 
#define DMA_IE_RSE   (1 << 8)
 
#define DMA_IE_RWE   (1 << 9)
 
#define DMA_IE_ETE   (1 << 10)
 
#define DMA_IE_FBE   (1 << 13)
 
#define DMA_IE_ERE   (1 << 14)
 
#define DMA_IE_AIE   (1 << 15)
 
#define DMA_IE_NIE   (1 << 16)
 
#define DMA_MFRM_FMCMSK   (0xFFFF)
 
#define DMA_MFRM_OC   (1 << 16)
 
#define DMA_MFRM_FMA(n)   (((n) & 0x0FFE0000) >> 17)
 
#define DMA_MFRM_OF   (1 << 28)
 
#define TDES_DB   (1 << 0)
 
#define TDES_UF   (1 << 1)
 
#define TDES_ED   (1 << 2)
 
#define TDES_CCMSK(n)   (((n) & 0x000000F0) >> 3)
 
#define TDES_VF   (1 << 7)
 
#define TDES_EC   (1 << 8)
 
#define TDES_LC   (1 << 9)
 
#define TDES_NC   (1 << 10)
 
#define TDES_LCAR   (1 << 11)
 
#define TDES_IPE   (1 << 12)
 
#define TDES_FF   (1 << 13)
 
#define TDES_JT   (1 << 14)
 
#define TDES_ES   (1 << 15)
 
#define TDES_IHE   (1 << 16)
 
#define TDES_TTSS   (1 << 17)
 
#define TDES_OWN   (1UL << 31)
 
#define TDES_ENH_IC   (1UL << 30)
 
#define TDES_ENH_LS   (1 << 29)
 
#define TDES_ENH_FS   (1 << 28)
 
#define TDES_ENH_DC   (1 << 27)
 
#define TDES_ENH_DP   (1 << 26)
 
#define TDES_ENH_TTSE   (1 << 25)
 
#define TDES_ENH_CIC(n)   ((n) << 22)
 
#define TDES_ENH_TER   (1 << 21)
 
#define TDES_ENH_TCH   (1 << 20)
 
#define TDES_NORM_IC   (1UL << 31)
 
#define TDES_NORM_FS   (1 << 30)
 
#define TDES_NORM_LS   (1 << 29)
 
#define TDES_NORM_CIC(n)   ((n) << 27)
 
#define TDES_NORM_DC   (1 << 26)
 
#define TDES_NORM_TER   (1 << 25)
 
#define TDES_NORM_TCH   (1 << 24)
 
#define TDES_NORM_DP   (1 << 23)
 
#define TDES_NORM_TTSE   (1 << 22)
 
#define TDES_NORM_BS2(n)   (((n) & 0x3FF) << 11)
 
#define TDES_NORM_BS1(n)   (((n) & 0x3FF) << 0)
 
#define TDES_ENH_BS2(n)   (((n) & 0xFFF) << 16)
 
#define TDES_ENH_BS1(n)   (((n) & 0xFFF) << 0)
 
#define RDES_ESA   (1 << 0)
 
#define RDES_CE   (1 << 1)
 
#define RDES_DRE   (1 << 2)
 
#define RDES_RE   (1 << 3)
 
#define RDES_RWT   (1 << 4)
 
#define RDES_FT   (1 << 5)
 
#define RDES_LC   (1 << 6)
 
#define RDES_TSA   (1 << 7)
 
#define RDES_LS   (1 << 8)
 
#define RDES_FS   (1 << 9)
 
#define RDES_VLAN   (1 << 10)
 
#define RDES_OE   (1 << 11)
 
#define RDES_LE   (1 << 12)
 
#define RDES_SAF   (1 << 13)
 
#define RDES_DE   (1 << 14)
 
#define RDES_ES   (1 << 15)
 
#define RDES_FLMSK(n)   (((n) & 0x3FFF0000) >> 16)
 
#define RDES_AFM   (1 << 30)
 
#define RDES_OWN   (1UL << 31)
 
#define RDES_DINT   (1UL << 31)
 
#define RDES_NORM_RER   (1 << 25)
 
#define RDES_NORM_RCH   (1 << 24)
 
#define RDES_NORM_BS2(n)   (((n) & 0x3FF) << 11)
 
#define RDES_NORM_BS1(n)   (((n) & 0x3FF) << 0)
 
#define RDES_ENH_RER   (1 << 15)
 REC_DESC_ENH_T only CTRL field bit defines. More...
 
#define RDES_ENH_RCH   (1 << 14)
 
#define RDES_ENH_BS2(n)   (((n) & 0xFFF) << 16)
 
#define RDES_ENH_BS1(n)   (((n) & 0xFFF) << 0)
 
#define RDES_ENH_IPPL(n)   (((n) & 0x7) >> 2)
 
#define RDES_ENH_IPHE   (1 << 3)
 
#define RDES_ENH_IPPLE   (1 << 4)
 
#define RDES_ENH_IPCSB   (1 << 5)
 
#define RDES_ENH_IPV4   (1 << 6)
 
#define RDES_ENH_IPV6   (1 << 7)
 
#define RDES_ENH_MTMSK(n)   (((n) & 0xF) >> 8)
 
#define EMAC_ETH_MAX_FLEN   (1536)
 

Functions

STATIC INLINE void Chip_ENET_Reset (LPC_ENET_T *pENET)
 Resets the ethernet interface. More...
 
STATIC INLINE void Chip_ENET_SetADDR (LPC_ENET_T *pENET, const uint8_t *macAddr)
 Sets the address of the interface. More...
 
void Chip_ENET_SetupMII (LPC_ENET_T *pENET, uint32_t div, uint8_t addr)
 Sets up the PHY link clock divider and PHY address. More...
 
void Chip_ENET_StartMIIWrite (LPC_ENET_T *pENET, uint8_t reg, uint16_t data)
 Starts a PHY write via the MII. More...
 
void Chip_ENET_StartMIIRead (LPC_ENET_T *pENET, uint8_t reg)
 Starts a PHY read via the MII. More...
 
STATIC INLINE bool Chip_ENET_IsMIIBusy (LPC_ENET_T *pENET)
 Returns MII link (PHY) busy status. More...
 
STATIC INLINE uint16_t Chip_ENET_ReadMIIData (LPC_ENET_T *pENET)
 Returns the value read from the PHY. More...
 
STATIC INLINE void Chip_ENET_TXEnable (LPC_ENET_T *pENET)
 Enables ethernet transmit. More...
 
STATIC INLINE void Chip_ENET_TXDisable (LPC_ENET_T *pENET)
 Disables ethernet transmit. More...
 
STATIC INLINE void Chip_ENET_RXEnable (LPC_ENET_T *pENET)
 Enables ethernet packet reception. More...
 
STATIC INLINE void Chip_ENET_RXDisable (LPC_ENET_T *pENET)
 Disables ethernet packet reception. More...
 
STATIC INLINE void Chip_ENET_RMIIEnable (LPC_ENET_T *pENET)
 Enable RMII ethernet operation. More...
 
STATIC INLINE void Chip_ENET_MIIEnable (LPC_ENET_T *pENET)
 Enable MII ethernet operation. More...
 
void Chip_ENET_SetDuplex (LPC_ENET_T *pENET, bool full)
 Sets full or half duplex for the interface. More...
 
void Chip_ENET_SetSpeed (LPC_ENET_T *pENET, bool speed100)
 Sets speed for the interface. More...
 
STATIC INLINE void Chip_ENET_InitDescriptors (LPC_ENET_T *pENET, ENET_ENHTXDESC_T *pTXDescs, ENET_ENHRXDESC_T *pRXDescs)
 Configures the initial ethernet descriptors. More...
 
STATIC INLINE void Chip_ENET_RXStart (LPC_ENET_T *pENET)
 Starts receive polling of RX descriptors. More...
 
STATIC INLINE void Chip_ENET_TXStart (LPC_ENET_T *pENET)
 Starts transmit polling of TX descriptors. More...
 
void Chip_ENET_Init (LPC_ENET_T *pENET, uint32_t phyAddr)
 Initialize ethernet interface. More...
 
void Chip_ENET_DeInit (LPC_ENET_T *pENET)
 De-initialize the ethernet interface. More...
 

Macro Definition Documentation

#define DMA_BM_AAL   (1 << 25)

Address-aligned beats

Definition at line 222 of file enet_18xx_43xx.h.

#define DMA_BM_ATDS   (1 << 7)

Alternate (Enhanced) descriptor size

Definition at line 215 of file enet_18xx_43xx.h.

#define DMA_BM_DA   (1 << 1)

DMA arbitration scheme, 1 = TX has priority over TX

Definition at line 213 of file enet_18xx_43xx.h.

#define DMA_BM_DSL (   n)    ((n) << 2)

Descriptor skip length, n = see manual

Definition at line 214 of file enet_18xx_43xx.h.

#define DMA_BM_FB   (1 << 16)

Fixed burst

Definition at line 218 of file enet_18xx_43xx.h.

#define DMA_BM_MB   (1 << 26)

Mixed burst

Definition at line 223 of file enet_18xx_43xx.h.

#define DMA_BM_PBL (   n)    ((n) << 8)

Programmable burst length, n = see manual

Definition at line 216 of file enet_18xx_43xx.h.

#define DMA_BM_PBL8X   (1 << 24)

8 x PBL mode

Definition at line 221 of file enet_18xx_43xx.h.

#define DMA_BM_PR (   n)    ((n) << 14)

Rx-to-Tx priority ratio, n = see manual

Definition at line 217 of file enet_18xx_43xx.h.

#define DMA_BM_RPBL (   n)    ((n) << 17)

RxDMA PBL, n = see manual

Definition at line 219 of file enet_18xx_43xx.h.

#define DMA_BM_SWR   (1 << 0)

Software reset

Definition at line 212 of file enet_18xx_43xx.h.

#define DMA_BM_TXPR   (1 << 27)

Transmit DMA has higher priority than receive DMA

Definition at line 224 of file enet_18xx_43xx.h.

#define DMA_BM_USP   (1 << 23)

Use separate PBL

Definition at line 220 of file enet_18xx_43xx.h.

#define DMA_IE_AIE   (1 << 15)

Abnormal interrupt summary enable

Definition at line 278 of file enet_18xx_43xx.h.

#define DMA_IE_ERE   (1 << 14)

Early receive interrupt enable

Definition at line 277 of file enet_18xx_43xx.h.

#define DMA_IE_ETE   (1 << 10)

Early transmit interrupt enable

Definition at line 275 of file enet_18xx_43xx.h.

#define DMA_IE_FBE   (1 << 13)

Fatal bus error enable

Definition at line 276 of file enet_18xx_43xx.h.

#define DMA_IE_NIE   (1 << 16)

Normal interrupt summary enable

Definition at line 279 of file enet_18xx_43xx.h.

#define DMA_IE_OVE   (1 << 4)

Overflow interrupt enable

Definition at line 269 of file enet_18xx_43xx.h.

#define DMA_IE_RIE   (1 << 6)

Receive interrupt enable

Definition at line 271 of file enet_18xx_43xx.h.

#define DMA_IE_RSE   (1 << 8)

Received stopped enable

Definition at line 273 of file enet_18xx_43xx.h.

#define DMA_IE_RUE   (1 << 7)

Receive buffer unavailable enable

Definition at line 272 of file enet_18xx_43xx.h.

#define DMA_IE_RWE   (1 << 9)

Receive watchdog timeout enable

Definition at line 274 of file enet_18xx_43xx.h.

#define DMA_IE_TIE   (1 << 0)

Transmit interrupt enable

Definition at line 265 of file enet_18xx_43xx.h.

#define DMA_IE_TJE   (1 << 3)

Transmit jabber timeout enable

Definition at line 268 of file enet_18xx_43xx.h.

#define DMA_IE_TSE   (1 << 1)

Transmit stopped enable

Definition at line 266 of file enet_18xx_43xx.h.

#define DMA_IE_TUE   (1 << 2)

Transmit buffer unavailable enable

Definition at line 267 of file enet_18xx_43xx.h.

#define DMA_IE_UNE   (1 << 5)

Underflow interrupt enable

Definition at line 270 of file enet_18xx_43xx.h.

#define DMA_MFRM_FMA (   n)    (((n) & 0x0FFE0000) >> 17)

Number of frames missed by the application mask/shift

Definition at line 286 of file enet_18xx_43xx.h.

#define DMA_MFRM_FMCMSK   (0xFFFF)

Number of frames missed mask

Definition at line 284 of file enet_18xx_43xx.h.

#define DMA_MFRM_OC   (1 << 16)

Overflow bit for missed frame counter

Definition at line 285 of file enet_18xx_43xx.h.

#define DMA_MFRM_OF   (1 << 28)

Overflow bit for FIFO overflow counter

Definition at line 287 of file enet_18xx_43xx.h.

#define DMA_OM_DFF   (1 << 24)

Disable flushing of received frames

Definition at line 258 of file enet_18xx_43xx.h.

#define DMA_OM_DT   (1 << 26)

Disable Dropping of TCP/IP Checksum Error Frames

Definition at line 260 of file enet_18xx_43xx.h.

#define DMA_OM_FEF   (1 << 7)

Forward error frames

Definition at line 253 of file enet_18xx_43xx.h.

#define DMA_OM_FTF   (1 << 20)

Flush transmit FIFO

Definition at line 256 of file enet_18xx_43xx.h.

#define DMA_OM_FUF   (1 << 6)

Forward undersized good frames

Definition at line 252 of file enet_18xx_43xx.h.

#define DMA_OM_OSF   (1 << 2)

Operate on second frame

Definition at line 250 of file enet_18xx_43xx.h.

#define DMA_OM_RSF   (1 << 25)

Receive store and forward

Definition at line 259 of file enet_18xx_43xx.h.

#define DMA_OM_RTC (   n)    ((n) << 3)

Receive threshold control, n = see manual

Definition at line 251 of file enet_18xx_43xx.h.

#define DMA_OM_SR   (1 << 1)

Start/stop receive

Definition at line 249 of file enet_18xx_43xx.h.

#define DMA_OM_ST   (1 << 13)

Start/Stop Transmission Command

Definition at line 254 of file enet_18xx_43xx.h.

#define DMA_OM_TSF   (1 << 21)

Transmit store and forward

Definition at line 257 of file enet_18xx_43xx.h.

#define DMA_OM_TTC (   n)    ((n) << 14)

Transmit threshold control, n = see manual

Definition at line 255 of file enet_18xx_43xx.h.

#define DMA_ST_AIE   (1 << 15)

Abnormal interrupt summary

Definition at line 242 of file enet_18xx_43xx.h.

#define DMA_ST_ALL   (0x1E7FF)

All interrupts

Definition at line 244 of file enet_18xx_43xx.h.

#define DMA_ST_ERI   (1 << 14)

Early receive interrupt

Definition at line 241 of file enet_18xx_43xx.h.

#define DMA_ST_ETI   (1 << 10)

Early transmit interrupt

Definition at line 239 of file enet_18xx_43xx.h.

#define DMA_ST_FBI   (1 << 13)

Fatal bus error interrupt

Definition at line 240 of file enet_18xx_43xx.h.

#define DMA_ST_NIS   (1 << 16)

Normal interrupt summary

Definition at line 243 of file enet_18xx_43xx.h.

#define DMA_ST_OVF   (1 << 4)

Receive overflow

Definition at line 233 of file enet_18xx_43xx.h.

#define DMA_ST_RI   (1 << 6)

Receive interrupt

Definition at line 235 of file enet_18xx_43xx.h.

#define DMA_ST_RPS   (1 << 8)

Received process stopped

Definition at line 237 of file enet_18xx_43xx.h.

#define DMA_ST_RU   (1 << 7)

Receive buffer unavailable

Definition at line 236 of file enet_18xx_43xx.h.

#define DMA_ST_RWT   (1 << 9)

Receive watchdog timeout

Definition at line 238 of file enet_18xx_43xx.h.

#define DMA_ST_TI   (1 << 0)

Transmit interrupt

Definition at line 229 of file enet_18xx_43xx.h.

#define DMA_ST_TJT   (1 << 3)

Transmit jabber timeout

Definition at line 232 of file enet_18xx_43xx.h.

#define DMA_ST_TPS   (1 << 1)

Transmit process stopped

Definition at line 230 of file enet_18xx_43xx.h.

#define DMA_ST_TU   (1 << 2)

Transmit buffer unavailable

Definition at line 231 of file enet_18xx_43xx.h.

#define DMA_ST_UNF   (1 << 5)

Transmit underflow

Definition at line 234 of file enet_18xx_43xx.h.

#define EMAC_ETH_MAX_FLEN   (1536)

Definition at line 401 of file enet_18xx_43xx.h.

#define MAC_ADRH_MO   (1UL << 31)

Always 1 when writing register

Definition at line 187 of file enet_18xx_43xx.h.

#define MAC_ADRH_MO   (1UL << 31)

Always 1 when writing register

Definition at line 187 of file enet_18xx_43xx.h.

#define MAC_CFG_ACS   (1 << 7)

Automatic Pad/CRC Stripping

Definition at line 105 of file enet_18xx_43xx.h.

#define MAC_CFG_BL (   n)    ((n) << 5)

Back-Off Limit

Definition at line 104 of file enet_18xx_43xx.h.

#define MAC_CFG_DCRS   (1 << 16)

Disable carrier sense during transmission

Definition at line 114 of file enet_18xx_43xx.h.

#define MAC_CFG_DF   (1 << 4)

Deferral Check

Definition at line 103 of file enet_18xx_43xx.h.

#define MAC_CFG_DM   (1 << 11)

Duplex Mode, 1 = full, 0 = half

Definition at line 109 of file enet_18xx_43xx.h.

#define MAC_CFG_DO   (1 << 13)

Disable Receive Own

Definition at line 111 of file enet_18xx_43xx.h.

#define MAC_CFG_DR   (1 << 9)

Disable Retry

Definition at line 107 of file enet_18xx_43xx.h.

#define MAC_CFG_FES   (1 << 14)

Speed, 1 = 100Mbps, 0 = 10Mbos

Definition at line 112 of file enet_18xx_43xx.h.

#define MAC_CFG_IFG (   n)    ((n) << 17)

Inter-frame gap, 40..96, n incs by 8

Definition at line 115 of file enet_18xx_43xx.h.

#define MAC_CFG_IPC   (1 << 10)

Checksum Offload

Definition at line 108 of file enet_18xx_43xx.h.

#define MAC_CFG_JD   (1 << 22)

Jabber Disable

Definition at line 117 of file enet_18xx_43xx.h.

#define MAC_CFG_JE   (1 << 20)

Jumbo Frame Enable

Definition at line 116 of file enet_18xx_43xx.h.

#define MAC_CFG_LM   (1 << 12)

Loopback Mode

Definition at line 110 of file enet_18xx_43xx.h.

#define MAC_CFG_LUD   (1 << 8)

Link Up/Down, 1 = up

Definition at line 106 of file enet_18xx_43xx.h.

#define MAC_CFG_PS   (1 << 15)

Port select, must always be 1

Definition at line 113 of file enet_18xx_43xx.h.

#define MAC_CFG_RE   (1 << 2)

Receiver enable

Definition at line 101 of file enet_18xx_43xx.h.

#define MAC_CFG_TE   (1 << 3)

Transmitter Enable

Definition at line 102 of file enet_18xx_43xx.h.

#define MAC_CFG_WD   (1 << 23)

Watchdog Disable

Definition at line 118 of file enet_18xx_43xx.h.

#define MAC_FC_DZPQ   (1 << 7)

Disable Zero-Quanta Pause

Definition at line 154 of file enet_18xx_43xx.h.

#define MAC_FC_FCB   (1 << 0)

MAC_FLOW_CONTROL register bit defines.

Flow Control Busy/Backpressure Activate

Definition at line 149 of file enet_18xx_43xx.h.

#define MAC_FC_PLT (   n)    ((n) << 4)

Pause Low Threshold, n = see manual

Definition at line 153 of file enet_18xx_43xx.h.

#define MAC_FC_PT (   n)    ((n) << 16)

Pause time

Definition at line 155 of file enet_18xx_43xx.h.

#define MAC_FC_RFE   (1 << 2)

Receive Flow Control Enable

Definition at line 151 of file enet_18xx_43xx.h.

#define MAC_FC_TFE   (1 << 1)

Transmit Flow Control Enable

Definition at line 150 of file enet_18xx_43xx.h.

#define MAC_FC_UP   (1 << 3)

Unicast Pause Frame Detect

Definition at line 152 of file enet_18xx_43xx.h.

#define MAC_FF_DAIF   (1 << 3)

DA Inverse Filtering

Definition at line 124 of file enet_18xx_43xx.h.

#define MAC_FF_DBF   (1 << 5)

Disable Broadcast Frames

Definition at line 126 of file enet_18xx_43xx.h.

#define MAC_FF_PCF (   n)    ((n) << 6)

Pass Control Frames, n = see user manual

Definition at line 127 of file enet_18xx_43xx.h.

#define MAC_FF_PM   (1 << 4)

Pass All Multicast

Definition at line 125 of file enet_18xx_43xx.h.

#define MAC_FF_PR   (1 << 0)

Promiscuous Mode

Definition at line 123 of file enet_18xx_43xx.h.

#define MAC_FF_RA   (1UL << 31)

Receive all

Definition at line 130 of file enet_18xx_43xx.h.

#define MAC_FF_SAF   (1 << 9)

Source Address Filter Enable

Definition at line 129 of file enet_18xx_43xx.h.

#define MAC_FF_SAIF   (1 << 8)

SA Inverse Filtering

Definition at line 128 of file enet_18xx_43xx.h.

#define MAC_IM_PMT   (1 << 3)

PMT Interrupt Mask

Definition at line 177 of file enet_18xx_43xx.h.

#define MAC_MIIA_CR (   n)    ((n) << 2)

CSR clock range, n = see manual

Definition at line 137 of file enet_18xx_43xx.h.

#define MAC_MIIA_GB   (1 << 0)

MII busy

Definition at line 135 of file enet_18xx_43xx.h.

#define MAC_MIIA_GR (   n)    ((n) << 6)

MII register. n = 0..31

Definition at line 138 of file enet_18xx_43xx.h.

#define MAC_MIIA_PA (   n)    ((n) << 11)

Physical layer address, n = 0..31

Definition at line 139 of file enet_18xx_43xx.h.

#define MAC_MIIA_W   (1 << 1)

MII write

Definition at line 136 of file enet_18xx_43xx.h.

#define MAC_MIID_GDMSK   (0xFFFF)

MII data mask

Definition at line 144 of file enet_18xx_43xx.h.

#define MAC_PMT_GU   (1 << 9)

Global Unicast

Definition at line 171 of file enet_18xx_43xx.h.

#define MAC_PMT_MPE   (1 << 1)

Magic packet enable

Definition at line 167 of file enet_18xx_43xx.h.

#define MAC_PMT_MPR   (1 << 5)

Magic Packet Received

Definition at line 169 of file enet_18xx_43xx.h.

#define MAC_PMT_PD   (1 << 0)

Power-down

Definition at line 166 of file enet_18xx_43xx.h.

#define MAC_PMT_WFE   (1 << 2)

Wake-up frame enable

Definition at line 168 of file enet_18xx_43xx.h.

#define MAC_PMT_WFFRPR   (1UL << 31)

Wake-up Frame Filter Register Pointer Reset

Definition at line 172 of file enet_18xx_43xx.h.

#define MAC_PMT_WFR   (1 << 6)

Wake-up Frame Received

Definition at line 170 of file enet_18xx_43xx.h.

#define MAC_TS_TSADDR   (1 << 5)

Addend Reg Update

Definition at line 197 of file enet_18xx_43xx.h.

#define MAC_TS_TSCFUP   (1 << 1)

Time Stamp Fine or Coarse Update

Definition at line 193 of file enet_18xx_43xx.h.

#define MAC_TS_TSCLKT (   n)    ((n) << 16)

Select the type of clock node, n = see menual

Definition at line 206 of file enet_18xx_43xx.h.

#define MAC_TS_TSCTRL   (1 << 9)

Time Stamp Digital or Binary rollover control

Definition at line 199 of file enet_18xx_43xx.h.

#define MAC_TS_TSENA   (1 << 0)

Time Stamp Enable

Definition at line 192 of file enet_18xx_43xx.h.

#define MAC_TS_TSENAL   (1 << 8)

Enable Time Stamp for All Frames

Definition at line 198 of file enet_18xx_43xx.h.

#define MAC_TS_TSENMA   (1 << 18)

Enable MAC address for PTP frame filtering

Definition at line 207 of file enet_18xx_43xx.h.

#define MAC_TS_TSEVNT   (1 << 14)

Enable Time Stamp Snapshot for Event Messages

Definition at line 204 of file enet_18xx_43xx.h.

#define MAC_TS_TSINIT   (1 << 2)

Time Stamp Initialize

Definition at line 194 of file enet_18xx_43xx.h.

#define MAC_TS_TSIPENA   (1 << 11)

Enable Time Stamp Snapshot for PTP over Ethernet frames

Definition at line 201 of file enet_18xx_43xx.h.

#define MAC_TS_TSIPV4E   (1 << 13)

Enable Time Stamp Snapshot for IPv4 frames

Definition at line 203 of file enet_18xx_43xx.h.

#define MAC_TS_TSIPV6E   (1 << 12)

Enable Time Stamp Snapshot for IPv6 frames

Definition at line 202 of file enet_18xx_43xx.h.

#define MAC_TS_TSMSTR   (1 << 15)

Enable Snapshot for Messages Relevant to Master

Definition at line 205 of file enet_18xx_43xx.h.

#define MAC_TS_TSTRIG   (1 << 4)

Time Stamp Interrupt Trigger Enable

Definition at line 196 of file enet_18xx_43xx.h.

#define MAC_TS_TSUPDT   (1 << 3)

Time Stamp Update

Definition at line 195 of file enet_18xx_43xx.h.

#define MAC_TS_TSVER2   (1 << 10)

Enable PTP packet snooping for version 2 format

Definition at line 200 of file enet_18xx_43xx.h.

#define MAC_VT_ETC   (1 << 7)

Enable 12-Bit VLAN Tag Comparison

Definition at line 161 of file enet_18xx_43xx.h.

#define MAC_VT_VL (   n)    ((n) << 0)

VLAN Tag Identifier for Receive Frames

Definition at line 160 of file enet_18xx_43xx.h.

#define RDES_AFM   (1 << 30)

Destination Address Filter Fail

Definition at line 363 of file enet_18xx_43xx.h.

#define RDES_CE   (1 << 1)

CRC Error

Definition at line 347 of file enet_18xx_43xx.h.

#define RDES_DE   (1 << 14)

Descriptor Error

Definition at line 360 of file enet_18xx_43xx.h.

#define RDES_DINT   (1UL << 31)

Disable interrupt on completion

Definition at line 369 of file enet_18xx_43xx.h.

#define RDES_DRE   (1 << 2)

Dribble Bit Error

Definition at line 348 of file enet_18xx_43xx.h.

#define RDES_ENH_BS1 (   n)    (((n) & 0xFFF) << 0)

Buffer 1 size, enhanced descriptor

Definition at line 385 of file enet_18xx_43xx.h.

#define RDES_ENH_BS2 (   n)    (((n) & 0xFFF) << 16)

Buffer 2 size, enhanced descriptor

Definition at line 384 of file enet_18xx_43xx.h.

#define RDES_ENH_IPCSB   (1 << 5)

IP Checksum Bypassed, enhanced descripto

Definition at line 393 of file enet_18xx_43xx.h.

#define RDES_ENH_IPHE   (1 << 3)

IP Header Error, enhanced descripto

Definition at line 391 of file enet_18xx_43xx.h.

#define RDES_ENH_IPPL (   n)    (((n) & 0x7) >> 2)

IP Payload Type mask and shift, enhanced descripto

Definition at line 390 of file enet_18xx_43xx.h.

#define RDES_ENH_IPPLE   (1 << 4)

IP Payload Error, enhanced descripto

Definition at line 392 of file enet_18xx_43xx.h.

#define RDES_ENH_IPV4   (1 << 6)

IPv4 Packet Received, enhanced descripto

Definition at line 394 of file enet_18xx_43xx.h.

#define RDES_ENH_IPV6   (1 << 7)

IPv6 Packet Received, enhanced descripto

Definition at line 395 of file enet_18xx_43xx.h.

#define RDES_ENH_MTMSK (   n)    (((n) & 0xF) >> 8)

Message Type mask and shift, enhanced descripto

Definition at line 396 of file enet_18xx_43xx.h.

#define RDES_ENH_RCH   (1 << 14)

Second Address Chained, enhanced descriptor

Definition at line 383 of file enet_18xx_43xx.h.

#define RDES_ENH_RER   (1 << 15)

REC_DESC_ENH_T only CTRL field bit defines.

Receive End of Ring, enhanced descriptor

Definition at line 382 of file enet_18xx_43xx.h.

#define RDES_ES   (1 << 15)

ES: Error Summary

Definition at line 361 of file enet_18xx_43xx.h.

#define RDES_ESA   (1 << 0)

Extended Status Available/Rx MAC Address

Definition at line 346 of file enet_18xx_43xx.h.

#define RDES_FLMSK (   n)    (((n) & 0x3FFF0000) >> 16)

Frame Length mask and shift

Definition at line 362 of file enet_18xx_43xx.h.

#define RDES_FS   (1 << 9)

First Descriptor

Definition at line 355 of file enet_18xx_43xx.h.

#define RDES_FT   (1 << 5)

Frame Type

Definition at line 351 of file enet_18xx_43xx.h.

#define RDES_LC   (1 << 6)

Late Collision

Definition at line 352 of file enet_18xx_43xx.h.

#define RDES_LE   (1 << 12)

Length Error

Definition at line 358 of file enet_18xx_43xx.h.

#define RDES_LS   (1 << 8)

Last Descriptor

Definition at line 354 of file enet_18xx_43xx.h.

#define RDES_NORM_BS1 (   n)    (((n) & 0x3FF) << 0)

Buffer 1 size, normal descriptor

Definition at line 377 of file enet_18xx_43xx.h.

#define RDES_NORM_BS2 (   n)    (((n) & 0x3FF) << 11)

Buffer 2 size, normal descriptor

Definition at line 376 of file enet_18xx_43xx.h.

#define RDES_NORM_RCH   (1 << 24)

Second Address Chained, normal descriptor

Definition at line 375 of file enet_18xx_43xx.h.

#define RDES_NORM_RER   (1 << 25)

Receive End of Ring, normal descriptor

Definition at line 374 of file enet_18xx_43xx.h.

#define RDES_OE   (1 << 11)

Overflow Error

Definition at line 357 of file enet_18xx_43xx.h.

#define RDES_OWN   (1UL << 31)

Own Bit

Definition at line 364 of file enet_18xx_43xx.h.

#define RDES_RE   (1 << 3)

Receive Error

Definition at line 349 of file enet_18xx_43xx.h.

#define RDES_RWT   (1 << 4)

Receive Watchdog Timeout

Definition at line 350 of file enet_18xx_43xx.h.

#define RDES_SAF   (1 << 13)

Source Address Filter Fail

Definition at line 359 of file enet_18xx_43xx.h.

#define RDES_TSA   (1 << 7)

Timestamp Available/IP Checksum Error (Type1) /Giant Frame

Definition at line 353 of file enet_18xx_43xx.h.

#define RDES_VLAN   (1 << 10)

VLAN Tag

Definition at line 356 of file enet_18xx_43xx.h.

#define TDES_CCMSK (   n)    (((n) & 0x000000F0) >> 3)

CC: Collision Count (Status field) mask and shift

Definition at line 295 of file enet_18xx_43xx.h.

#define TDES_DB   (1 << 0)

Deferred Bit

Definition at line 292 of file enet_18xx_43xx.h.

#define TDES_EC   (1 << 8)

Excessive Collision

Definition at line 297 of file enet_18xx_43xx.h.

#define TDES_ED   (1 << 2)

Excessive Deferral

Definition at line 294 of file enet_18xx_43xx.h.

#define TDES_ENH_BS1 (   n)    (((n) & 0xFFF) << 0)

Buffer 1 size, enhanced descriptor

Definition at line 341 of file enet_18xx_43xx.h.

#define TDES_ENH_BS2 (   n)    (((n) & 0xFFF) << 16)

Buffer 2 size, enhanced descriptor

Definition at line 340 of file enet_18xx_43xx.h.

#define TDES_ENH_CIC (   n)    ((n) << 22)

Checksum Insertion Control, enhanced descriptor

Definition at line 318 of file enet_18xx_43xx.h.

#define TDES_ENH_DC   (1 << 27)

Disable CRC, enhanced descriptor

Definition at line 315 of file enet_18xx_43xx.h.

#define TDES_ENH_DP   (1 << 26)

Disable Pad, enhanced descriptor

Definition at line 316 of file enet_18xx_43xx.h.

#define TDES_ENH_FS   (1 << 28)

First Segment, enhanced descriptor

Definition at line 314 of file enet_18xx_43xx.h.

#define TDES_ENH_IC   (1UL << 30)

Interrupt on Completion, enhanced descriptor

Definition at line 312 of file enet_18xx_43xx.h.

#define TDES_ENH_LS   (1 << 29)

Last Segment, enhanced descriptor

Definition at line 313 of file enet_18xx_43xx.h.

#define TDES_ENH_TCH   (1 << 20)

Second Address Chained, enhanced descriptor

Definition at line 320 of file enet_18xx_43xx.h.

#define TDES_ENH_TER   (1 << 21)

Transmit End of Ring, enhanced descriptor

Definition at line 319 of file enet_18xx_43xx.h.

#define TDES_ENH_TTSE   (1 << 25)

Transmit Timestamp Enable, enhanced descriptor

Definition at line 317 of file enet_18xx_43xx.h.

#define TDES_ES   (1 << 15)

Error Summary

Definition at line 304 of file enet_18xx_43xx.h.

#define TDES_FF   (1 << 13)

Frame Flushed

Definition at line 302 of file enet_18xx_43xx.h.

#define TDES_IHE   (1 << 16)

IP Header Error

Definition at line 305 of file enet_18xx_43xx.h.

#define TDES_IPE   (1 << 12)

IP Payload Error

Definition at line 301 of file enet_18xx_43xx.h.

#define TDES_JT   (1 << 14)

Jabber Timeout

Definition at line 303 of file enet_18xx_43xx.h.

#define TDES_LC   (1 << 9)

Late Collision

Definition at line 298 of file enet_18xx_43xx.h.

#define TDES_LCAR   (1 << 11)

Loss of Carrier

Definition at line 300 of file enet_18xx_43xx.h.

#define TDES_NC   (1 << 10)

No Carrier

Definition at line 299 of file enet_18xx_43xx.h.

#define TDES_NORM_BS1 (   n)    (((n) & 0x3FF) << 0)

Buffer 1 size, normal descriptor

Definition at line 335 of file enet_18xx_43xx.h.

#define TDES_NORM_BS2 (   n)    (((n) & 0x3FF) << 11)

Buffer 2 size, normal descriptor

Definition at line 334 of file enet_18xx_43xx.h.

#define TDES_NORM_CIC (   n)    ((n) << 27)

Checksum Insertion Control, normal descriptor

Definition at line 328 of file enet_18xx_43xx.h.

#define TDES_NORM_DC   (1 << 26)

Disable CRC, normal descriptor

Definition at line 329 of file enet_18xx_43xx.h.

#define TDES_NORM_DP   (1 << 23)

Disable Pad, normal descriptor

Definition at line 332 of file enet_18xx_43xx.h.

#define TDES_NORM_FS   (1 << 30)

First Segment, normal descriptor

Definition at line 326 of file enet_18xx_43xx.h.

#define TDES_NORM_IC   (1UL << 31)

Interrupt on Completion, normal descriptor

Definition at line 325 of file enet_18xx_43xx.h.

#define TDES_NORM_LS   (1 << 29)

Last Segment, normal descriptor

Definition at line 327 of file enet_18xx_43xx.h.

#define TDES_NORM_TCH   (1 << 24)

Second Address Chained, normal descriptor

Definition at line 331 of file enet_18xx_43xx.h.

#define TDES_NORM_TER   (1 << 25)

Transmit End of Ring, normal descriptor

Definition at line 330 of file enet_18xx_43xx.h.

#define TDES_NORM_TTSE   (1 << 22)

Transmit Timestamp Enable, normal descriptor

Definition at line 333 of file enet_18xx_43xx.h.

#define TDES_OWN   (1UL << 31)

Own Bit

Definition at line 307 of file enet_18xx_43xx.h.

#define TDES_TTSS   (1 << 17)

Transmit Timestamp Status

Definition at line 306 of file enet_18xx_43xx.h.

#define TDES_UF   (1 << 1)

Underflow Error

Definition at line 293 of file enet_18xx_43xx.h.

#define TDES_VF   (1 << 7)

VLAN Frame

Definition at line 296 of file enet_18xx_43xx.h.

Function Documentation

void Chip_ENET_DeInit ( LPC_ENET_T pENET)

De-initialize the ethernet interface.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing

Definition at line 123 of file enet_18xx_43xx.c.

void Chip_ENET_Init ( LPC_ENET_T pENET,
uint32_t  phyAddr 
)

Initialize ethernet interface.

Parameters
pENET: The base of ENET peripheral on the chip
phyAddr: Address of the Phy [valid range 0 to 31]
Returns
Nothing
Note
Performs basic initialization of the ethernet interface in a default state. This is enough to place the interface in a usable state, but may require more setup outside this function.

Definition at line 87 of file enet_18xx_43xx.c.

STATIC INLINE void Chip_ENET_InitDescriptors ( LPC_ENET_T pENET,
ENET_ENHTXDESC_T pTXDescs,
ENET_ENHRXDESC_T pRXDescs 
)

Configures the initial ethernet descriptors.

Parameters
pENET: The base of ENET peripheral on the chip
pTXDescs: Pointer to TX descriptor list
pRXDescs: Pointer to RX descriptor list
Returns
Nothing

Definition at line 624 of file enet_18xx_43xx.h.

STATIC INLINE bool Chip_ENET_IsMIIBusy ( LPC_ENET_T pENET)

Returns MII link (PHY) busy status.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Returns true if busy, otherwise false

Definition at line 518 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_MIIEnable ( LPC_ENET_T pENET)

Enable MII ethernet operation.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing
Note
This function must be called to enable the MII PHY, and must be called before calling any Ethernet functions.

Definition at line 596 of file enet_18xx_43xx.h.

STATIC INLINE uint16_t Chip_ENET_ReadMIIData ( LPC_ENET_T pENET)

Returns the value read from the PHY.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Read value from PHY

Definition at line 528 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_Reset ( LPC_ENET_T pENET)

Resets the ethernet interface.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing
Note
Resets the ethernet interface. This should be called prior to Chip_ENET_Init with a small delay after this call.

Definition at line 458 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_RMIIEnable ( LPC_ENET_T pENET)

Enable RMII ethernet operation.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing
Note
This function must be called to enable the internal RMII PHY, and must be called before calling any Ethernet functions.

Definition at line 583 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_RXDisable ( LPC_ENET_T pENET)

Disables ethernet packet reception.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing

Definition at line 570 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_RXEnable ( LPC_ENET_T pENET)

Enables ethernet packet reception.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing

Definition at line 559 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_RXStart ( LPC_ENET_T pENET)

Starts receive polling of RX descriptors.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing

Definition at line 637 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_SetADDR ( LPC_ENET_T pENET,
const uint8_t *  macAddr 
)

Sets the address of the interface.

Parameters
pENET: The base of ENET peripheral on the chip
macAddr: Pointer to the 6 bytes used for the MAC address
Returns
Nothing

Definition at line 472 of file enet_18xx_43xx.h.

void Chip_ENET_SetDuplex ( LPC_ENET_T pENET,
bool  full 
)

Sets full or half duplex for the interface.

Parameters
pENET: The base of ENET peripheral on the chip
full: true to selected full duplex, false for half
Returns
Nothing

Definition at line 162 of file enet_18xx_43xx.c.

void Chip_ENET_SetSpeed ( LPC_ENET_T pENET,
bool  speed100 
)

Sets speed for the interface.

Parameters
pENET: The base of ENET peripheral on the chip
speed100: true to select 100Mbps mode, false for 10Mbps
Returns
Nothing

Definition at line 173 of file enet_18xx_43xx.c.

void Chip_ENET_SetupMII ( LPC_ENET_T pENET,
uint32_t  div,
uint8_t  addr 
)

Sets up the PHY link clock divider and PHY address.

Parameters
pENET: The base of ENET peripheral on the chip
div: Divider index, not a divider value, see user manual
addr: PHY address, used with MII read and write
Returns
Nothing

Definition at line 138 of file enet_18xx_43xx.c.

void Chip_ENET_StartMIIRead ( LPC_ENET_T pENET,
uint8_t  reg 
)

Starts a PHY read via the MII.

Parameters
pENET: The base of ENET peripheral on the chip
reg: PHY register to read
Returns
Nothing
Note
Start a PHY read operation. Does not block, requires calling IP_ENET_IsMIIBusy to determine when read is complete and calling IP_ENET_ReadMIIData to get the data.

Definition at line 154 of file enet_18xx_43xx.c.

void Chip_ENET_StartMIIWrite ( LPC_ENET_T pENET,
uint8_t  reg,
uint16_t  data 
)

Starts a PHY write via the MII.

Parameters
pENET: The base of ENET peripheral on the chip
reg: PHY register to write
data: Data to write to PHY register
Returns
Nothing
Note
Start a PHY write operation. Does not block, requires calling IP_ENET_IsMIIBusy to determine when write is complete.

Definition at line 145 of file enet_18xx_43xx.c.

STATIC INLINE void Chip_ENET_TXDisable ( LPC_ENET_T pENET)

Disables ethernet transmit.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing

Definition at line 549 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_TXEnable ( LPC_ENET_T pENET)

Enables ethernet transmit.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing

Definition at line 538 of file enet_18xx_43xx.h.

STATIC INLINE void Chip_ENET_TXStart ( LPC_ENET_T pENET)

Starts transmit polling of TX descriptors.

Parameters
pENET: The base of ENET peripheral on the chip
Returns
Nothing

Definition at line 648 of file enet_18xx_43xx.h.