LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
spi_18xx_43xx.h
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1 /*
2  * @brief LPC43xx SPI driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SPI_43XX_H_
33 #define __SPI_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
44 #if defined(CHIP_LPC43XX)
45 
49 typedef struct {
50  __IO uint32_t CR;
51  __I uint32_t SR;
52  __IO uint32_t DR;
53  __IO uint32_t CCR;
54  __I uint32_t RESERVED0[3];
55  __IO uint32_t INT;
56 } LPC_SPI_T;
57 
58 /*
59  * Macro defines for SPI Control register
60  */
61 /* SPI CFG Register BitMask */
62 #define SPI_CR_BITMASK ((uint32_t) 0xFFC)
63 
64 #define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
65 
66 #define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
67 
68 #define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
69 
70 #define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /*Capture data on the first edge, Change data on the following edge*/
71 #define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /*Change data on the first edge, Capture data on the following edge*/
72 
73 #define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
74 #define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
75 
76 #define SPI_CR_SLAVE_EN ((uint32_t) 0)
77 
78 #define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
79 
80 #define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /*Data will be transmitted and received in standard order (MSB first).*/
81 
82 #define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /*Data will be transmitted and received in reverse order (LSB first).*/
83 
84 #define SPI_CR_INT_EN ((uint32_t) (1 << 7))
85 
86 /*
87  * Macro defines for SPI Status register
88  */
90 #define SPI_SR_BITMASK ((uint32_t) 0xF8)
91 
92 #define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
93 /* Mode fault Flag */
94 #define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
95 
96 #define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
97 
98 #define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
99 
100 #define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
101 
102 #define SPI_SR_ERROR (SPI_SR_ABRT | SPI_SR_MODF | SPI_SR_ROVR | SPI_SR_WCOL)
103 /*
104  * Macro defines for SPI Test Control Register register
105  */
106 /*Enable SPI Test Mode */
107 #define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
108 
109 /*
110  * Macro defines for SPI Interrupt register
111  */
113 #define SPI_INT_SPIF ((uint32_t) (1 << 0))
114 
119 #define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
120 
122 typedef enum {
123  SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
124  SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
125 } SPI_MODE_T;
126 
128 typedef enum {
129  SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_FIRST,
130  SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_FIRST,
131  SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO | SPI_CR_CPHA_SECOND,
132  SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI | SPI_CR_CPHA_SECOND,
133  SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0,
134  SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0,
135  SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1,
136  SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1,
137 } SPI_CLOCK_MODE_T;
138 
140 typedef enum {
141  SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
142  SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
143 } SPI_DATA_ORDER_T;
144 
145 /*
146  * @brief Number of bits per frame
147  */
148 typedef enum {
149  SPI_BITS_8 = SPI_CR_BITS(8),
150  SPI_BITS_9 = SPI_CR_BITS(9),
151  SPI_BITS_10 = SPI_CR_BITS(10),
152  SPI_BITS_11 = SPI_CR_BITS(11),
153  SPI_BITS_12 = SPI_CR_BITS(12),
154  SPI_BITS_13 = SPI_CR_BITS(13),
155  SPI_BITS_14 = SPI_CR_BITS(14),
156  SPI_BITS_15 = SPI_CR_BITS(15),
157  SPI_BITS_16 = SPI_CR_BITS(16),
158 } SPI_BITS_T;
159 
161 typedef void (*SPI_CALLBACK_T)(void);
162 /*
163  * @brief SPI config format
164  */
165 typedef struct {
166  SPI_BITS_T bits;
167  SPI_CLOCK_MODE_T clockMode;
168  SPI_DATA_ORDER_T dataOrder;
169 } SPI_CONFIG_FORMAT_T;
170 
171 /*
172  * @brief SPI data setup structure
173  */
174 typedef struct {
175  uint8_t *pTxData;
176  uint8_t *pRxData;
177  uint32_t cnt;
178  uint32_t length;
179  SPI_CALLBACK_T fnBefFrame;
180  SPI_CALLBACK_T fnAftFrame;
181  SPI_CALLBACK_T fnBefTransfer;
182  SPI_CALLBACK_T fnAftTransfer;
183 } SPI_DATA_SETUP_T;
184 
189 STATIC INLINE uint32_t Chip_SPI_GetStatus(LPC_SPI_T *pSPI)
190 {
191  return pSPI->SR;
192 }
193 
200 STATIC INLINE void Chip_SPI_SendFrame(LPC_SPI_T *pSPI, uint16_t data)
201 {
202  pSPI->DR = SPI_DR_DATA(data);
203 }
204 
210 STATIC INLINE uint16_t Chip_SPI_ReceiveFrame(LPC_SPI_T *pSPI)
211 {
212  return SPI_DR_DATA(pSPI->DR);
213 }
214 
223 STATIC INLINE void Chip_SPI_SetClockCounter(LPC_SPI_T *pSPI, uint32_t counter)
224 {
225  pSPI->CCR = counter;
226 }
227 
234 STATIC INLINE void Chip_SPI_SetFormat(LPC_SPI_T *pSPI, SPI_CONFIG_FORMAT_T *format)
235 {
236  pSPI->CR = (pSPI->CR & (~0xF1C)) | SPI_CR_BIT_EN | format->bits | format->clockMode | format->dataOrder;
237 }
238 
244 STATIC INLINE SPI_BITS_T Chip_SPI_GetDataSize(LPC_SPI_T *pSPI)
245 {
246  return (pSPI->CR & SPI_CR_BIT_EN) ? ((SPI_BITS_T) (pSPI->CR & SPI_CR_BITS_MASK)) : SPI_BITS_8;
247 }
248 
254 STATIC INLINE SPI_CLOCK_MODE_T Chip_SPI_GetClockMode(LPC_SPI_T *pSPI)
255 {
256  return (SPI_CLOCK_MODE_T) (pSPI->CR & (3 << 3));
257 }
258 
264 STATIC INLINE SPI_MODE_T Chip_SPI_GetMode(LPC_SPI_T *pSPI)
265 {
266  return (SPI_MODE_T) (pSPI->CR & (1 << 5));
267 }
268 
275 STATIC INLINE void Chip_SPI_SetMode(LPC_SPI_T *pSPI, SPI_MODE_T mode)
276 {
277  pSPI->CR = (pSPI->CR & (~(1 << 5))) | mode;
278 }
279 
286 void Chip_SPI_SetBitRate(LPC_SPI_T *pSPI, uint32_t bitRate);
287 
293 STATIC INLINE void Chip_SPI_Int_Enable(LPC_SPI_T *pSPI)
294 {
295  pSPI->CR |= SPI_CR_INT_EN;
296 }
297 
303 STATIC INLINE void Chip_SPI_Int_Disable(LPC_SPI_T *pSPI)
304 {
305  pSPI->CR &= ~SPI_CR_INT_EN;
306 }
307 
313 STATIC INLINE uint32_t Chip_SPI_Int_GetStatus(LPC_SPI_T *pSPI)
314 {
315  return pSPI->INT;
316 }
317 
324 STATIC INLINE void Chip_SPI_Int_ClearStatus(LPC_SPI_T *pSPI, uint32_t mask)
325 {
326  pSPI->INT = mask;
327 }
328 
334 void Chip_SPI_Init(LPC_SPI_T *pSPI);
335 
342 void Chip_SPI_DeInit(LPC_SPI_T *pSPI);
343 
349 void Chip_SPI_Int_FlushData(LPC_SPI_T *pSPI);
350 
358 Status Chip_SPI_Int_RWFrames8Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup);
359 
367 Status Chip_SPI_Int_RWFrames16Bits(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *xf_setup);
368 
380 uint32_t Chip_SPI_RWFrames_Blocking(LPC_SPI_T *pSPI, SPI_DATA_SETUP_T *pXfSetup);
381 
392 uint32_t Chip_SPI_WriteFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len);
393 
404 uint32_t Chip_SPI_ReadFrames_Blocking(LPC_SPI_T *pSPI, uint8_t *buffer, uint32_t buffer_len);
405 
406 #endif
407 
412 #ifdef __cplusplus
413 }
414 #endif
415 
416 #endif /* __SPI_43XX_H_ */