LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_board/boards_43xx/ngx_xplorer_4330/board_sysinit.c Source File

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board_sysinit.c
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1 /*
2 * Copyright(C) NXP Semiconductors, 2012
3 * All rights reserved.
4 *
5 * Software that is described herein is for illustrative purposes only
6 * which provides customers with programming information regarding the
7 * LPC products. This software is supplied "AS IS" without any warranties of
8 * any kind, and NXP Semiconductors and its licensor disclaim any and
9 * all warranties, express or implied, including all implied warranties of
10 * merchantability, fitness for a particular purpose and non-infringement of
11 * intellectual property rights. NXP Semiconductors assumes no responsibility
12 * or liability for the use of the software, conveys no license or rights under any
13 * patent, copyright, mask work right, or any other intellectual property rights in
14 * or to any products. NXP Semiconductors reserves the right to make changes
15 * in the software without notification. NXP Semiconductors also makes no
16 * representation or warranty that such application will be suitable for the
17 * specified use without further testing or modification.
18 *
19 * Permission to use, copy, modify, and distribute this software and its
20 * documentation is hereby granted, under NXP Semiconductors' and its
21 * licensor's relevant copyrights in the software, without fee, provided that it
22 * is used in conjunction with NXP Semiconductors microcontrollers. This
23 * copyright, permission, and disclaimer notice must appear in all copies of
24 * this code.
25 */
26
27 #include "board.h"
28
29 /* The System initialization code is called prior to the application and
30 initializes the board for run-time operation. */
31
32 /*****************************************************************************
33 * Private types/enumerations/variables
34 ****************************************************************************/
35
36 /* Structure for initial base clock states */
37 struct CLK_BASE_STATES {
38 CHIP_CGU_BASE_CLK_T clk; /* Base clock */
39 CHIP_CGU_CLKIN_T clkin; /* Base clock source, see UM for allowable souorces per base clock */
40 bool autoblock_enab;/* Set to true to enable autoblocking on frequency change */
41 bool powerdn; /* Set to true if the base clock is initially powered down */
42 };
43
44 /* Initial base clock states are mostly on */
45 STATIC const struct CLK_BASE_STATES InitClkStates[] = {
46 {CLK_BASE_PHY_TX, CLKIN_ENET_TX, true, false},
47 #if defined(USE_RMII)
48 {CLK_BASE_PHY_RX, CLKIN_ENET_TX, true, false},
49 #else
50 {CLK_BASE_PHY_RX, CLKIN_ENET_RX, true, false},
51 #endif
52
53 /* Clocks derived from dividers */
54 {CLK_BASE_LCD, CLKIN_IDIVC, true, false},
55 {CLK_BASE_USB1, CLKIN_IDIVD, true, true}
56 };
57
58 /* SPIFI high speed pin mode setup */
59 STATIC const PINMUX_GRP_T spifipinmuxing[] = {
60 {0x3, 3, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI CLK */
61 {0x3, 4, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D3 */
62 {0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D2 */
63 {0x3, 6, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D1 */
64 {0x3, 7, (SCU_PINIO_FAST | SCU_MODE_FUNC3)}, /* SPIFI D0 */
65 {0x3, 8, (SCU_PINIO_FAST | SCU_MODE_FUNC3)} /* SPIFI CS/SSEL */
66 };
67
68 STATIC const PINMUX_GRP_T pinmuxing[] = {
69 /* RMII pin group */
70 {0x1, 15,
71 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
72 {0x0, 0,
73 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC2)},
74 {0x1, 16,
75 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
76 {0x0, 1, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC6)},
77 {0x1, 19,
78 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC0)},
79 {0x1, 18, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
80 {0x1, 20, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
81 {0x1, 17,
82 (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC3)},
83 {0x2, 0, (SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INACT | SCU_MODE_ZIF_DIS | SCU_MODE_FUNC7)},
84 /* Board LEDs */
85 {0x2, 11, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
86 {0x2, 12, (SCU_MODE_INBUFF_EN | SCU_MODE_PULLDOWN | SCU_MODE_FUNC0)},
87 /* I2S */
88 {0x3, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
89 {0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)},
90 {0x7, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
91 {0x6, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
92 {0x7, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC2)},
93 {0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)},
94 };
95
96 /*****************************************************************************
97 * Public types/enumerations/variables
98 ****************************************************************************/
99
100 /*****************************************************************************
101 * Private functions
102 ****************************************************************************/
103
104 /*****************************************************************************
105 * Public functions
106 ****************************************************************************/
107
108 /* Sets up system pin muxing */
109 void Board_SetupMuxing(void)
110 {
111 /* Setup system level pin muxing */
112 Chip_SCU_SetPinMuxing(pinmuxing, sizeof(pinmuxing) / sizeof(PINMUX_GRP_T));
113
114 /* SPIFI pin setup is done prior to setting up system clocking */
115 Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T));
116 }
117
118 /* Set up and initialize clocking prior to call to main */
119 void Board_SetupClocking(void)
120 {
121 int i;
122
123 Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
124
125 /* Reset and enable 32Khz oscillator */
126 LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
127 LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
128
129 /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
130 Divide rate is based on CPU speed and speed of SPI FLASH part. */
131 #if (MAX_CLOCK_FREQ > 180000000)
132 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
133 #else
134 Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
135 #endif
136 Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
137
138 /* Setup system base clocks and initial states. This won't enable and
139 disable individual clocks, but sets up the base clock sources for
140 each individual peripheral clock. */
141 for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
142 Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
143 InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
144 }
145 }
146
147 /* Set up and initialize hardware prior to call to main */
148 void Board_SystemInit(void)
149 {
150 /* Setup system clocking and memory. This is done early to allow the
151 application and tools to clear memory and use scatter loading to
152 external memory. */
153 Board_SetupMuxing();
154 Board_SetupClocking();
155 }