LPCOpen Platform for LPC18XX/43XX microcontrollers: CHIP: LPC43xx peripheral interrupt numbers

| LPCOpen Platform for LPC18XX/43XX microcontrollers 18XX43XX LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers

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CHIP: LPC43xx peripheral interrupt numbers
CHIP: LPC43xx CMSIS include file

## Detailed Description

## Enumerations
enum | LPC43XX_IRQn_Type { Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DAC_IRQn = 0, M0APP_IRQn = 1, DMA_IRQn = 2, RESERVED1_IRQn = 3, RESERVED2_IRQn = 4, ETHERNET_IRQn = 5, SDIO_IRQn = 6, LCD_IRQn = 7, USB0_IRQn = 8, USB1_IRQn = 9, SCT_IRQn = 10, RITIMER_IRQn = 11, TIMER0_IRQn = 12, TIMER1_IRQn = 13, TIMER2_IRQn = 14, TIMER3_IRQn = 15, MCPWM_IRQn = 16, ADC0_IRQn = 17, I2C0_IRQn = 18, I2C1_IRQn = 19, SPI_INT_IRQn = 20, ADC1_IRQn = 21, SSP0_IRQn = 22, SSP1_IRQn = 23, USART0_IRQn = 24, UART1_IRQn = 25, USART2_IRQn = 26, USART3_IRQn = 27, I2S0_IRQn = 28, I2S1_IRQn = 29, RESERVED4_IRQn = 30, SGPIO_INT_IRQn = 31, PIN_INT0_IRQn = 32, PIN_INT1_IRQn = 33, PIN_INT2_IRQn = 34, PIN_INT3_IRQn = 35, PIN_INT4_IRQn = 36, PIN_INT5_IRQn = 37, PIN_INT6_IRQn = 38, PIN_INT7_IRQn = 39, GINT0_IRQn = 40, GINT1_IRQn = 41, EVENTROUTER_IRQn = 42, C_CAN1_IRQn = 43, RESERVED6_IRQn = 44, ADCHS_IRQn = 45, ATIMER_IRQn = 46, RTC_IRQn = 47, RESERVED8_IRQn = 48, WWDT_IRQn = 49, M0SUB_IRQn = 50, C_CAN0_IRQn = 51, QEI_IRQn = 52 }

## Enumeration Type Documentation

enum LPC43XX_IRQn_Type

Enumerator
Reset_IRQn | 1 Reset Vector, invoked on Power up and warm reset
NonMaskableInt_IRQn | 2 Non maskable Interrupt, cannot be stopped or preempted
HardFault_IRQn | 3 Hard Fault, all classes of Fault
MemoryManagement_IRQn | 4 Memory Management, MPU mismatch, including Access Violation and No Match
BusFault_IRQn | 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault
UsageFault_IRQn | 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition
SVCall_IRQn | 11 System Service Call via SVC instruction
DebugMonitor_IRQn | 12 Debug Monitor
PendSV_IRQn | 14 Pendable request for system service
SysTick_IRQn | 15 System Tick Timer
DAC_IRQn | 0 DAC
M0APP_IRQn | 1 M0APP Core interrupt
DMA_IRQn | 2 DMA
RESERVED1_IRQn | 3 EZH/EDM
RESERVED2_IRQn |
ETHERNET_IRQn | 5 ETHERNET
SDIO_IRQn | 6 SDIO
LCD_IRQn | 7 LCD
USB0_IRQn | 8 USB0
USB1_IRQn | 9 USB1
SCT_IRQn | 10 SCT
RITIMER_IRQn | 11 RITIMER
TIMER0_IRQn | 12 TIMER0
TIMER1_IRQn | 13 TIMER1
TIMER2_IRQn | 14 TIMER2
TIMER3_IRQn | 15 TIMER3
MCPWM_IRQn | 16 MCPWM
ADC0_IRQn | 17 ADC0
I2C0_IRQn | 18 I2C0
I2C1_IRQn | 19 I2C1
SPI_INT_IRQn | 20 SPI_INT
ADC1_IRQn | 21 ADC1
SSP0_IRQn | 22 SSP0
SSP1_IRQn | 23 SSP1
USART0_IRQn | 24 USART0
UART1_IRQn | 25 UART1
USART2_IRQn | 26 USART2
USART3_IRQn | 27 USART3
I2S0_IRQn | 28 I2S0
I2S1_IRQn | 29 I2S1
RESERVED4_IRQn |
SGPIO_INT_IRQn | 31 SGPIO_IINT
PIN_INT0_IRQn | 32 PIN_INT0
PIN_INT1_IRQn | 33 PIN_INT1
PIN_INT2_IRQn | 34 PIN_INT2
PIN_INT3_IRQn | 35 PIN_INT3
PIN_INT4_IRQn | 36 PIN_INT4
PIN_INT5_IRQn | 37 PIN_INT5
PIN_INT6_IRQn | 38 PIN_INT6
PIN_INT7_IRQn | 39 PIN_INT7
GINT0_IRQn | 40 GINT0
GINT1_IRQn | 41 GINT1
EVENTROUTER_IRQn | 42 EVENTROUTER
C_CAN1_IRQn | 43 C_CAN1
RESERVED6_IRQn |
ADCHS_IRQn | 45 ADCHS interrupt
ATIMER_IRQn | 46 ATIMER
RTC_IRQn | 47 RTC
RESERVED8_IRQn |
WWDT_IRQn | 49 WWDT
M0SUB_IRQn | 50 M0SUB core interrupt
C_CAN0_IRQn | 51 C_CAN0
QEI_IRQn | 52 QEI

Definition at line 81 of file cmsis_43xx.h.