LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
hsadc_18xx_43xx.c
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1 /*
2  * @brief LPC18xx/43xx High speed ADC driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2013
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #include "chip.h"
33 
34 /*****************************************************************************
35  * Private types/enumerations/variables
36  ****************************************************************************/
37 
38 /* CRS and DGEC values mapped to maximum HSADC sample rates */
39 typedef struct {
40  uint32_t minRate;
41  uint8_t crs;
42  uint8_t dgec;
43 } CRSDCEG_T;
44 static const CRSDCEG_T powerSets[] = {
45  {20000000, 0, 0x0}, /* Use 0/0 for less than 20MHz */
46  {30000000, 1, 0x0}, /* Use 1/0 for less than 30MHz */
47  {50000000, 2, 0x0}, /* Use 2/0 for less than 50MHz */
48  {65000000, 3, 0xF}, /* Use 3/F for less than 65MHz */
49  {0xFFFFFFFF, 4, 0xE}, /* Use 4/E for everything else */
50 };
51 
52 /*****************************************************************************
53  * Public types/enumerations/variables
54  ****************************************************************************/
55 
56 /*****************************************************************************
57  * Private functions
58  ****************************************************************************/
59 
60 /*****************************************************************************
61  * Public functions
62  ****************************************************************************/
63 
64 /* Initialize the High speed ADC */
66 {
67  /* Enable HSADC register clock */
68  Chip_Clock_EnableOpts(CLK_MX_ADCHS, true, true, 1);
69 
70  /* Enable HSADC sample clock */
71  Chip_Clock_Enable(CLK_ADCHS);
72 
73  /* Reset HSADC, will auto-clear */
74  Chip_RGU_TriggerReset(RGU_ADCHS_RST);
75 }
76 
77 /* Shutdown ADC */
79 {
80  /* Power down */
82 
83  /* Reset HSADC and wait for clear, will auto-clear */
84  Chip_RGU_TriggerReset(RGU_ADCHS_RST);
85  while (Chip_RGU_InReset(RGU_ADCHS_RST)) {}
86 
87  /* SHutdown HSADC clock after reset is complete */
88  Chip_Clock_Disable(CLK_MX_ADCHS);
89 }
90 
91 /* Sets up HSADC FIFO trip level and packing */
92 void Chip_HSADC_SetupFIFO(LPC_HSADC_T *pHSADC, uint8_t trip, bool packed)
93 {
94  uint32_t val = (uint32_t) trip << 1;
95  if (packed) {
96  val |= 1;
97  }
98 
99  pHSADC->FIFO_CFG = val;
100 }
101 
102 /* Set HSADC Threshold low value */
103 void Chip_HSADC_SetThrLowValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value)
104 {
105  uint32_t reg;
106 
107  reg = pHSADC->THR[thrnum] & ~0xFFF;
108  pHSADC->THR[thrnum] = reg | (uint32_t) value;
109 }
110 
111 /* Set HSADC Threshold high value */
112 void Chip_HSADC_SetThrHighValue(LPC_HSADC_T *pHSADC, uint8_t thrnum, uint16_t value)
113 {
114  uint32_t reg;
115 
116  reg = pHSADC->THR[thrnum] & ~0xFFF0000;
117  pHSADC->THR[thrnum] = reg | (((uint32_t) value) << 16);
118 }
119 
120 /* Setup speed for a input channel */
121 void Chip_HSADC_SetSpeed(LPC_HSADC_T *pHSADC, uint8_t channel, uint8_t speed)
122 {
123  uint32_t reg, shift = channel * 4;
124 
125  reg = pHSADC->ADC_SPEED & ~(0xF << shift);
126  pHSADC->ADC_SPEED = reg | (speed << shift);
127 }
128 
129 /* Setup (common) HSADC power and speed settings */
130 void Chip_HSADC_SetPowerSpeed(LPC_HSADC_T *pHSADC, bool comp2)
131 {
132  uint32_t rate, val, orBits;
133  int i, idx;
134 
135  /* Get current clock rate for HSADC */
136  rate = Chip_HSADC_GetBaseClockRate(pHSADC);
137 
138  /* Determine optimal CRS and DCEG settings based on clock rate */
139  idx = 0;
140  while (rate > powerSets[idx].minRate) {
141  idx++;
142  }
143 
144  /* Add CRS selection based on clock speed */
145  orBits = powerSets[idx].crs;
146 
147  /* Enable 2's complement data format? */
148  if (comp2) {
149  orBits |= (1 << 16);
150  }
151 
152  /* Update DCEG settings for all channels based on current CRS */
153  for (i = 0; i < 6; i++) {
154  Chip_HSADC_SetSpeed(pHSADC, i, powerSets[idx].dgec);
155  }
156 
157  /* Get current power control register value and mask off bits that
158  may change */
159  val = pHSADC->POWER_CONTROL & ~((1 << 16) | 0xF);
160 
161  /* Update with new power and data format settings */
162  pHSADC->POWER_CONTROL = val | orBits;
163 }
164 
165 /* Setup AC-DC coupling selection for a channel */
166 void Chip_HSADC_SetACDCBias(LPC_HSADC_T *pHSADC, uint8_t channel,
167  HSADC_DCBIAS_T dcInNeg, HSADC_DCBIAS_T dcInPos)
168 {
169  uint32_t reg, mask, orBits;
170 
171  /* Build mask and enable words for selected DCINNEG abd DCINPOS
172  fields for the selected channel */
173  mask = ((1 << 4) | (1 << 10)) << channel;
174  orBits = (((uint32_t) dcInNeg << 4) | ((uint32_t) dcInPos << 10)) << channel;
175 
176  reg = pHSADC->POWER_CONTROL & ~mask;
177  pHSADC->POWER_CONTROL = reg | orBits;
178 }