LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
ssp_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx SSP driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __SSP_18XX_43XX_H_
33 #define __SSP_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef struct {
48  __IO uint32_t CR0;
49  __IO uint32_t CR1;
50  __IO uint32_t DR;
51  __I uint32_t SR;
52  __IO uint32_t CPSR;
53  __IO uint32_t IMSC;
54  __I uint32_t RIS;
55  __I uint32_t MIS;
56  __O uint32_t ICR;
57  __IO uint32_t DMACR;
58 } LPC_SSP_T;
59 
65 #define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
66 
67 #define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
68 
69 #define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
70 
71 #define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
72 
74 #define SSP_CR0_CPOL_LO ((uint32_t) (0))
75 #define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
76 
78 #define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
79 #define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
80 
82 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
83 
84 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
85 
86 #define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
87 
89 #define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
90 
96 #define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
97 
98 #define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
99 
100 #define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
101 #define SSP_CR1_MASTER_EN ((uint32_t) (0))
102 
104 #define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
105 
106 #define SSP_CR1_BITMASK ((uint32_t) (0x0F))
107 
109 #define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
110 
115 #define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
116 
122 #define SSP_SR_BITMASK ((uint32_t) (0x1F))
123 
125 #define SSP_ICR_BITMASK ((uint32_t) (0x03))
126 
130 typedef enum _SSP_STATUS {
131  SSP_STAT_TFE = ((uint32_t)(1 << 0)),
132  SSP_STAT_TNF = ((uint32_t)(1 << 1)),
133  SSP_STAT_RNE = ((uint32_t)(1 << 2)),
134  SSP_STAT_RFF = ((uint32_t)(1 << 3)),
135  SSP_STAT_BSY = ((uint32_t)(1 << 4)),
136 } SSP_STATUS_T;
137 
141 typedef enum _SSP_INTMASK {
142  SSP_RORIM = ((uint32_t)(1 << 0)),
143  SSP_RTIM = ((uint32_t)(1 << 1)),
144  SSP_RXIM = ((uint32_t)(1 << 2)),
145  SSP_TXIM = ((uint32_t)(1 << 3)),
146  SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
147 } SSP_INTMASK_T;
148 
152 typedef enum _SSP_MASKINTSTATUS {
153  SSP_RORMIS = ((uint32_t)(1 << 0)),
154  SSP_RTMIS = ((uint32_t)(1 << 1)),
155  SSP_RXMIS = ((uint32_t)(1 << 2)),
156  SSP_TXMIS = ((uint32_t)(1 << 3)),
157  SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
159 
163 typedef enum _SSP_RAWINTSTATUS {
164  SSP_RORRIS = ((uint32_t)(1 << 0)),
165  SSP_RTRIS = ((uint32_t)(1 << 1)),
166  SSP_RXRIS = ((uint32_t)(1 << 2)),
167  SSP_TXRIS = ((uint32_t)(1 << 3)),
168  SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
170 
171 typedef enum _SSP_INTCLEAR {
172  SSP_RORIC = 0x0,
173  SSP_RTIC = 0x1,
176 
177 typedef enum _SSP_DMA {
178  SSP_DMA_RX = (1u),
179  SSP_DMA_TX = (1u << 1),
180  SSP_DMA_BITMASK = ((uint32_t)(0x3)),
181 } SSP_DMA_T;
182 
183 /*
184  * @brief SSP clock format
185  */
186 typedef enum CHIP_SSP_CLOCK_FORMAT {
188  SSP_CLOCK_CPHA0_CPOL1 = (1u << 6),
189  SSP_CLOCK_CPHA1_CPOL0 = (2u << 6),
190  SSP_CLOCK_CPHA1_CPOL1 = (3u << 6),
196 
197 /*
198  * @brief SSP frame format
199  */
200 typedef enum CHIP_SSP_FRAME_FORMAT {
201  SSP_FRAMEFORMAT_SPI = (0 << 4),
205 
206 /*
207  * @brief Number of bits per frame
208  */
209 typedef enum CHIP_SSP_BITS {
210  SSP_BITS_4 = (3u << 0),
211  SSP_BITS_5 = (4u << 0),
212  SSP_BITS_6 = (5u << 0),
213  SSP_BITS_7 = (6u << 0),
214  SSP_BITS_8 = (7u << 0),
215  SSP_BITS_9 = (8u << 0),
216  SSP_BITS_10 = (9u << 0),
217  SSP_BITS_11 = (10u << 0),
218  SSP_BITS_12 = (11u << 0),
219  SSP_BITS_13 = (12u << 0),
220  SSP_BITS_14 = (13u << 0),
221  SSP_BITS_15 = (14u << 0),
222  SSP_BITS_16 = (15u << 0),
224 
225 /*
226  * @brief SSP config format
227  */
228 typedef struct SSP_ConfigFormat {
233 
240 {
241  pSSP->CR1 |= SSP_CR1_SSP_EN;
242 }
243 
250 {
251  pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
252 }
253 
262 {
263  pSSP->CR1 |= SSP_CR1_LBM_EN;
264 }
265 
274 {
275  pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
276 }
277 
290 {
291  return (pSSP->SR & Stat) ? SET : RESET;
292 }
293 
301 {
302  return pSSP->MIS;
303 }
304 
317 {
318  return (pSSP->RIS & RawInt) ? SET : RESET;
319 }
320 
328 {
329  return SSP_CR0_DSS(pSSP->CR0);
330 }
331 
342 {
343  pSSP->ICR = IntClear;
344 }
345 
352 {
353  pSSP->IMSC |= SSP_TXIM;
354 }
355 
362 {
363  pSSP->IMSC &= (~SSP_TXIM);
364 }
365 
372 {
373  return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
374 }
375 
382 STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
383 {
384  pSSP->DR = SSP_DR_BITMASK(tx_data);
385 }
386 
395 void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
396 
413 STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
414 {
415  pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
416 }
417 
426 STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
427 {
428  pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
429 }
430 
437 {
438  pSSP->DMACR |= SSP_DMA_BITMASK;
439 }
440 
447 {
448  pSSP->DMACR &= ~SSP_DMA_BITMASK;
449 }
450 
451 /*
452  * @brief SSP mode
453  */
454 typedef enum CHIP_SSP_MODE {
455  SSP_MODE_MASTER = (0 << 2),
456  SSP_MODE_SLAVE = (1u << 2),
458 
459 /*
460  * @brief SPI address
461  */
462 typedef struct {
463  uint8_t port;
464  uint8_t pin;
465 } SPI_Address_t;
466 
467 /*
468  * @brief SSP data setup structure
469  */
470 typedef struct {
471  void *tx_data;
472  uint32_t tx_cnt;
473  void *rx_data;
474  uint32_t rx_cnt;
475  uint32_t length;
477 
480 #define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
481 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
482 
484 /* There's no bug here!!!
485  * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
486  * That means the active clock is in HI state.
487  * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
488  * high between frames. That means the active clock is in LO state.
489  */
490 #define SSP_CPOL_HI SSP_CR0_CPOL_LO
491 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
492 
494 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
495 #define SSP_MASTER_MODE SSP_CR1_MASTER_EN
496 
503 
512 
521 
534 
545 uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, const uint8_t *buffer, uint32_t buffer_len);
546 
557 uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
558 
564 void Chip_SSP_Init(LPC_SSP_T *pSSP);
565 
572 void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
573 
580 void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
581 
588 void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
589 
594 #ifdef __cplusplus
595 }
596 #endif
597 
598 #endif /* __SSP_18XX_43XX_H_ */