LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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chip_18xx_43xx
adc_18xx_43xx.h
Go to the documentation of this file.
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/*
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* @brief LPC18xx/43xx A/D conversion driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __ADC_18XX_43XX_H_
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#define __ADC_18XX_43XX_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#define ADC_ACC_10BITS
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#define ADC_MAX_SAMPLE_RATE 400000
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typedef
struct
{
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__IO uint32_t
CR
;
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__I uint32_t
GDR
;
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__I uint32_t
RESERVED0
;
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__IO uint32_t
INTEN
;
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__I uint32_t DR[8];
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__I uint32_t
STAT
;
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}
LPC_ADC_T
;
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#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF))
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#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17))
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#define ADC_DR_DONE(n) (((n) >> 31))
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#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL)))
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#define ADC_CR_CH_SEL(n) ((1UL << (n)))
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#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8))
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#define ADC_CR_BURST ((1UL << 16))
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#define ADC_CR_PDN ((1UL << 21))
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#define ADC_CR_START_MASK ((7UL << 24))
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#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24))
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#define ADC_CR_START_NOW ((1UL << 24))
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#define ADC_CR_START_CTOUT15 ((2UL << 24))
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#define ADC_CR_START_CTOUT8 ((3UL << 24))
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#define ADC_CR_START_ADCTRIG0 ((4UL << 24))
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#define ADC_CR_START_ADCTRIG1 ((5UL << 24))
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#define ADC_CR_START_MCOA2 ((6UL << 24))
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#define ADC_CR_EDGE ((1UL << 27))
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#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
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typedef
enum
IP_ADC_STATUS {
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ADC_DR_DONE_STAT
,
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ADC_DR_OVERRUN_STAT
,
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ADC_DR_ADINT_STAT
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}
ADC_STATUS_T
;
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typedef
enum
CHIP_ADC_CHANNEL {
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ADC_CH0
= 0,
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ADC_CH1
,
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ADC_CH2
,
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ADC_CH3
,
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ADC_CH4
,
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ADC_CH5
,
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ADC_CH6
,
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ADC_CH7
,
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}
ADC_CHANNEL_T
;
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typedef
enum
CHIP_ADC_RESOLUTION {
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ADC_10BITS
= 0,
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ADC_9BITS
,
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ADC_8BITS
,
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ADC_7BITS
,
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ADC_6BITS
,
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ADC_5BITS
,
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ADC_4BITS
,
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ADC_3BITS
,
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}
ADC_RESOLUTION_T
;
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typedef
enum
CHIP_ADC_EDGE_CFG {
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ADC_TRIGGERMODE_RISING
= 0,
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ADC_TRIGGERMODE_FALLING
,
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}
ADC_EDGE_CFG_T
;
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typedef
enum
CHIP_ADC_START_MODE {
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ADC_NO_START
= 0,
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ADC_START_NOW
,
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ADC_START_ON_CTOUT15
,
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ADC_START_ON_CTOUT8
,
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ADC_START_ON_ADCTRIG0
,
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ADC_START_ON_ADCTRIG1
,
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ADC_START_ON_MCOA2
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}
ADC_START_MODE_T
;
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typedef
struct
{
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uint32_t
adcRate
;
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uint8_t
bitsAccuracy
;
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bool
burstMode
;
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}
ADC_CLOCK_SETUP_T
;
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void
Chip_ADC_Init
(
LPC_ADC_T
*pADC,
ADC_CLOCK_SETUP_T
*ADCSetup);
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void
Chip_ADC_DeInit
(
LPC_ADC_T
*pADC);
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Status
Chip_ADC_ReadValue
(
LPC_ADC_T
*pADC, uint8_t channel, uint16_t *data);
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Status
Chip_ADC_ReadByte
(
LPC_ADC_T
*pADC,
ADC_CHANNEL_T
channel, uint8_t *data);
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FlagStatus
Chip_ADC_ReadStatus
(
LPC_ADC_T
*pADC, uint8_t channel, uint32_t StatusType);
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void
Chip_ADC_Int_SetChannelCmd
(
LPC_ADC_T
*pADC, uint8_t channel,
FunctionalState
NewState);
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STATIC
INLINE
void
Chip_ADC_Int_SetGlobalCmd
(
LPC_ADC_T
*pADC,
FunctionalState
NewState)
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{
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Chip_ADC_Int_SetChannelCmd
(pADC, 8, NewState);
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}
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void
Chip_ADC_SetStartMode
(
LPC_ADC_T
*pADC,
ADC_START_MODE_T
mode,
ADC_EDGE_CFG_T
EdgeOption);
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void
Chip_ADC_SetSampleRate
(
LPC_ADC_T
*pADC,
ADC_CLOCK_SETUP_T
*ADCSetup, uint32_t rate);
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void
Chip_ADC_SetResolution
(
LPC_ADC_T
*pADC,
ADC_CLOCK_SETUP_T
*ADCSetup,
ADC_RESOLUTION_T
resolution);
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void
Chip_ADC_EnableChannel
(
LPC_ADC_T
*pADC,
ADC_CHANNEL_T
channel,
FunctionalState
NewState);
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void
Chip_ADC_SetBurstCmd
(
LPC_ADC_T
*pADC,
FunctionalState
NewState);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* __ADC_18XX_43XX_H_ */
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