LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/config_18xx/cmsis_18xx.h Source File

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cmsis_18xx.h
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1 /*
2 * @brief Basic CMSIS include file for LPC18XX
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2013
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CMSIS_18XX_H_
33 #define __CMSIS_18XX_H_
34
35 #ifndef __CMSIS_H_
36 #error "cmsis_18xx.h should not be included directly use cmsis.h instead"
37 #endif
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
48 #if defined(__ARMCC_VERSION)
49 #pragma diag_suppress 2525
50 #pragma push
51 #pragma anon_unions
52 #elif defined(__CWCC__)
53 #pragma push
54 #pragma cpp_extensions on
55 #elif defined(__GNUC__)
56 /* anonymous unions are enabled by default */
57 #elif defined(__IAR_SYSTEMS_ICC__)
58 #pragma language=extended
59 #else
60 #error Not supported compiler type
61 #endif
62
66 #define __CM3_REV 0x0201
67 #define __MPU_PRESENT 1
68 #define __NVIC_PRIO_BITS 3
69 #define __Vendor_SysTickConfig 0
70 #define __FPU_PRESENT 0
80 typedef enum {
81 /* ------------------------- Cortex-M3 Processor Exceptions Numbers ----------------------------- */
82 Reset_IRQn = -15,
83 NonMaskableInt_IRQn = -14,
84 HardFault_IRQn = -13,
85 MemoryManagement_IRQn = -12,
86 BusFault_IRQn = -11,
87 UsageFault_IRQn = -10,
88 SVCall_IRQn = -5,
89 DebugMonitor_IRQn = -4,
90 PendSV_IRQn = -2,
91 SysTick_IRQn = -1,
93 /* --------------------------- LPC18xx/43xx Specific Interrupt Numbers ------------------------------- */
94 DAC_IRQn = 0,
95 RESERVED0_IRQn = 1,
96 DMA_IRQn = 2,
97 RESERVED1_IRQn = 3,
98 RESERVED2_IRQn = 4,
99 ETHERNET_IRQn = 5,
100 SDIO_IRQn = 6,
101 LCD_IRQn = 7,
102 USB0_IRQn = 8,
103 USB1_IRQn = 9,
104 SCT_IRQn = 10,
105 RITIMER_IRQn = 11,
106 TIMER0_IRQn = 12,
107 TIMER1_IRQn = 13,
108 TIMER2_IRQn = 14,
109 TIMER3_IRQn = 15,
110 MCPWM_IRQn = 16,
111 ADC0_IRQn = 17,
112 I2C0_IRQn = 18,
113 I2C1_IRQn = 19,
114 RESERVED3_IRQn = 20,
115 ADC1_IRQn = 21,
116 SSP0_IRQn = 22,
117 SSP1_IRQn = 23,
118 USART0_IRQn = 24,
119 UART1_IRQn = 25,
120 USART2_IRQn = 26,
121 USART3_IRQn = 27,
122 I2S0_IRQn = 28,
123 I2S1_IRQn = 29,
124 RESERVED4_IRQn = 30,
125 RESERVED5_IRQn = 31,
126 PIN_INT0_IRQn = 32,
127 PIN_INT1_IRQn = 33,
128 PIN_INT2_IRQn = 34,
129 PIN_INT3_IRQn = 35,
130 PIN_INT4_IRQn = 36,
131 PIN_INT5_IRQn = 37,
132 PIN_INT6_IRQn = 38,
133 PIN_INT7_IRQn = 39,
134 GINT0_IRQn = 40,
135 GINT1_IRQn = 41,
136 EVENTROUTER_IRQn = 42,
137 C_CAN1_IRQn = 43,
138 RESERVED6_IRQn = 44,
139 RESERVED7_IRQn = 45,
140 ATIMER_IRQn = 46,
141 RTC_IRQn = 47,
142 RESERVED8_IRQn = 48,
143 WWDT_IRQn = 49,
144 RESERVED9_IRQn = 50,
145 C_CAN0_IRQn = 51,
146 QEI_IRQn = 52,
147 } LPC18XX_IRQn_Type;
148
153 typedef LPC18XX_IRQn_Type IRQn_Type;
154
155 /* Cortex-M3 processor and core peripherals */
156 #include "core_cm3.h"
157
162 #ifdef __cplusplus
163 }
164 #endif
165
166 #endif /* ifndef __CMSIS_18XX_H_ */