LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/chip_clocks.h Source File

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chip_clocks.h
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1 /*
2 * @brief LPC18xx/43xx chip clock list used by CGU and CCU drivers
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CHIP_CLOCKS_H_
33 #define __CHIP_CLOCKS_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
49 typedef enum CHIP_CGU_CLKIN {
50 CLKIN_32K,
51 CLKIN_IRC,
52 CLKIN_ENET_RX,
53 CLKIN_ENET_TX,
54 CLKIN_CLKIN,
55 CLKIN_RESERVED1,
56 CLKIN_CRYSTAL,
57 CLKIN_USBPLL,
58 CLKIN_AUDIOPLL,
59 CLKIN_MAINPLL,
60 CLKIN_RESERVED2,
61 CLKIN_RESERVED3,
62 CLKIN_IDIVA,
63 CLKIN_IDIVB,
64 CLKIN_IDIVC,
65 CLKIN_IDIVD,
66 CLKIN_IDIVE,
67 CLKINPUT_PD
68 } CHIP_CGU_CLKIN_T;
69
78 typedef enum CHIP_CGU_BASE_CLK {
79 CLK_BASE_SAFE,
80 CLK_BASE_USB0,
81 #if defined(CHIP_LPC43XX)
82 CLK_BASE_PERIPH,
83 #else
84 CLK_BASE_RESERVED1,
85 #endif
86 CLK_BASE_USB1,
87 CLK_BASE_MX,
88 CLK_BASE_SPIFI,
89 #if defined(CHIP_LPC43XX)
90 CLK_BASE_SPI,
91 #else
92 CLK_BASE_RESERVED2,
93 #endif
94 CLK_BASE_PHY_RX,
95 CLK_BASE_PHY_TX,
96 CLK_BASE_APB1,
97 CLK_BASE_APB3,
98 CLK_BASE_LCD,
99 #if defined(CHIP_LPC43XX)
100 CLK_BASE_ADCHS,
101 #else
102 CLK_BASE_RESERVED3,
103 #endif
104 CLK_BASE_SDIO,
105 CLK_BASE_SSP0,
106 CLK_BASE_SSP1,
107 CLK_BASE_UART0,
108 CLK_BASE_UART1,
109 CLK_BASE_UART2,
110 CLK_BASE_UART3,
111 CLK_BASE_OUT,
112 CLK_BASE_RESERVED4,
113 CLK_BASE_RESERVED5,
114 CLK_BASE_RESERVED6,
115 CLK_BASE_RESERVED7,
116 CLK_BASE_APLL,
117 CLK_BASE_CGU_OUT0,
118 CLK_BASE_CGU_OUT1,
119 CLK_BASE_LAST,
120 CLK_BASE_NONE = CLK_BASE_LAST
121 } CHIP_CGU_BASE_CLK_T;
122
131 typedef enum CHIP_CGU_IDIV {
132 CLK_IDIV_A,
133 CLK_IDIV_B,
134 CLK_IDIV_C,
135 CLK_IDIV_D,
136 CLK_IDIV_E,
137 CLK_IDIV_LAST
138 } CHIP_CGU_IDIV_T;
139
140 #define CHIP_CGU_IDIV_MASK(x) ("\x03\x0F\x0F\x0F\xFF"[x])
141
149 typedef enum CHIP_CCU_CLK {
150 /* CCU1 clocks */
151 CLK_APB3_BUS,
152 CLK_APB3_I2C1,
153 CLK_APB3_DAC,
154 CLK_APB3_ADC0,
155 CLK_APB3_ADC1,
156 CLK_APB3_CAN0,
157 CLK_APB1_BUS = 32,
158 CLK_APB1_MOTOCON,
159 CLK_APB1_I2C0,
160 CLK_APB1_I2S,
161 CLK_APB1_CAN1,
162 CLK_SPIFI = 64,
163 CLK_MX_BUS = 96,
164 CLK_MX_SPIFI,
165 CLK_MX_GPIO,
166 CLK_MX_LCD,
167 CLK_MX_ETHERNET,
168 CLK_MX_USB0,
169 CLK_MX_EMC,
170 CLK_MX_SDIO,
171 CLK_MX_DMA,
172 CLK_MX_MXCORE,
173 RESERVED_ALIGN = CLK_MX_MXCORE + 3,
174 CLK_MX_SCT,
175 CLK_MX_USB1,
176 CLK_MX_EMC_DIV,
177 CLK_MX_FLASHA,
178 CLK_MX_FLASHB,
179 #if defined(CHIP_LPC43XX)
180 CLK_M4_M0APP,
181 CLK_MX_ADCHS,
182 #else
183 CLK_RESERVED1,
184 CLK_RESERVED2,
185 #endif
186 CLK_MX_EEPROM,
187 CLK_MX_WWDT = 128,
188 CLK_MX_UART0,
189 CLK_MX_UART1,
190 CLK_MX_SSP0,
191 CLK_MX_TIMER0,
192 CLK_MX_TIMER1,
193 CLK_MX_SCU,
194 CLK_MX_CREG,
195 CLK_MX_RITIMER = 160,
196 CLK_MX_UART2,
197 CLK_MX_UART3,
198 CLK_MX_TIMER2,
199 CLK_MX_TIMER3,
200 CLK_MX_SSP1,
201 CLK_MX_QEI,
202 #if defined(CHIP_LPC43XX)
203 CLK_PERIPH_BUS = 192,
204 CLK_RESERVED3,
205 CLK_PERIPH_CORE,
206 CLK_PERIPH_SGPIO,
207 #else
208 CLK_RESERVED3 = 192,
209 CLK_RESERVED3A,
210 CLK_RESERVED4,
211 CLK_RESERVED5,
212 #endif
213 CLK_USB0 = 224,
214 CLK_USB1 = 256,
215 #if defined(CHIP_LPC43XX)
216 CLK_SPI = 288,
217 CLK_ADCHS = 320,
218 #else
219 CLK_RESERVED7 = 320,
220 CLK_RESERVED8,
221 #endif
222 CLK_CCU1_LAST,
223
224 /* CCU2 clocks */
225 CLK_CCU2_START,
226 CLK_APLL = CLK_CCU2_START,
227 RESERVED_ALIGNB = CLK_CCU2_START + 31,
228 CLK_APB2_UART3,
229 RESERVED_ALIGNC = CLK_CCU2_START + 63,
230 CLK_APB2_UART2,
231 RESERVED_ALIGND = CLK_CCU2_START + 95,
232 CLK_APB0_UART1,
233 RESERVED_ALIGNE = CLK_CCU2_START + 127,
234 CLK_APB0_UART0,
235 RESERVED_ALIGNF = CLK_CCU2_START + 159,
236 CLK_APB2_SSP1,
237 RESERVED_ALIGNG = CLK_CCU2_START + 191,
238 CLK_APB0_SSP0,
239 RESERVED_ALIGNH = CLK_CCU2_START + 223,
240 CLK_APB2_SDIO,
241 CLK_CCU2_LAST
242 } CHIP_CCU_CLK_T;
243
248 #ifdef __cplusplus
249 }
250 #endif
251
252 #endif /* __CHIP_CLOCKS_H_ */