LPCOpen Platform for LPC18XX/43XX microcontrollers: HSADC driver setup and initialization

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HSADC driver setup and initialization
LPC18xx/43xx High speed ADC driver use examples

What to know before using this driver
The HSADC peripheral requires several clocks - the register interface clock and the sample clock. Although the driver's Init() and DeInit() functions handle enabling and disabling of the clocks, the sample clock rate is not setup as part of the driver and there are no functions for selecting a sample clock rate as part of the driver. This must be done outside the driver - preferably before calling Chip_HSADC_Init() or any other HSADC driver function. To setup the HSADC sample clock, a base clock source needs to be selected for the HSADC sample clock. The following clock driver function performs this:

        /* Attach the VADC sample clock to a base clock */
        Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, \<BASE_CLOCK\>, true, false);

The selected <BASE_CLOCK> can be one of the selectable input clocks such as CLKIN_IRC or CLKIN_AUDIOPLL or routed via a divider such as CLKIN_IDIVA. The selected clock rate must not exceed 80MHz.
Hint: You can get the clock rate for a base clock by using the Chip_Clock_GetClockInputHz(<BASE_CLOCK>) function. The HSADC sample rate (which includes the base clock and any dividers in the clock generation path can be determined with a call to Chip_HSADC_GetBaseClockRate().

Basic initialization of the HSADC driver
Once HSADC sample clocking is setup, the first call that is needed is a call the Chip_HSADC_Init(). This enables the HSADC clocking and places the HSADC into a default state.

        /* Initialize the HSADC */
        Chip_HSADC_Init(CLK_BASE_ADCHS);

After the HSADC has been initialized with a call to Chip_HSADC_Init(), the HSADC can be setup and configured for desired operation.

HSADC FIFO configuration
The FIFO trip point for a DMA request or interrupt servicing and optional data packing can be setup with the following call.

        /* Setup HSADC to generate an interrupt or DMA request at 8 samples.
           Also enables FIFP data packing (2 samples per FIFO entry)*/
        Chip_HSADC_SetupFIFO(LPC_ADCHS, 8, true);

HSADC trigger setup, channel ID, and recovery time
The HSADC trigger source and level, optional channel ID, and recovery time are configured with a call to Chip_HSADC_ConfigureTrigger().

        /* Usw SW triggering, add channel ID to FIFO word, 60 clocks recovery */
        Chip_HSADC_ConfigureTrigger(LPC_ADCHS, HSADC_CONFIG_TRIGGER_SW, HSADC_CONFIG_TRIGGER_RISEEXT,
            HSADC_CONFIG_TRIGGER_NOEXTSYNC, HSADC_CHANNEL_ID_EN_ADD, 60);

HSADC speed and power setup
The HSADC power and speed settings must be configured to the HSADC sample clock. The Chip_HSADC_SetPowerSpeed() function must be called to set these timings and after any HSADC sample clock rate change. This function also selects the data format used for samples - either binary offset or 2's complement.

        /* Configure HSADC power and speed settings and set data format to 2's complement */
        Chip_HSADC_SetPowerSpeed(LPC_ADCHS, true);

HSADC input biasing setup
The HSADC has 6 input channels. Each channel can be individually configured with it's own bias. To setup a channel for AC biasing, select no bias options for negative and positive biases. If a DC bias is needed, select negative and positive biases.

        /* Select both positive and ngeative DC biasing for input 3 */
        Chip_HSADC_SetACDCBias(LPC_ADCHS, 3, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_DCBIAS);

Enabling HSADC opwer
Before using the HSADC, the power to the ADC and the band gap reference needs to be enabled. The power can be enabled and disabled with a call to Chip_HSADC_EnablePower() or Chip_HSADC_DisablePower() functions.

        /* Enable HSADC power */
     Chip_HSADC_DisablePower(LPC_ADCHS);

Optional threshold setup
HSADC samples can optionally be compared against threshold values during sampling. The status - inside, above, or below the threshold is contained in the status fields of the HSADC sample. Two low and two high thresholds can be setup for monitoring during sampling. These thresolds are setup with the Chip_HSADC_SetThrLowValue() and Chip_HSADC_SetThrHighValue() functions.

        /* Set A low threshold to 10% of maximum sample resolution */
     Chip_HSADC_SetThrLowValue(LPC_ADCHS, 0, ((HSADC_MAX_SAMPLEVAL * 1) / 10));

        /* Set A high threshold to 90% of maximum sample resolution */
     Chip_HSADC_SetThrHighValue(LPC_ADCHS, 0, ((HSADC_MAX_SAMPLEVAL * 9) / 10));

        /* Set B low threshold to 30% of maximum sample resolution */
     Chip_HSADC_SetThrLowValue(LPC_ADCHS, 1, ((HSADC_MAX_SAMPLEVAL * 3) / 10));

        /* Set B high threshold to 70% of maximum sample resolution */
     Chip_HSADC_SetThrHighValue(LPC_ADCHS, 1, ((HSADC_MAX_SAMPLEVAL * 7) / 10));