LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/scu_18xx_43xx.h Source File

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scu_18xx_43xx.h
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1 /*
2 * Copyright(C) NXP Semiconductors, 2012
3 * All rights reserved.
4 *
5 * Software that is described herein is for illustrative purposes only
6 * which provides customers with programming information regarding the
7 * LPC products. This software is supplied "AS IS" without any warranties of
8 * any kind, and NXP Semiconductors and its licensor disclaim any and
9 * all warranties, express or implied, including all implied warranties of
10 * merchantability, fitness for a particular purpose and non-infringement of
11 * intellectual property rights. NXP Semiconductors assumes no responsibility
12 * or liability for the use of the software, conveys no license or rights under any
13 * patent, copyright, mask work right, or any other intellectual property rights in
14 * or to any products. NXP Semiconductors reserves the right to make changes
15 * in the software without notification. NXP Semiconductors also makes no
16 * representation or warranty that such application will be suitable for the
17 * specified use without further testing or modification.
18 *
19 * Permission to use, copy, modify, and distribute this software and its
20 * documentation is hereby granted, under NXP Semiconductors' and its
21 * licensor's relevant copyrights in the software, without fee, provided that it
22 * is used in conjunction with NXP Semiconductors microcontrollers. This
23 * copyright, permission, and disclaimer notice must appear in all copies of
24 * this code.
25 */
26
27 #ifndef __SCU_18XX_43XX_H_
28 #define __SCU_18XX_43XX_H_
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
43 typedef struct {
44 uint8_t pingrp; /* Pin group */
45 uint8_t pinnum; /* Pin number */
46 uint16_t modefunc; /* Pin mode and function for SCU */
47 } PINMUX_GRP_T;
48
52 typedef struct {
53 __IO uint32_t SFSP[16][32];
54 __I uint32_t RESERVED0[256];
55 __IO uint32_t SFSCLK[4];
56 __I uint32_t RESERVED16[28];
57 __IO uint32_t SFSUSB;
58 __IO uint32_t SFSI2C0;
59 __IO uint32_t ENAIO[3];
60 __I uint32_t RESERVED17[27];
61 __IO uint32_t EMCDELAYCLK;
62 __I uint32_t RESERVED18[63];
63 __IO uint32_t PINTSEL[2];
64 } LPC_SCU_T;
65
71 #define SCU_MODE_PULLUP (0x0 << 3)
72 #define SCU_MODE_REPEATER (0x1 << 3)
73 #define SCU_MODE_INACT (0x2 << 3)
74 #define SCU_MODE_PULLDOWN (0x3 << 3)
75 #define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5)
76 #define SCU_MODE_INBUFF_EN (0x1 << 6)
77 #define SCU_MODE_ZIF_DIS (0x1 << 7)
78 #define SCU_MODE_4MA_DRIVESTR (0x0 << 8)
79 #define SCU_MODE_8MA_DRIVESTR (0x1 << 8)
80 #define SCU_MODE_14MA_DRIVESTR (0x2 << 8)
81 #define SCU_MODE_20MA_DRIVESTR (0x3 << 8)
82 #define SCU_MODE_FUNC0 0x0
83 #define SCU_MODE_FUNC1 0x1
84 #define SCU_MODE_FUNC2 0x2
85 #define SCU_MODE_FUNC3 0x3
86 #define SCU_MODE_FUNC4 0x4
87 #define SCU_MODE_FUNC5 0x5
88 #define SCU_MODE_FUNC6 0x6
89 #define SCU_MODE_FUNC7 0x7
90 #define SCU_PINIO_FAST (SCU_MODE_INACT | SCU_MODE_HIGHSPEEDSLEW_EN | SCU_MODE_INBUFF_EN | SCU_MODE_ZIF_DIS)
91
96 #define MD_PUP (0x0 << 3)
97 #define MD_BUK (0x1 << 3)
98 #define MD_PLN (0x2 << 3)
99 #define MD_PDN (0x3 << 3)
100 #define MD_EHS (0x1 << 5)
101 #define MD_EZI (0x1 << 6)
102 #define MD_ZI (0x1 << 7)
103 #define MD_EHD0 (0x1 << 8)
104 #define MD_EHD1 (0x1 << 8)
105 #define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
106 #define I2C0_STANDARD_FAST_MODE (1 << 3 | 1 << 11)
107 #define I2C0_FAST_MODE_PLUS (2 << 1 | 1 << 3 | 1 << 7 | 1 << 10 | 1 << 11)
108 #define FUNC0 0x0
109 #define FUNC1 0x1
110 #define FUNC2 0x2
111 #define FUNC3 0x3
112 #define FUNC4 0x4
113 #define FUNC5 0x5
114 #define FUNC6 0x6
115 #define FUNC7 0x7
117 #define PORT_OFFSET 0x80
118 #define PIN_OFFSET 0x04
121 #define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) (*(volatile int *) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
122
124 #define LPC_SCU_CLK(LPC_SCU_BASE, c) (*(volatile int *) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
125
135 STATIC INLINE void Chip_SCU_PinMuxSet(uint8_t port, uint8_t pin, uint16_t modefunc)
136 {
137 LPC_SCU->SFSP[port][pin] = modefunc;
138 }
139
150 STATIC INLINE void Chip_SCU_PinMux(uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
151 {
152 Chip_SCU_PinMuxSet(port, pin, (mode | (uint16_t) func));
153 }
154
161 STATIC INLINE void Chip_SCU_ClockPinMuxSet(uint8_t clknum, uint16_t modefunc)
162 {
163 LPC_SCU->SFSCLK[clknum] = (uint32_t) modefunc;
164 }
165
173 STATIC INLINE void Chip_SCU_ClockPinMux(uint8_t clknum, uint16_t mode, uint8_t func)
174 {
175 LPC_SCU->SFSCLK[clknum] = ((uint32_t) mode | (uint32_t) func);
176 }
177
185 STATIC INLINE void Chip_SCU_GPIOIntPinSel(uint8_t PortSel, uint8_t PortNum, uint8_t PinNum)
186 {
187 int32_t of = (PortSel & 3) << 3;
188 uint32_t val = (((PortNum & 0x7) << 5) | (PinNum & 0x1F)) << of;
189 LPC_SCU->PINTSEL[PortSel >> 2] = (LPC_SCU->PINTSEL[PortSel >> 2] & ~(0xFF << of)) | val;
190 }
191
199 STATIC INLINE void Chip_SCU_I2C0PinConfig(uint32_t I2C0Mode)
200 {
201 LPC_SCU->SFSI2C0 = I2C0Mode;
202 }
203
210 STATIC INLINE void Chip_SCU_ADC_Channel_Config(uint32_t ADC_ID, uint8_t channel)
211 {
212 LPC_SCU->ENAIO[ADC_ID] |= 1UL << channel;
213 }
214
219 STATIC INLINE void Chip_SCU_DAC_Analog_Config(void)
220 {
221 /*Enable analog function DAC on pin P4_4*/
222 LPC_SCU->ENAIO[2] |= 1;
223 }
224
231 STATIC INLINE void Chip_SCU_SetPinMuxing(const PINMUX_GRP_T *pinArray, uint32_t arrayLength)
232 {
233 uint32_t ix;
234 for (ix = 0; ix < arrayLength; ix++ ) {
235 Chip_SCU_PinMuxSet(pinArray[ix].pingrp, pinArray[ix].pinnum, pinArray[ix].modefunc);
236 }
237 }
238
243 #ifdef __cplusplus
244 }
245 #endif
246
247 #endif /* __SCU_18XX_43XX_H_ */