LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
i2s_18xx_43xx.h
Go to the documentation of this file.
1 /*
2  * @brief LPC18xx/43xx I2S driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licensor disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __I2S_18XX_43XX_H_
33 #define __I2S_18XX_43XX_H_
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
47 typedef enum {
52 
56 typedef struct {
57  __IO uint32_t DAO;
58  __IO uint32_t DAI;
59  __O uint32_t TXFIFO;
60  __I uint32_t RXFIFO;
61  __I uint32_t STATE;
62  __IO uint32_t DMA[I2S_DMA_REQUEST_CHANNEL_NUM];
63  __IO uint32_t IRQ;
64  __IO uint32_t TXRATE;
65  __IO uint32_t RXRATE;
66  __IO uint32_t TXBITRATE;
67  __IO uint32_t RXBITRATE;
68  __IO uint32_t TXMODE;
69  __IO uint32_t RXMODE;
70 } LPC_I2S_T;
71 
72 /*
73  * @brief I2S configuration parameter defines
74  */
75 /* I2S Wordwidth bit */
76 #define I2S_WORDWIDTH_8 (0UL << 0)
77 #define I2S_WORDWIDTH_16 (1UL << 0)
78 #define I2S_WORDWIDTH_32 (3UL << 0)
80 /* I2S Channel bit */
81 #define I2S_STEREO (0UL << 2)
82 #define I2S_MONO (1UL << 2)
84 /* I2S Master/Slave mode bit */
85 #define I2S_MASTER_MODE (0UL << 5)
86 #define I2S_SLAVE_MODE (1UL << 5)
88 /* I2S Stop bit */
89 #define I2S_STOP_ENABLE (0UL << 3)
90 #define I2S_STOP_DISABLE (1UL << 3)
92 /* I2S Reset bit */
93 #define I2S_RESET_ENABLE (1UL << 4)
94 #define I2S_RESET_DISABLE (0UL << 4)
96 /* I2S Mute bit */
97 #define I2S_MUTE_ENABLE (1UL << 15)
98 #define I2S_MUTE_DISABLE (0UL << 15)
100 /*
101  * @brief Macro defines for DAO-Digital Audio Output register
102  */
103 /* I2S wordwide - the number of bytes in data*/
104 #define I2S_DAO_WORDWIDTH_8 ((uint32_t) (0))
105 #define I2S_DAO_WORDWIDTH_16 ((uint32_t) (1))
106 #define I2S_DAO_WORDWIDTH_32 ((uint32_t) (3))
107 #define I2S_DAO_WORDWIDTH_MASK ((uint32_t) (3))
108 
109 /* I2S control mono or stereo format */
110 #define I2S_DAO_MONO ((uint32_t) (1 << 2))
112 /* I2S control stop mode */
113 #define I2S_DAO_STOP ((uint32_t) (1 << 3))
115 /* I2S control reset mode */
116 #define I2S_DAO_RESET ((uint32_t) (1 << 4))
118 /* I2S control master/slave mode */
119 #define I2S_DAO_SLAVE ((uint32_t) (1 << 5))
121 /* I2S word select half period minus one */
122 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6))
123 #define I2S_DAO_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
125 /* I2S control mute mode */
126 #define I2S_DAO_MUTE ((uint32_t) (1 << 15))
128 /*
129  * @brief Macro defines for DAI-Digital Audio Input register
130  */
131 /* I2S wordwide - the number of bytes in data*/
132 #define I2S_DAI_WORDWIDTH_8 ((uint32_t) (0))
133 #define I2S_DAI_WORDWIDTH_16 ((uint32_t) (1))
134 #define I2S_DAI_WORDWIDTH_32 ((uint32_t) (3))
135 #define I2S_DAI_WORDWIDTH_MASK ((uint32_t) (3))
137 /* I2S control mono or stereo format */
138 #define I2S_DAI_MONO ((uint32_t) (1 << 2))
140 /* I2S control stop mode */
141 #define I2S_DAI_STOP ((uint32_t) (1 << 3))
143 /* I2S control reset mode */
144 #define I2S_DAI_RESET ((uint32_t) (1 << 4))
146 /* I2S control master/slave mode */
147 #define I2S_DAI_SLAVE ((uint32_t) (1 << 5))
149 /* I2S word select half period minus one (9 bits)*/
150 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t) (((n) & 0x1FF) << 6))
151 #define I2S_DAI_WS_HALFPERIOD_MASK ((uint32_t) ((0x1FF) << 6))
153 /*
154  * @brief Macro defines for STAT register (Status Feedback register)
155  */
156 #define I2S_STATE_IRQ ((uint32_t) (1))
157 #define I2S_STATE_DMA1 ((uint32_t) (1 << 1))
158 #define I2S_STATE_DMA2 ((uint32_t) (1 << 2))
159 #define I2S_STATE_RX_LEVEL(n) ((uint32_t) ((n & 1F) << 8))
160 #define I2S_STATE_TX_LEVEL(n) ((uint32_t) ((n & 1F) << 16))
162 /*
163  * @brief Macro defines for DMA1 register (DMA1 Configuration register)
164  */
165 #define I2S_DMA1_RX_ENABLE ((uint32_t) (1))
166 #define I2S_DMA1_TX_ENABLE ((uint32_t) (1 << 1))
167 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
168 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
170 /*
171  * @brief Macro defines for DMA2 register (DMA2 Configuration register)
172  */
173 #define I2S_DMA2_RX_ENABLE ((uint32_t) (1))
174 #define I2S_DMA2_TX_ENABLE ((uint32_t) (1 << 1))
175 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 8))
176 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t) ((n & 0x1F) << 16))
178 /*
179  * @brief Macro defines for IRQ register (Interrupt Request Control register)
180  */
181 
182 #define I2S_IRQ_RX_ENABLE ((uint32_t) (1))
183 #define I2S_IRQ_TX_ENABLE ((uint32_t) (1 << 1))
184 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 8))
185 #define I2S_IRQ_RX_DEPTH_MASK ((uint32_t) ((0x0F) << 8))
186 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t) ((n & 0x0F) << 16))
187 #define I2S_IRQ_TX_DEPTH_MASK ((uint32_t) ((0x0F) << 16))
188 
189 /*
190  * @brief Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
191  */
192 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
193 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
194 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t) (n & 0xFF))
195 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t) ((n & 0xFF) << 8))
197 /*
198  * @brief Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
199  */
200 #define I2S_TXBITRATE(n) ((uint32_t) (n & 0x3F))
201 #define I2S_RXBITRATE(n) ((uint32_t) (n & 0x3F))
202 
203 /*
204  * @brief Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
205  */
206 #define I2S_TXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
207 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
208 #define I2S_TXMODE_MCENA ((uint32_t) (1 << 3))
209 #define I2S_RXMODE_CLKSEL(n) ((uint32_t) (n & 0x03))
210 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t) (1 << 2))
211 #define I2S_RXMODE_MCENA ((uint32_t) (1 << 3))
216 typedef struct {
217  uint32_t SampleRate;
218  uint8_t ChannelNumber;
219  uint8_t WordWidth;
221 
227 void Chip_I2S_Init(LPC_I2S_T *pI2S);
228 
235 void Chip_I2S_DeInit(LPC_I2S_T *pI2S);
236 
244 STATIC INLINE void Chip_I2S_Send(LPC_I2S_T *pI2S, uint32_t data)
245 {
246  pI2S->TXFIFO = data;
247 }
248 
256 {
257  return pI2S->RXFIFO;
258 }
259 
266 {
267  pI2S->DAO &= ~(I2S_DAO_RESET | I2S_DAO_STOP | I2S_DAO_MUTE);
268 }
269 
276 {
277  pI2S->DAI &= ~(I2S_DAI_RESET | I2S_DAI_STOP);
278 }
279 
286 {
287  pI2S->DAO |= I2S_DAO_STOP;
288 }
289 
296 {
297  pI2S->DAI |= I2S_DAI_STOP;
298 }
299 
307 {
308  pI2S->DAO |= I2S_DAO_MUTE;
309 }
310 
317 {
318  pI2S->DAO &= ~I2S_DAO_MUTE;
319 }
320 
328 {
329  pI2S->DAO &= ~I2S_DAO_MUTE;
330  pI2S->DAO |= I2S_DAO_STOP | I2S_DAO_RESET;
331 }
332 
340 {
341  pI2S->DAI |= I2S_DAI_STOP | I2S_DAI_RESET;
342 }
343 
353 {
354  pI2S->DAI |= I2S_SLAVE_MODE;
355 }
356 
366 {
367  pI2S->DAO |= I2S_SLAVE_MODE;
368 }
369 
383  uint32_t clksel,
384  uint32_t fpin,
385  uint32_t mcena)
386 {
387  pI2S->TXMODE = clksel | fpin | mcena;
388 }
389 
403  uint32_t clksel,
404  uint32_t fpin,
405  uint32_t mcena)
406 {
407  pI2S->RXMODE = clksel | fpin | mcena;
408 }
409 
416 {
417  return (pI2S->STATE >> 16) & 0xF;
418 }
419 
426 {
427  return (pI2S->STATE >> 8) & 0xF;
428 }
429 
438 STATIC INLINE void Chip_I2S_SetTxBitRate(LPC_I2S_T *pI2S, uint32_t div)
439 {
440  pI2S->TXBITRATE = div;
441 }
442 
451 STATIC INLINE void Chip_I2S_SetRxBitRate(LPC_I2S_T *pI2S, uint32_t div)
452 {
453  pI2S->RXBITRATE = div;
454 }
455 
470 STATIC INLINE void Chip_I2S_SetTxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv)
471 {
472  pI2S->TXRATE = yDiv | (xDiv << 8);
473 }
474 
489 STATIC INLINE void Chip_I2S_SetRxXYDivider(LPC_I2S_T *pI2S, uint8_t xDiv, uint8_t yDiv)
490 {
491  pI2S->RXRATE = yDiv | (xDiv << 8);
492 }
493 
501 
509 
517 void Chip_I2S_Int_TxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth);
518 
526 void Chip_I2S_Int_RxCmd(LPC_I2S_T *pI2S, FunctionalState newState, uint8_t depth);
527 
538 void Chip_I2S_DMA_TxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth);
539 
550 void Chip_I2S_DMA_RxCmd(LPC_I2S_T *pI2S, I2S_DMA_CHANNEL_T dmaNum, FunctionalState newState, uint8_t depth);
551 
556 #ifdef __cplusplus
557 }
558 #endif
559 
560 #endif /* __I2S_18XX_43XX_H_ */