LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_board/board_common/lpc_nandflash_k9f1g.h Source File

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lpc_nandflash_k9f1g.h
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1 /*
2 * @brief K9F1G NAND Flash definitions
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __LPC_K9F1G_NANDFLASH_H_
33 #define __LPC_K9F1G_NANDFLASH_H_
34
35 #include "board.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
46 #define KF91G_NANDFLASH
47
48 /* Page size */
49 #define K9F1G_PAGE_SIZE (2 << 10) /* 2K bytes */
50 /* Spare start address */
51 #define K9F1G_SPARE_START_ADDR ( K9F1G_PAGE_SIZE) /* Spare start address */
52 /* Spare size */
53 #define K9F1G_SPARE_SIZE (64)
54 /* Pages per block */
55 #define K9F1G_PAGES_PER_BLOCK (64)
56 /* The number of blocks */
57 #define K9F1G_BLOCK_COUNT (1024)
58
59 /*
60 * @brief K9F1G commands
61 */
62 #define K9F1G_READ_1 0x00
63 #define K9F1G_READ_2 0x30
64 #define K9F1G_READ_ID 0x90
65 #define K9F1G_RESET 0xFF
66 #define K9F1G_PAGE_PROGRAM_1 0x80
67 #define K9F1G_PAGE_PROGRAM_2 0x10
68 #define K9F1G_BLOCK_ERASE_1 0x60
69 #define K9F1G_BLOCK_ERASE_2 0xD0
70 #define K9F1G_READ_STATUS 0x70
71
72 /*
73 * @brief K9F1G ID structures
74 */
75 typedef struct {
76 uint8_t MarkerCode;
77 uint8_t DeviceCode;
78 struct {
79 uint8_t InternalChipNum : 2;
80 uint8_t CellType : 2;
81 uint8_t MaxProgramPageNum : 2;
82 uint8_t InterProgSupport : 1;
83 uint8_t CacheProgSupport : 1;
84 } b3;
85
86 struct {
87 uint8_t PageSize : 2;
88 uint8_t BlockSize : 2;
89 uint8_t RedundantSize : 1;
90 uint8_t Organization : 1;
91 uint8_t SeriaAccessMin : 2;
92 } b4;
93
94 struct {
95 uint8_t Reserved0 : 2;
96 uint8_t PlaneNum : 2;
97 uint8_t PlaneSize : 3;
98 uint8_t Reserved1 : 1;
99 } b5;
100
101 } K9F1G_ID_T;
102
103 /*
104 * @brief NAND FLASH status
105 */
106 #define NANDFLASH_STATUS_PAGE_PROG_FAIL (1 << 0)
107 #define NANDFLASH_STATUS_BLOCK_ERASE_FAIL (1 << 0)
108 #define NANDFLASH_STATUS_DEV_READY (1 << 6)
109 #define NANDFLASH_STATUS_READ_WRITE_NPROTECTED (1 << 7)
110
111 /*
112 * @brief Timming defitnitions (in ns)
113 */
115 #define NANDFLASH_PROG_TIME (700 * 1000)
116
117 #define NANDFLASH_BLOCK_ERASE_TIME (3 * 1000 * 1000)
118
119 #define NANDFLASH_READ_TIME (25 * 1000)
120
124 #ifdef __cplusplus
125 }
126 #endif
127
128 #endif /* __LPC_K9F1G_NANDFLASH_H_ */