LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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chip_18xx_43xx
sysinit_18xx_43xx.c
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/*
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* @brief LPC18xx/LPC43xx Chip specific SystemInit
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "
chip.h
"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/* Structure for initial base clock states */
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struct
CLK_BASE_STATES
{
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CHIP_CGU_BASE_CLK_T
clk
;
/* Base clock */
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CHIP_CGU_CLKIN_T
clkin
;
/* Base clock source, see UM for allowable souorces per base clock */
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bool
autoblock_enab
;
/* Set to true to enable autoblocking on frequency change */
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bool
powerdn
;
/* Set to true if the base clock is initially powered down */
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};
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static
const
struct
CLK_BASE_STATES
InitClkStates
[] = {
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{
CLK_BASE_SAFE
,
CLKIN_IRC
,
true
,
false
},
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{
CLK_BASE_APB1
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_APB3
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_USB0
,
CLKIN_USBPLL
,
true
,
true
},
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#if defined(CHIP_LPC43XX)
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{CLK_BASE_PERIPH,
CLKIN_MAINPLL
,
true
,
false
},
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{CLK_BASE_SPI,
CLKIN_MAINPLL
,
true
,
false
},
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{CLK_BASE_ADCHS,
CLKIN_MAINPLL
,
true
,
true
},
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#endif
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{
CLK_BASE_SDIO
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_SSP0
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_SSP1
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_UART0
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_UART1
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_UART2
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_UART3
,
CLKIN_MAINPLL
,
true
,
false
},
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{
CLK_BASE_OUT
,
CLKINPUT_PD
,
true
,
false
},
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{
CLK_BASE_APLL
,
CLKINPUT_PD
,
true
,
false
},
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{
CLK_BASE_CGU_OUT0
,
CLKINPUT_PD
,
true
,
false
},
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{
CLK_BASE_CGU_OUT1
,
CLKINPUT_PD
,
true
,
false
},
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};
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Setup Chip Core clock */
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void
Chip_SetupCoreClock
(
CHIP_CGU_CLKIN_T
clkin
, uint32_t core_freq,
bool
setbase)
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{
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int
i;
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volatile
uint32_t
delay
= 500;
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uint32_t direct = 0;
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PLL_PARAM_T
ppll;
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if
(clkin ==
CLKIN_CRYSTAL
) {
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/* Switch main system clocking to crystal */
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Chip_Clock_EnableCrystal
();
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}
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Chip_Clock_SetBaseClock
(
CLK_BASE_MX
, clkin,
true
,
false
);
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Chip_Clock_DisableMainPLL
();
/* Disable PLL */
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/* Calculate the PLL Parameters */
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ppll.
srcin
=
clkin
;
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Chip_Clock_CalcMainPLLValue
(core_freq, &ppll);
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if
(core_freq > 110000000UL) {
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if
(!(ppll.
ctrl
& (1 << 7)) || ppll.
psel
) {
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PLL_PARAM_T
lpll;
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/* Calculate the PLL Parameters */
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lpll.
srcin
=
clkin
;
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Chip_Clock_CalcMainPLLValue
(110000000UL, &lpll);
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Chip_Clock_SetupMainPLL
(&lpll);
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/* Wait for the PLL to lock */
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while
(!
Chip_Clock_MainPLLLocked
()) {}
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Chip_Clock_SetBaseClock
(
CLK_BASE_MX
,
CLKIN_MAINPLL
,
true
,
false
);
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while
(delay --){}
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delay = 500;
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}
else
{
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direct = 1;
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ppll.
ctrl
&= ~(1 << 7);
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}
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}
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/* Setup and start the PLL */
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Chip_Clock_SetupMainPLL
(&ppll);
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/* Wait for the PLL to lock */
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while
(!
Chip_Clock_MainPLLLocked
()) {}
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/* Set core clock base as PLL1 */
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Chip_Clock_SetBaseClock
(
CLK_BASE_MX
,
CLKIN_MAINPLL
,
true
,
false
);
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while
(delay --){}
/* Wait for approx 50 uSec */
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if
(direct) {
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delay = 500;
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ppll.
ctrl
|= 1 << 7;
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Chip_Clock_SetupMainPLL
(&ppll);
/* Set DIRECT to operate at full frequency */
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while
(delay --){}
/* Wait for approx 50 uSec */
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}
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if
(setbase) {
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/* Setup system base clocks and initial states. This won't enable and
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disable individual clocks, but sets up the base clock sources for
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each individual peripheral clock. */
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for
(i = 0; i < (
sizeof
(
InitClkStates
) /
sizeof
(InitClkStates[0])); i++) {
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Chip_Clock_SetBaseClock
(InitClkStates[i].
clk
, InitClkStates[i].clkin,
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InitClkStates[i].
autoblock_enab
, InitClkStates[i].
powerdn
);
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}
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}
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}
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/* Setup system clocking */
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void
Chip_SetupXtalClocking
(
void
)
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{
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Chip_SetupCoreClock
(
CLKIN_CRYSTAL
,
MAX_CLOCK_FREQ
,
true
);
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}
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/* Set up and initialize hardware prior to call to main */
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void
Chip_SetupIrcClocking
(
void
)
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{
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Chip_SetupCoreClock
(
CLKIN_IRC
,
MAX_CLOCK_FREQ
,
true
);
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}
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/* Set up and initialize hardware prior to call to main */
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void
Chip_SystemInit
(
void
)
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{
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/* Initial internal clocking */
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Chip_SetupIrcClocking
();
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}
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