48 #if defined(CHIP_LPC43XX)
49 {CLK_PERIPH_BUS, CLK_PERIPH_SGPIO, CLK_BASE_PERIPH},
53 #if defined(CHIP_LPC43XX)
54 {CLK_SPI, CLK_SPI, CLK_BASE_SPI},
55 {CLK_ADCHS, CLK_ADCHS, CLK_BASE_ADCHS},
68 #define CRYSTAL_32K_FREQ_IN (32 * 1024)
80 __STATIC_INLINE uint32_t
ABS(
int val)
94 if (ppll->
ctrl & (1 << 7)) {
95 ppll->
ctrl &= ~(1 << 6);
97 for (n = 1; n <= 4; n++) {
98 for (p = 0; p < 4; p ++) {
99 for (m = 1; m <= 256; m++) {
101 if (ppll->
ctrl & (1 << 6)) {
102 fcco = ((m << (p + 1)) * ppll->
fin) / n;
104 fcco = (m * ppll->
fin) / n;
108 if (ppll->
ctrl & (1 << 7)) {
111 fout = fcco >> (p + 1);
114 if (
ABS(freq - fout) < prev) {
120 prev =
ABS(freq - fout);
133 pll[0].
ctrl |= (1 << 7);
137 if (pll[0].fout == freq) {
141 diff[0] =
ABS(freq - pll[0].fout);
144 pll[2].
ctrl = (1 << 6);
148 if (pll[2].fout == freq) {
153 diff[2] =
ABS(freq - pll[2].fout);
155 pll[1].
ctrl = (1 << 6);
159 if (pll[1].fout == freq) {
163 diff[1] =
ABS(freq - pll[1].fout);
166 if (diff[0] <= diff[1]) {
167 if (diff[0] <= diff[2]) {
173 if (diff[1] <= diff[2]) {
184 uint32_t TestHz = TestMult * InputHz;
186 if ((TestHz < MinHz) || (TestHz >
MAX_CLOCK_FREQ) || (TestHz > MaxHz)) {
210 while ((baseclk ==
CLK_BASE_NONE) && (periph_to_base[i].clkbase != baseclk)) {
211 if ((clk >= periph_to_base[i].clkstart) && (clk <= periph_to_base[i].clkend)) {
212 baseclk = periph_to_base[i].
clkbase;
229 volatile uint32_t
delay = 1000;
231 uint32_t OldCrystalConfig =
LPC_CGU->XTAL_OSC_CTRL;
234 OldCrystalConfig &= (~2);
235 if (OldCrystalConfig !=
LPC_CGU->XTAL_OSC_CTRL) {
236 LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
240 OldCrystalConfig &= (~1);
242 OldCrystalConfig |= 4;
245 LPC_CGU->XTAL_OSC_CTRL = OldCrystalConfig;
266 if (freq < PLL_MIN_CCO_FREQ || ppll->msel * ppll->
fin != freq) {
274 if (ppll->
msel == 0) {
298 uint32_t Mult, LastMult, MultEnd;
299 uint32_t freqout, freqout2;
301 if (DesiredHz != 0xFFFFFFFF) {
303 Mult = DesiredHz / freqin;
310 if (freqout && !freqout2) {
314 if (!freqout && freqout2) {
318 if (freqout && freqout2) {
319 if ((DesiredHz - freqout) > (freqout2 - DesiredHz)) {
331 Mult = MinHz / freqin;
332 MultEnd = MaxHz / freqin;
341 if (Mult >= MultEnd) {
357 volatile uint32_t
delay = 250;
359 uint32_t msel = 0, nsel = 0, psel = 0, pval = 1;
360 uint32_t PLLReg =
LPC_CGU->PLL1_CTRL;
365 PLLReg &= ~(0x1F << 24);
366 PLLReg |= Input << 24;
369 PLLReg &= ~((1 << 6) |
372 (0x03 << 8) | (0xFF << 16) | (0x03 << 12));
374 if (freq < 156000000) {
376 while ((2 * (pval) * freq) < 156000000) {
381 PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 6);
383 else if (freq < 320000000) {
384 PLLReg |= (msel << 16) | (nsel << 12) | (psel << 8) | (1 << 7) | (1 << 6);
390 LPC_CGU->PLL1_CTRL = PLLReg & ~(1 << 0);
401 uint32_t PLLReg =
LPC_CGU->PLL1_CTRL;
403 uint32_t msel, nsel, psel, direct, fbsel;
405 const uint8_t ptab[] = {1, 2, 4, 8};
408 if (!(
LPC_CGU->PLL1_STAT & 1)) {
412 msel = (PLLReg >> 16) & 0xFF;
413 nsel = (PLLReg >> 12) & 0x3;
414 psel = (PLLReg >> 8) & 0x3;
415 direct = (PLLReg >> 7) & 0x1;
416 fbsel = (PLLReg >> 6) & 0x1;
422 if (direct || fbsel) {
423 return m * (freq / n);
426 return (m / (2 * p)) * (freq / n);
432 uint32_t reg =
LPC_CGU->IDIV_CTRL[Divider];
441 LPC_CGU->IDIV_CTRL[Divider] = reg | (1 << 11) | (Input << 24) | (Divisor << 2);
444 LPC_CGU->IDIV_CTRL[Divider] = reg | 1;
451 uint32_t reg =
LPC_CGU->IDIV_CTRL[Divider];
481 if ((
LPC_CREG->CREG6 & 0x07) != 0x4) {
488 if ((
LPC_CREG->CREG6 & 0x07) != 0x4) {
555 uint32_t reg =
LPC_CGU->BASE_CLK[BaseClock];
560 reg &= ~((0x1F << 24) | 1 | (1 << 11));
570 reg |= (Input << 24);
572 LPC_CGU->BASE_CLK[BaseClock] = reg;
576 LPC_CGU->BASE_CLK[BaseClock] = reg | 1;
584 uint32_t reg =
LPC_CGU->BASE_CLK[BaseClock];
590 *autoblocken = (reg & (1 << 11)) ?
true :
false;
591 *powerdn = (reg & (1 << 0)) ?
true :
false;
604 LPC_CGU->BASE_CLK[BaseClock] &= ~1;
612 LPC_CGU->BASE_CLK[BaseClock] |= 1;
622 enabled = (bool) ((
LPC_CGU->BASE_CLK[BaseClock] & 1) == 0);
640 reg =
LPC_CGU->BASE_CLK[BaseClock];
692 LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
693 LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
735 uint32_t reg, div, rate;
754 if (((reg >> 5) & 0x7) == 0) {
783 if ((EMCDiv == 1) && (
LPC_CREG->CREG6 & (1 << 16))) {
793 uint32_t reg = pPLLSetup->
ctrl | (Input << 24);
796 LPC_CGU->PLL[pllnum].PLL_CTRL = reg;
810 LPC_CGU->PLL[pllnum].PLL_CTRL &= ~1;
816 LPC_CGU->PLL[pllnum].PLL_CTRL |= 1;
822 return LPC_CGU->PLL[pllnum].PLL_STAT;