LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
Macros | Typedefs | Enumerations
cmsis_43xx_m0app.h File Reference
#include "core_cm0.h"

Go to the source code of this file.

Macros

#define __MPU_PRESENT   0
 
#define __NVIC_PRIO_BITS   2
 
#define __Vendor_SysTickConfig   0
 
#define __FPU_PRESENT   0
 

Typedefs

typedef LPC43XX_M0_IRQn_Type IRQn_Type
 

Enumerations

enum  LPC43XX_M0_IRQn_Type {
  Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, RTC_IRQn = 0,
  M4_IRQn = 1, DMA_IRQn = 2, RESERVED1_IRQn = 3, FLASHEEPROM_IRQn = 4,
  ATIMER_IRQn = 4, ETHERNET_IRQn = 5, SDIO_IRQn = 6, LCD_IRQn = 7,
  USB0_IRQn = 8, USB1_IRQn = 9, SCT_IRQn = 10, RITIMER_IRQn = 11,
  WWDT_IRQn = 11, TIMER0_IRQn = 12, GINT1_IRQn = 13, PIN_INT4_IRQn = 14,
  TIMER3_IRQn = 15, MCPWM_IRQn = 16, ADC0_IRQn = 17, I2C0_IRQn = 18,
  I2C1_IRQn = 18, SGPIO_INT_IRQn = 19, SPI_INT_IRQn = 20, DAC_IRQn = 20,
  ADC1_IRQn = 21, SSP0_IRQn = 22, SSP1_IRQn = 22, EVENTROUTER_IRQn = 23,
  USART0_IRQn = 24, UART1_IRQn = 25, USART2_IRQn = 26, C_CAN1_IRQn = 26,
  USART3_IRQn = 27, I2S0_IRQn = 28, I2S1_IRQn = 28, QEI_IRQn = 28,
  C_CAN0_IRQn = 29, ADCHS_IRQn = 30, M0SUB_IRQn = 31, Reset_IRQn = -15,
  NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, DAC_IRQn = 0, M4_IRQn = 1,
  DMA_IRQn = 2, RESERVED1_IRQn = 3, SGPIO_INPUT_IRQn = 4, SGPIO_MATCH_IRQn = 5,
  SGPIO_SHIFT_IRQn = 6, SGPIO_POS_IRQn = 7, USB0_IRQn = 8, USB1_IRQn = 9,
  SCT_IRQn = 10, RITIMER_IRQn = 11, GINT1_IRQn = 12, TIMER1_IRQn = 13,
  TIMER2_IRQn = 14, PIN_INT5_IRQn = 15, MCPWM_IRQn = 16, ADC0_IRQn = 17,
  I2C0_IRQn = 18, I2C1_IRQn = 19, SPI_INT_IRQn = 20, ADC1_IRQn = 21,
  SSP0_IRQn = 22, SSP1_IRQn = 22, EVENTROUTER_IRQn = 23, USART0_IRQn = 24,
  UART1_IRQn = 25, USART2_IRQn = 26, C_CAN1_IRQn = 26, USART3_IRQn = 27,
  I2S0_IRQn = 28, I2S1_IRQn = 28, C_CAN0_IRQn = 29, ADCHS_IRQn = 30,
  M0APP_IRQn = 31
}