32 #ifndef __SDIF_18XX_43XX_H_
33 #define __SDIF_18XX_43XX_H_
91 #define MCI_DMADES0_OWN (1UL << 31)
92 #define MCI_DMADES0_CES (1 << 30)
93 #define MCI_DMADES0_ER (1 << 5)
94 #define MCI_DMADES0_CH (1 << 4)
95 #define MCI_DMADES0_FS (1 << 3)
96 #define MCI_DMADES0_LD (1 << 2)
97 #define MCI_DMADES0_DIC (1 << 1)
101 #define MCI_DMADES1_BS1(x) (x)
102 #define MCI_DMADES1_BS2(x) ((x) << 13)
103 #define MCI_DMADES1_MAXTR 4096
107 #define MCI_CTRL_USE_INT_DMAC (1 << 25)
108 #define MCI_CTRL_CARDV_MASK (0x7 << 16)
109 #define MCI_CTRL_CEATA_INT_EN (1 << 11)
110 #define MCI_CTRL_SEND_AS_CCSD (1 << 10)
111 #define MCI_CTRL_SEND_CCSD (1 << 9)
112 #define MCI_CTRL_ABRT_READ_DATA (1 << 8)
113 #define MCI_CTRL_SEND_IRQ_RESP (1 << 7)
114 #define MCI_CTRL_READ_WAIT (1 << 6)
115 #define MCI_CTRL_INT_ENABLE (1 << 4)
116 #define MCI_CTRL_DMA_RESET (1 << 2)
117 #define MCI_CTRL_FIFO_RESET (1 << 1)
118 #define MCI_CTRL_RESET (1 << 0)
122 #define MCI_POWER_ENABLE 0x1
126 #define MCI_CLOCK_DIVIDER(dn, d2) ((d2) << ((dn) * 8))
130 #define MCI_CLKSRC_CLKDIV0 0
131 #define MCI_CLKSRC_CLKDIV1 1
132 #define MCI_CLKSRC_CLKDIV2 2
133 #define MCI_CLKSRC_CLKDIV3 3
134 #define MCI_CLK_SOURCE(clksrc) (clksrc)
138 #define MCI_CLKEN_LOW_PWR (1 << 16)
139 #define MCI_CLKEN_ENABLE (1 << 0)
143 #define MCI_TMOUT_DATA(clks) ((clks) << 8)
144 #define MCI_TMOUT_DATA_MSK 0xFFFFFF00
145 #define MCI_TMOUT_RESP(clks) ((clks) & 0xFF)
146 #define MCI_TMOUT_RESP_MSK 0xFF
150 #define MCI_CTYPE_8BIT (1 << 16)
151 #define MCI_CTYPE_4BIT (1 << 0)
155 #define MCI_INT_SDIO (1 << 16)
156 #define MCI_INT_EBE (1 << 15)
157 #define MCI_INT_ACD (1 << 14)
158 #define MCI_INT_SBE (1 << 13)
159 #define MCI_INT_HLE (1 << 12)
160 #define MCI_INT_FRUN (1 << 11)
161 #define MCI_INT_HTO (1 << 10)
162 #define MCI_INT_DTO (1 << 9)
163 #define MCI_INT_RTO (1 << 8)
164 #define MCI_INT_DCRC (1 << 7)
165 #define MCI_INT_RCRC (1 << 6)
166 #define MCI_INT_RXDR (1 << 5)
167 #define MCI_INT_TXDR (1 << 4)
168 #define MCI_INT_DATA_OVER (1 << 3)
169 #define MCI_INT_CMD_DONE (1 << 2)
170 #define MCI_INT_RESP_ERR (1 << 1)
171 #define MCI_INT_CD (1 << 0)
175 #define MCI_CMD_START (1UL << 31)
176 #define MCI_CMD_VOLT_SWITCH (1 << 28)
177 #define MCI_CMD_BOOT_MODE (1 << 27)
178 #define MCI_CMD_DISABLE_BOOT (1 << 26)
179 #define MCI_CMD_EXPECT_BOOT_ACK (1 << 25)
180 #define MCI_CMD_ENABLE_BOOT (1 << 24)
181 #define MCI_CMD_CCS_EXP (1 << 23)
182 #define MCI_CMD_CEATA_RD (1 << 22)
183 #define MCI_CMD_UPD_CLK (1 << 21)
184 #define MCI_CMD_INIT (1 << 15)
185 #define MCI_CMD_STOP (1 << 14)
186 #define MCI_CMD_PRV_DAT_WAIT (1 << 13)
187 #define MCI_CMD_SEND_STOP (1 << 12)
188 #define MCI_CMD_STRM_MODE (1 << 11)
189 #define MCI_CMD_DAT_WR (1 << 10)
190 #define MCI_CMD_DAT_EXP (1 << 9)
191 #define MCI_CMD_RESP_CRC (1 << 8)
192 #define MCI_CMD_RESP_LONG (1 << 7)
193 #define MCI_CMD_RESP_EXP (1 << 6)
194 #define MCI_CMD_INDX(n) ((n) & 0x1F)
198 #define MCI_STS_GET_FCNT(x) (((x) >> 17) & 0x1FF)
202 #define MCI_FIFOTH_TX_WM(x) ((x) & 0xFFF)
203 #define MCI_FIFOTH_RX_WM(x) (((x) & 0xFFF) << 16)
204 #define MCI_FIFOTH_DMA_MTS_1 (0UL << 28)
205 #define MCI_FIFOTH_DMA_MTS_4 (1UL << 28)
206 #define MCI_FIFOTH_DMA_MTS_8 (2UL << 28)
207 #define MCI_FIFOTH_DMA_MTS_16 (3UL << 28)
208 #define MCI_FIFOTH_DMA_MTS_32 (4UL << 28)
209 #define MCI_FIFOTH_DMA_MTS_64 (5UL << 28)
210 #define MCI_FIFOTH_DMA_MTS_128 (6UL << 28)
211 #define MCI_FIFOTH_DMA_MTS_256 (7UL << 28)
215 #define MCI_BMOD_PBL1 (0 << 8)
216 #define MCI_BMOD_PBL4 (1 << 8)
217 #define MCI_BMOD_PBL8 (2 << 8)
218 #define MCI_BMOD_PBL16 (3 << 8)
219 #define MCI_BMOD_PBL32 (4 << 8)
220 #define MCI_BMOD_PBL64 (5 << 8)
221 #define MCI_BMOD_PBL128 (6 << 8)
222 #define MCI_BMOD_PBL256 (7 << 8)
223 #define MCI_BMOD_DE (1 << 7)
224 #define MCI_BMOD_DSL(len) ((len) << 2)
225 #define MCI_BMOD_FB (1 << 1)
226 #define MCI_BMOD_SWR (1 << 0)
230 #define SD_FIFO_SZ 32
233 typedef uint32_t (*MCI_IRQ_CB_FUNC_T)(uint32_t);
252 typedef struct _sdif_device {
262 #define US_TIMEOUT 1000000
263 #define MS_ACQUIRE_DELAY (10)
264 #define INIT_OP_RETRIES 50
265 #define SET_OP_RETRIES 1000
266 #define SDIO_BUS_WIDTH 4
267 #define SD_MMC_ENUM_CLOCK 400000
268 #define MMC_MAX_CLOCK 20000000
269 #define MMC_LOW_BUS_MAX_CLOCK 26000000
270 #define MMC_HIGH_BUS_MAX_CLOCK 52000000
271 #define SD_MAX_CLOCK 25000000
279 STATIC INLINE void Chip_SDIF_SetBlkSize(LPC_SDMMC_T *pSDMMC, uint32_t bytes)
281 pSDMMC->BLKSIZ = bytes;
323 return (pSDMMC->
WRTPRT & 1);
356 pSDMMC->
CTYPE = ctype;
399 pSDMMC->
BLKSIZ = blk_size;
400 pSDMMC->
BYTCNT = blk_size;