32 #ifndef __EMC_18XX_43XX_H_
33 #define __EMC_18XX_43XX_H_
53 __I uint32_t RESERVED0[5];
69 __I uint32_t RESERVED2[9];
71 __I uint32_t RESERVED3[31];
74 __I uint32_t RESERVED4[6];
77 __I uint32_t RESERVED5[6];
80 __I uint32_t RESERVED6[6];
83 __I uint32_t RESERVED7[38];
120 #define EMC_ADDRESS_DYCS0 (0x28000000)
121 #define EMC_ADDRESS_DYCS1 (0x30000000)
122 #define EMC_ADDRESS_DYCS2 (0x60000000)
123 #define EMC_ADDRESS_DYCS3 (0x70000000)
128 #define EMC_ADDRESS_CS0 (0x1C000000)
129 #define EMC_ADDRESS_CS1 (0x1D000000)
130 #define EMC_ADDRESS_CS2 (0x1E000000)
131 #define EMC_ADDRESS_CS3 (0x1F000000)
137 #define EMC_SUPPORT_ONLY_PL172
139 #define EMC_CONFIG_ENDIAN_LITTLE (0)
140 #define EMC_CONFIG_ENDIAN_BIG (1)
142 #define EMC_CONFIG_BUFFER_ENABLE (1 << 19)
143 #define EMC_CONFIG_WRITE_PROTECT (1 << 20)
146 #define EMC_DYN_CONFIG_MD_BIT (3)
147 #define EMC_DYN_CONFIG_MD_SDRAM (0 << EMC_DYN_CONFIG_MD_BIT)
148 #define EMC_DYN_CONFIG_MD_LPSDRAM (1 << EMC_DYN_CONFIG_MD_BIT)
150 #define EMC_DYN_CONFIG_LPSDRAM_BIT (12)
151 #define EMC_DYN_CONFIG_LPSDRAM (1 << EMC_DYN_CONFIG_LPSDRAM_BIT)
153 #define EMC_DYN_CONFIG_DEV_SIZE_BIT (9)
154 #define EMC_DYN_CONFIG_DEV_SIZE_16Mb (0x00 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
155 #define EMC_DYN_CONFIG_DEV_SIZE_64Mb (0x01 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
156 #define EMC_DYN_CONFIG_DEV_SIZE_128Mb (0x02 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
157 #define EMC_DYN_CONFIG_DEV_SIZE_256Mb (0x03 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
158 #define EMC_DYN_CONFIG_DEV_SIZE_512Mb (0x04 << EMC_DYN_CONFIG_DEV_SIZE_BIT)
160 #define EMC_DYN_CONFIG_DEV_BUS_BIT (7)
161 #define EMC_DYN_CONFIG_DEV_BUS_8 (0x00 << EMC_DYN_CONFIG_DEV_BUS_BIT)
162 #define EMC_DYN_CONFIG_DEV_BUS_16 (0x01 << EMC_DYN_CONFIG_DEV_BUS_BIT)
163 #define EMC_DYN_CONFIG_DEV_BUS_32 (0x02 << EMC_DYN_CONFIG_DEV_BUS_BIT)
165 #define EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT (14)
166 #define EMC_DYN_CONFIG_DATA_BUS_16 (0x00 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
167 #define EMC_DYN_CONFIG_DATA_BUS_32 (0x01 << EMC_DYN_CONFIG_DATA_BUS_WIDTH_BIT)
170 #define EMC_DYN_CONFIG_2Mx8_2BANKS_11ROWS_9COLS ((0x0 << 9) | (0x0 << 7))
171 #define EMC_DYN_CONFIG_1Mx16_2BANKS_11ROWS_8COLS ((0x0 << 9) | (0x1 << 7))
172 #define EMC_DYN_CONFIG_8Mx8_4BANKS_12ROWS_9COLS ((0x1 << 9) | (0x0 << 7))
173 #define EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS ((0x1 << 9) | (0x1 << 7))
174 #define EMC_DYN_CONFIG_2Mx32_4BANKS_11ROWS_8COLS ((0x1 << 9) | (0x2 << 7))
175 #define EMC_DYN_CONFIG_16Mx8_4BANKS_12ROWS_10COLS ((0x2 << 9) | (0x0 << 7))
176 #define EMC_DYN_CONFIG_8Mx16_4BANKS_12ROWS_9COLS ((0x2 << 9) | (0x1 << 7))
177 #define EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS ((0x2 << 9) | (0x2 << 7))
178 #define EMC_DYN_CONFIG_32Mx8_4BANKS_13ROWS_10COLS ((0x3 << 9) | (0x0 << 7))
179 #define EMC_DYN_CONFIG_16Mx16_4BANKS_13ROWS_9COLS ((0x3 << 9) | (0x1 << 7))
180 #define EMC_DYN_CONFIG_8Mx32_4BANKS_13ROWS_8COLS ((0x3 << 9) | (0x2 << 7))
181 #define EMC_DYN_CONFIG_64Mx8_4BANKS_13ROWS_11COLS ((0x4 << 9) | (0x0 << 7))
182 #define EMC_DYN_CONFIG_32Mx16_4BANKS_13ROWS_10COLS ((0x4 << 9) | (0x1 << 7))
185 #define EMC_DYN_MODE_BURST_LEN_BIT (0)
186 #define EMC_DYN_MODE_BURST_LEN_1 (0)
187 #define EMC_DYN_MODE_BURST_LEN_2 (1)
188 #define EMC_DYN_MODE_BURST_LEN_4 (2)
189 #define EMC_DYN_MODE_BURST_LEN_8 (3)
190 #define EMC_DYN_MODE_BURST_LEN_FULL (7)
192 #define EMC_DYN_MODE_BURST_TYPE_BIT (3)
193 #define EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL (0 << EMC_DYN_MODE_BURST_TYPE_BIT)
194 #define EMC_DYN_MODE_BURST_TYPE_INTERLEAVE (1 << EMC_DYN_MODE_BURST_TYPE_BIT)
197 #define EMC_DYN_MODE_CAS_BIT (4)
198 #define EMC_DYN_MODE_CAS_1 (1 << EMC_DYN_MODE_CAS_BIT)
199 #define EMC_DYN_MODE_CAS_2 (2 << EMC_DYN_MODE_CAS_BIT)
200 #define EMC_DYN_MODE_CAS_3 (3 << EMC_DYN_MODE_CAS_BIT)
203 #define EMC_DYN_MODE_OPMODE_BIT (7)
204 #define EMC_DYN_MODE_OPMODE_STANDARD (0 << EMC_DYN_MODE_OPMODE_BIT)
207 #define EMC_DYN_MODE_WBMODE_BIT (9)
208 #define EMC_DYN_MODE_WBMODE_PROGRAMMED (0 << EMC_DYN_MODE_WBMODE_BIT)
209 #define EMC_DYN_MODE_WBMODE_SINGLE_LOC (1 << EMC_DYN_MODE_WBMODE_BIT)
212 #define EMC_DYN_CONTROL_ENABLE (0x03)
215 #define EMC_STATIC_CONFIG_MEM_WIDTH_8 (0)
216 #define EMC_STATIC_CONFIG_MEM_WIDTH_16 (1)
217 #define EMC_STATIC_CONFIG_MEM_WIDTH_32 (2)
219 #define EMC_STATIC_CONFIG_PAGE_MODE_BIT (3)
220 #define EMC_STATIC_CONFIG_PAGE_MODE_ENABLE (1 << EMC_STATIC_CONFIG_PAGE_MODE_BIT)
222 #define EMC_STATIC_CONFIG_CS_POL_BIT (6)
223 #define EMC_STATIC_CONFIG_CS_POL_ACTIVE_HIGH (1 << EMC_STATIC_CONFIG_CS_POL_BIT)
224 #define EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW (0 << EMC_STATIC_CONFIG_CS_POL_BIT)
226 #define EMC_STATIC_CONFIG_BLS_BIT (7)
227 #define EMC_STATIC_CONFIG_BLS_HIGH (1 << EMC_STATIC_CONFIG_BLS_BIT)
228 #define EMC_STATIC_CONFIG_BLS_LOW (0 << EMC_STATIC_CONFIG_BLS_BIT)
230 #define EMC_STATIC_CONFIG_EW_BIT (8)
231 #define EMC_STATIC_CONFIG_EW_ENABLE (1 << EMC_STATIC_CONFIG_EW_BIT)
232 #define EMC_STATIC_CONFIG_EW_DISABLE (0 << EMC_STATIC_CONFIG_EW_BIT)
235 #define Q24_8_FP(x) ((x) * 256)
236 #define EMC_NANOSECOND(x) Q24_8_FP(x)
237 #define EMC_CLOCK(x) Q24_8_FP(-(x))
334 void Chip_EMC_Init(uint32_t Enable, uint32_t ClockRatio, uint32_t EndianMode);
343 LPC_EMC->STATICEXTENDEDWAIT = Wait16Clks;