LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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lpc_core
lpc_board
boards_43xx
nxp_lpclink2_4370
board_sysinit.c
Go to the documentation of this file.
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/*
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "
board.h
"
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/* The System initialization code is called prior to the application and
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initializes the board for run-time operation. Board initialization
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includes clock setup and default pin muxing configuration. */
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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#if defined(CORE_M4)
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/* Structure for initial base clock states */
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struct
CLK_BASE_STATES
{
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CHIP_CGU_BASE_CLK_T
clk
;
/* Base clock */
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CHIP_CGU_CLKIN_T
clkin
;
/* Base clock source, see UM for allowable souorces per base clock */
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bool
autoblock_enab
;
/* Set to true to enable autoblocking on frequency change */
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bool
powerdn
;
/* Set to true if the base clock is initially powered down */
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};
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/* Initial base clock states are mostly on */
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STATIC
const
struct
CLK_BASE_STATES
InitClkStates
[] = {
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{
CLK_BASE_PHY_TX
,
CLKIN_ENET_TX
,
true
,
false
},
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#if defined(USE_RMII)
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{
CLK_BASE_PHY_RX
,
CLKIN_ENET_TX
,
true
,
false
},
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#else
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{
CLK_BASE_PHY_RX
,
CLKIN_ENET_RX
,
true
,
false
},
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#endif
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/* Clocks derived from dividers */
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{
CLK_BASE_LCD
,
CLKIN_IDIVC
,
true
,
false
},
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{
CLK_BASE_USB1
,
CLKIN_IDIVD
,
true
,
true
}
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};
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/* SPIFI high speed pin mode setup */
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STATIC
const
PINMUX_GRP_T
spifipinmuxing
[] = {
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{0x3, 3, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI CLK */
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{0x3, 4, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D3 */
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{0x3, 5, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D2 */
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{0x3, 6, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D1 */
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{0x3, 7, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)},
/* SPIFI D0 */
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{0x3, 8, (
SCU_PINIO_FAST
|
SCU_MODE_FUNC3
)}
/* SPIFI CS/SSEL */
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};
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STATIC
const
PINMUX_GRP_T
pinmuxing
[] = {
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/* Board LEDs */
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{0x1, 1, (
SCU_MODE_INBUFF_EN
|
SCU_MODE_PULLDOWN
|
SCU_MODE_FUNC0
)},
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};
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#endif
/* defined(CORE_M4) */
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Sets up system pin muxing */
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void
Board_SetupMuxing
(
void
)
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{
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#if defined(CORE_M4)
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/* Setup system level pin muxing */
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Chip_SCU_SetPinMuxing
(pinmuxing,
sizeof
(pinmuxing) /
sizeof
(
PINMUX_GRP_T
));
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/* SPIFI pin setup is done prior to setting up system clocking */
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Chip_SCU_SetPinMuxing
(
spifipinmuxing
,
sizeof
(
spifipinmuxing
) /
sizeof
(
PINMUX_GRP_T
));
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#endif
/* defined(CORE_M4) */
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}
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/* Set up and initialize clocking prior to call to main */
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void
Board_SetupClocking
(
void
)
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{
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#if defined(CORE_M4)
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int
i;
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Chip_SetupCoreClock
(
CLKIN_CRYSTAL
,
MAX_CLOCK_FREQ
,
true
);
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/* Setup system base clocks and initial states. This won't enable and
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disable individual clocks, but sets up the base clock sources for
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each individual peripheral clock. */
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for
(i = 0; i < (
sizeof
(
InitClkStates
) /
sizeof
(InitClkStates[0])); i++) {
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Chip_Clock_SetBaseClock
(InitClkStates[i].
clk
, InitClkStates[i].
clkin
,
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InitClkStates[i].
autoblock_enab
, InitClkStates[i].
powerdn
);
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}
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/* Reset and enable 32Khz oscillator */
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LPC_CREG
->CREG0 &= ~((1 << 3) | (1 << 2));
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LPC_CREG
->CREG0 |= (1 << 1) | (1 << 0);
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/* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
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Divide rate is based on CPU speed and speed of SPI FLASH part. */
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#if (MAX_CLOCK_FREQ > 180000000)
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Chip_Clock_SetDivider
(
CLK_IDIV_E
,
CLKIN_MAINPLL
, 5);
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#else
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Chip_Clock_SetDivider
(
CLK_IDIV_E
,
CLKIN_MAINPLL
, 4);
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#endif
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Chip_Clock_SetBaseClock
(
CLK_BASE_SPIFI
,
CLKIN_IDIVE
,
true
,
false
);
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/* Attach main PLL clock to divider C with a divider of 2 */
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Chip_Clock_SetDivider
(
CLK_IDIV_C
,
CLKIN_MAINPLL
, 2);
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#endif
/* defined(CORE_M4) */
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}
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/* Set up and initialize hardware prior to call to main */
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void
Board_SystemInit
(
void
)
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{
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#if defined(CORE_M4)
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/* Setup system clocking and memory. This is done early to allow the
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application and tools to clear memory and use scatter loading to
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external memory. */
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Board_SetupMuxing
();
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Board_SetupClocking
();
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#endif
/* defined(CORE_M4) */
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}
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