LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_18xx_43xx/ccan_18xx_43xx.h Source File

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ccan_18xx_43xx.h
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1 /*
2 * @brief LPC18xx/43xx CCAN driver
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #ifndef __CCAN_18XX_43XX_H_
33 #define __CCAN_18XX_43XX_H_
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
47 typedef struct {
48 __IO uint32_t CMDREQ;
49 __IO uint32_t CMDMSK;
50 __IO uint32_t MSK1;
51 __IO uint32_t MSK2;
52 __IO uint32_t ARB1;
53 __IO uint32_t ARB2;
54 __IO uint32_t MCTRL;
55 __IO uint32_t DA1;
56 __IO uint32_t DA2;
57 __IO uint32_t DB1;
58 __IO uint32_t DB2;
59 __I uint32_t RESERVED[13];
60 } CCAN_IF_T;
61
65 typedef struct {
66 __IO uint32_t CNTL;
67 __IO uint32_t STAT;
68 __I uint32_t EC;
69 __IO uint32_t BT;
70 __I uint32_t INT;
71 __IO uint32_t TEST;
72 __IO uint32_t BRPE;
73 __I uint32_t RESERVED0;
74 CCAN_IF_T IF[2];
75 __I uint32_t RESERVED2[8];
76 __I uint32_t TXREQ1;
77 __I uint32_t TXREQ2;
78 __I uint32_t RESERVED3[6];
79 __I uint32_t ND1;
80 __I uint32_t ND2;
81 __I uint32_t RESERVED4[6];
82 __I uint32_t IR1;
83 __I uint32_t IR2;
84 __I uint32_t RESERVED5[6];
85 __I uint32_t MSGV1;
86 __I uint32_t MSGV2;
87 __I uint32_t RESERVED6[6];
88 __IO uint32_t CLKDIV;
89 } LPC_CCAN_T;
90
91 /* CCAN Control register bit definitions */
92 #define CCAN_CTRL_INIT (1 << 0)
93 #define CCAN_CTRL_IE (1 << 1)
94 #define CCAN_CTRL_SIE (1 << 2)
95 #define CCAN_CTRL_EIE (1 << 3)
96 #define CCAN_CTRL_DAR (1 << 5)
97 #define CCAN_CTRL_CCE (1 << 6)
98 #define CCAN_CTRL_TEST (1 << 7)
100 /* CCAN STAT register bit definitions */
101 #define CCAN_STAT_LEC_MASK (0x07) /* Mask for Last Error Code */
102 #define CCAN_STAT_TXOK (1 << 3) /* Transmitted a message successfully */
103 #define CCAN_STAT_RXOK (1 << 4) /* Received a message successfully */
104 #define CCAN_STAT_EPASS (1 << 5) /* The CAN controller is in the error passive state*/
105 #define CCAN_STAT_EWARN (1 << 6) /*At least one of the error counters in the EC has reached the error warning limit of 96.*/
106 #define CCAN_STAT_BOFF (1 << 7) /*The CAN controller is in busoff state.*/
107
111 typedef enum {
112 CCAN_LEC_NO_ERROR,
113 CCAN_LEC_STUFF_ERROR,
114 CCAN_LEC_FORM_ERROR,
115 CCAN_LEC_ACK_ERROR,
116 CCAN_LEC_BIT1_ERROR,
118 CCAN_LEC_BIT0_ERROR,
122 CCAN_LEC_CRC_ERROR,
123 } CCAN_LEC_T;
124
125 /* CCAN INT register bit definitions */
126 #define CCAN_INT_NO_PENDING 0
127 #define CCAN_INT_STATUS 0x8000
128 #define CCAN_INT_MSG_NUM(n) (n)
130 /* CCAN TEST register bit definitions */
131 #define CCAN_TEST_BASIC_MODE (1 << 2)
132 #define CCAN_TEST_SILENT_MODE (1 << 3)
133 #define CCAN_TEST_LOOPBACK_MODE (1 << 4)
134 #define CCAN_TEST_TD_CONTROLLED (0)
135 #define CCAN_TEST_TD_MONITORED (1 << 5)
136 #define CCAN_TEST_TD_DOMINANT (2 << 5)
137 #define CCAN_TEST_TD_RECESSIVE (3 << 5)
138 #define CCAN_TEST_RD_DOMINANT (0)
139 #define CCAN_TEST_RD_RECESSIVE (1 << 7)
141 #define CCAN_SEG1_DEFAULT_VAL 5
142 #define CCAN_SEG2_DEFAULT_VAL 4
143 #define CCAN_SJW_DEFAULT_VAL 0
144
148 typedef enum {
149 CCAN_RX_DIR,
150 CCAN_TX_DIR,
151 } CCAN_TRANSFER_DIR_T;
152
162 STATIC INLINE void Chip_CCAN_EnableInt(LPC_CCAN_T *pCCAN, uint32_t mask)
163 {
164 pCCAN->CNTL |= mask;
165 }
166
176 STATIC INLINE void Chip_CCAN_DisableInt(LPC_CCAN_T *pCCAN, uint32_t mask)
177 {
178 pCCAN->CNTL &= ~mask;
179 }
180
186 STATIC INLINE uint32_t Chip_CCAN_GetIntID(LPC_CCAN_T *pCCAN)
187 {
188 return pCCAN->INT;
189 }
190
196 STATIC INLINE uint32_t Chip_CCAN_GetStatus(LPC_CCAN_T *pCCAN)
197 {
198 return pCCAN->STAT;
199 }
200
207 STATIC INLINE void Chip_CCAN_SetStatus(LPC_CCAN_T *pCCAN, uint32_t val)
208 {
209 pCCAN->STAT = val & 0x1F;
210 }
211
218 void Chip_CCAN_ClearStatus(LPC_CCAN_T *pCCAN, uint32_t val);
219
233 STATIC INLINE uint8_t Chip_CCAN_GetErrCounter(LPC_CCAN_T *pCCAN, CCAN_TRANSFER_DIR_T dir)
234 {
235 return (dir == CCAN_TX_DIR) ? (pCCAN->EC & 0x0FF) : ((pCCAN->EC >> 8) & 0x0FF);
236 }
237
243 STATIC INLINE void Chip_CCAN_EnableTestMode(LPC_CCAN_T *pCCAN)
244 {
245 pCCAN->CNTL |= CCAN_CTRL_TEST;
246 }
247
253 STATIC INLINE void Chip_CCAN_DisableTestMode(LPC_CCAN_T *pCCAN)
254 {
255 pCCAN->CNTL &= ~CCAN_CTRL_TEST;
256 }
257
265 STATIC INLINE void Chip_CCAN_ConfigTestMode(LPC_CCAN_T *pCCAN, uint32_t cfg)
266 {
267 pCCAN->TEST = cfg;
268 }
269
275 STATIC INLINE void Chip_CCAN_EnableAutoRetransmit(LPC_CCAN_T *pCCAN)
276 {
277 pCCAN->CNTL &= ~CCAN_CTRL_DAR;
278 }
279
285 STATIC INLINE void Chip_CCAN_DisableAutoRetransmit(LPC_CCAN_T *pCCAN)
286 {
287 pCCAN->CNTL |= CCAN_CTRL_DAR;
288 }
289
295 STATIC INLINE uint32_t Chip_CCAN_GetTxRQST(LPC_CCAN_T *pCCAN)
296 {
297 return pCCAN->TXREQ1 | (pCCAN->TXREQ2 << 16);
298 }
299
305 void Chip_CCAN_Init(LPC_CCAN_T *pCCAN);
306
312 void Chip_CCAN_DeInit(LPC_CCAN_T *pCCAN);
313
320 Status Chip_CCAN_SetBitRate(LPC_CCAN_T *pCCAN, uint32_t bitRate);
321
323 #define CCAN_MSG_MAX_NUM 32
324
328 typedef struct {
329 uint32_t id;
330 uint32_t dlc;
331 uint8_t data[8];
332 } CCAN_MSG_OBJ_T;
333
334 typedef enum {
335 CCAN_MSG_IF1 = 0,
336 CCAN_MSG_IF2 = 1,
337 } CCAN_MSG_IF_T;
338
339 /* bit field of IF command request n register */
340 #define CCAN_IF_CMDREQ_MSG_NUM(n) (n) /* Message number (1->20) */
341 #define CCAN_IF_CMDREQ_BUSY 0x8000 /* 1 is writing is progress, cleared when RD/WR done */
342
343 /* bit field of IF command mask register */
344 #define CCAN_IF_CMDMSK_DATAB (1 << 0)
345 #define CCAN_IF_CMDMSK_DATAA (1 << 1)
346 #define CCAN_IF_CMDMSK_W_TXRQST (1 << 2)
347 #define CCAN_IF_CMDMSK_R_NEWDAT (1 << 2)
348 #define CCAN_IF_CMDMSK_R_CLRINTPND (1 << 3)
349 #define CCAN_IF_CMDMSK_CTRL (1 << 4)
350 #define CCAN_IF_CMDMSK_ARB (1 << 5)
351 #define CCAN_IF_CMDMSK_MASK (1 << 6)
352 #define CCAN_IF_CMDMSK_WR (1 << 7) /* Tranfer direction: Write */
353 #define CCAN_IF_CMDMSK_RD (0) /* Tranfer direction: Read */
354 #define CCAN_IF_CMDMSK_TRANSFER_ALL (CCAN_IF_CMDMSK_CTRL | CCAN_IF_CMDMSK_MASK | CCAN_IF_CMDMSK_ARB | \
355 CCAN_IF_CMDMSK_DATAB | CCAN_IF_CMDMSK_DATAA)
356
357 /* bit field of IF mask 2 register */
358 #define CCAN_IF_MASK2_MXTD (1 << 15) /* 1 is extended identifier bit is used in the RX filter unit, 0 is not */
359 #define CCAN_IF_MASK2_MDIR(n) (((n) & 0x01) << 14) /* 1 is direction bit is used in the RX filter unit, 0 is not */
360
361 /* bit field of IF arbitration 2 register */
362 #define CCAN_IF_ARB2_DIR(n) (((n) & 0x01) << 13) /* 1: Dir = transmit, 0: Dir = receive */
363 #define CCAN_IF_ARB2_XTD (1 << 14) /* Extended identifier bit is used*/
364 #define CCAN_IF_ARB2_MSGVAL (1 << 15) /* Message valid bit, 1 is valid in the MO handler, 0 is ignored */
365
366 /* bit field of IF message control register */
367 #define CCAN_IF_MCTRL_DLC_MSK 0x000F /* bit mask for DLC */
368 #define CCAN_IF_MCTRL_EOB (1 << 7) /* End of buffer, always write to 1 */
369 #define CCAN_IF_MCTRL_TXRQ (1 << 8) /* 1 is TxRqst enabled */
370 #define CCAN_IF_MCTRL_RMTEN(n) (((n) & 1UL) << 9) /* 1 is remote frame enabled */
371 #define CCAN_IF_MCTRL_RXIE (1 << 10) /* 1 is RX interrupt enabled */
372 #define CCAN_IF_MCTRL_TXIE (1 << 11) /* 1 is TX interrupt enabled */
373 #define CCAN_IF_MCTRL_UMSK (1 << 12) /* 1 is to use the mask for the receive filter mask. */
374 #define CCAN_IF_MCTRL_INTP (1 << 13) /* 1 indicates message object is an interrupt source */
375 #define CCAN_IF_MCTRL_MLST (1 << 14) /* 1 indicates a message loss. */
376 #define CCAN_IF_MCTRL_NEWD (1 << 15) /* 1 indicates new data is in the message buffer. */
377
378 #define CCAN_MSG_ID_STD_MASK 0x07FF
379 #define CCAN_MSG_ID_EXT_MASK 0x1FFFFFFF
380
389 void Chip_CCAN_TransferMsgObject(LPC_CCAN_T *pCCAN,
390 CCAN_MSG_IF_T IFSel,
391 uint32_t mask,
392 uint32_t msgNum);
393
404 void Chip_CCAN_SetMsgObject (LPC_CCAN_T *pCCAN,
405 CCAN_MSG_IF_T IFSel,
406 CCAN_TRANSFER_DIR_T dir,
407 bool remoteFrame,
408 uint8_t msgNum,
409 const CCAN_MSG_OBJ_T *pMsgObj);
410
419 void Chip_CCAN_GetMsgObject(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, CCAN_MSG_OBJ_T *pMsgObj);
420
429 void Chip_CCAN_SetValidMsg(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum, bool valid);
430
436 STATIC INLINE uint32_t Chip_CCAN_GetValidMsg(LPC_CCAN_T *pCCAN)
437 {
438 return pCCAN->MSGV1 | (pCCAN->MSGV2 << 16);
439 }
440
449 STATIC INLINE void Chip_CCAN_ClearMsgIntPend(LPC_CCAN_T *pCCAN,
450 CCAN_MSG_IF_T IFSel,
451 uint8_t msgNum,
452 CCAN_TRANSFER_DIR_T dir)
453 {
454 Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum);
455 }
456
464 STATIC INLINE void Chip_CCAN_ClearNewDataFlag(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint8_t msgNum)
465 {
466 Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_NEWDAT, msgNum);
467 }
468
477 void Chip_CCAN_Send (LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, bool remoteFrame, CCAN_MSG_OBJ_T *pMsgObj);
478
486 void Chip_CCAN_AddReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id);
487
495 void Chip_CCAN_DeleteReceiveID(LPC_CCAN_T *pCCAN, CCAN_MSG_IF_T IFSel, uint32_t id);
496
501 #ifdef __cplusplus
502 }
503 #endif
504
505 #endif /* __CCAN_18XX_43XX_H_ */