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LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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CREG Register Block.
Definition at line 47 of file creg_18xx_43xx.h.
#include "creg_18xx_43xx.h"
Data Fields | |
| __I uint32_t | RESERVED0 |
| __IO uint32_t | CREG0 |
| __I uint32_t | RESERVED1 [62] |
| __IO uint32_t | MXMEMMAP |
| __I uint32_t | RESERVED2 |
| __I uint32_t | CREG1 |
| __I uint32_t | CREG2 |
| __I uint32_t | CREG3 |
| __I uint32_t | CREG4 |
| __IO uint32_t | CREG5 |
| __IO uint32_t | DMAMUX |
| __IO uint32_t | FLASHCFGA |
| __IO uint32_t | FLASHCFGB |
| __IO uint32_t | ETBCFG |
| __IO uint32_t | CREG6 |
| __IO uint32_t | M4TXEVENT |
| __I uint32_t | RESERVED4 [51] |
| __I uint32_t | CHIPID |
| __I uint32_t | RESERVED5 [65] |
| __IO uint32_t | M0SUBMEMMAP |
| __I uint32_t | RESERVED6 [2] |
| __IO uint32_t | M0SUBTXEVENT |
| __I uint32_t | RESERVED7 [58] |
| __IO uint32_t | M0APPTXEVENT |
| __IO uint32_t | M0APPMEMMAP |
| __I uint32_t | RESERVED8 [62] |
| __IO uint32_t | USB0FLADJ |
| __I uint32_t | RESERVED9 [63] |
| __IO uint32_t | USB1FLADJ |
| __I uint32_t CHIPID |
Part ID
Definition at line 73 of file creg_18xx_43xx.h.
| __IO uint32_t CREG0 |
Chip configuration register 32 kHz oscillator output and BOD control register.
Definition at line 49 of file creg_18xx_43xx.h.
| __I uint32_t CREG1 |
Configuration Register 1
Definition at line 56 of file creg_18xx_43xx.h.
| __I uint32_t CREG2 |
Configuration Register 2
Definition at line 57 of file creg_18xx_43xx.h.
| __I uint32_t CREG3 |
Configuration Register 3
Definition at line 58 of file creg_18xx_43xx.h.
| __I uint32_t CREG4 |
Configuration Register 4
Definition at line 59 of file creg_18xx_43xx.h.
| __IO uint32_t CREG5 |
Chip configuration register 5. Controls JTAG access.
Definition at line 61 of file creg_18xx_43xx.h.
| __IO uint32_t CREG6 |
Chip configuration register 6.
Definition at line 66 of file creg_18xx_43xx.h.
| __IO uint32_t DMAMUX |
DMA muxing control
Definition at line 62 of file creg_18xx_43xx.h.
| __IO uint32_t ETBCFG |
ETB RAM configuration
Definition at line 65 of file creg_18xx_43xx.h.
| __IO uint32_t FLASHCFGA |
Flash accelerator configuration register for flash bank A
Definition at line 63 of file creg_18xx_43xx.h.
| __IO uint32_t FLASHCFGB |
Flash accelerator configuration register for flash bank B
Definition at line 64 of file creg_18xx_43xx.h.
| __IO uint32_t M0APPMEMMAP |
ARM Cortex M0APP memory mapping
Definition at line 83 of file creg_18xx_43xx.h.
| __IO uint32_t M0APPTXEVENT |
M0APP IPC Event register
Definition at line 82 of file creg_18xx_43xx.h.
| __IO uint32_t M0SUBMEMMAP |
M0SUB IPC Event memory mapping
Definition at line 78 of file creg_18xx_43xx.h.
| __IO uint32_t M0SUBTXEVENT |
M0SUB IPC Event register
Definition at line 80 of file creg_18xx_43xx.h.
| __IO uint32_t M4TXEVENT |
M4 IPC event register
Definition at line 70 of file creg_18xx_43xx.h.
| __IO uint32_t MXMEMMAP |
ARM Cortex-M3/M4 memory mapping
Definition at line 51 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED0 |
< CREG Structure
Definition at line 48 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED1[62] |
Definition at line 50 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED2 |
Definition at line 55 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED4[51] |
Definition at line 71 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED5[65] |
Definition at line 77 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED6[2] |
Definition at line 79 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED7[58] |
Definition at line 81 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED8[62] |
Definition at line 84 of file creg_18xx_43xx.h.
| __I uint32_t RESERVED9[63] |
Definition at line 87 of file creg_18xx_43xx.h.
| __IO uint32_t USB0FLADJ |
USB0 frame length adjust register
Definition at line 86 of file creg_18xx_43xx.h.
| __IO uint32_t USB1FLADJ |
USB1 frame length adjust register
Definition at line 88 of file creg_18xx_43xx.h.
1.8.3.1