LPCOpen Platform for LPC18XX/43XX microcontrollers: C:/w/lpcopen_docs/software/lpc_core/lpc_chip/chip_common/fpu_init.c Source File

| LPCOpen Platform for LPC18XX/43XX microcontrollers 18XX43XX LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers

- Main Page
- Modules
- Data Structures
- Files

- File List
- Globals

fpu_init.c
Go to the documentation of this file.
1 /*
2 * @brief FPU init code
3 *
4 * @note
5 * Copyright(C) NXP Semiconductors, 2012
6 * All rights reserved.
7 *
8 * @par
9 * Software that is described herein is for illustrative purposes only
10 * which provides customers with programming information regarding the
11 * LPC products. This software is supplied "AS IS" without any warranties of
12 * any kind, and NXP Semiconductors and its licensor disclaim any and
13 * all warranties, express or implied, including all implied warranties of
14 * merchantability, fitness for a particular purpose and non-infringement of
15 * intellectual property rights. NXP Semiconductors assumes no responsibility
16 * or liability for the use of the software, conveys no license or rights under any
17 * patent, copyright, mask work right, or any other intellectual property rights in
18 * or to any products. NXP Semiconductors reserves the right to make changes
19 * in the software without notification. NXP Semiconductors also makes no
20 * representation or warranty that such application will be suitable for the
21 * specified use without further testing or modification.
22 *
23 * @par
24 * Permission to use, copy, modify, and distribute this software and its
25 * documentation is hereby granted, under NXP Semiconductors' and its
26 * licensor's relevant copyrights in the software, without fee, provided that it
27 * is used in conjunction with NXP Semiconductors microcontrollers. This
28 * copyright, permission, and disclaimer notice must appear in all copies of
29 * this code.
30 */
31
32 #if defined(CORE_M4)
33
34 #include "sys_config.h"
35 #include "cmsis.h"
36 #include "stdint.h"
37
38 /*****************************************************************************
39 * Private types/enumerations/variables
40 ****************************************************************************/
41
42 #define LPC_CPACR 0xE000ED88
43
44 #define SCB_MVFR0 0xE000EF40
45 #define SCB_MVFR0_RESET 0x10110021
46
47 #define SCB_MVFR1 0xE000EF44
48 #define SCB_MVFR1_RESET 0x11000011
49
50 /*****************************************************************************
51 * Public types/enumerations/variables
52 ****************************************************************************/
53
54 /*****************************************************************************
55 * Private functions
56 ****************************************************************************/
57
58 /*****************************************************************************
59 * Public functions
60 ****************************************************************************/
61
62 /* Early initialization of the FPU */
63 void fpuInit(void)
64 {
65 #if __FPU_PRESENT != 0
66 // from arm trm manual:
67 // ; CPACR is located at address 0xE000ED88
68 // LDR.W R0, =0xE000ED88
69 // ; Read CPACR
70 // LDR R1, [R0]
71 // ; Set bits 20-23 to enable CP10 and CP11 coprocessors
72 // ORR R1, R1, #(0xF << 20)
73 // ; Write back the modified value to the CPACR
74 // STR R1, [R0]
75
76 volatile uint32_t *regCpacr = (uint32_t *) LPC_CPACR;
77 volatile uint32_t *regMvfr0 = (uint32_t *) SCB_MVFR0;
78 volatile uint32_t *regMvfr1 = (uint32_t *) SCB_MVFR1;
79 volatile uint32_t Cpacr;
80 volatile uint32_t Mvfr0;
81 volatile uint32_t Mvfr1;
82 char vfpPresent = 0;
83
84 Mvfr0 = *regMvfr0;
85 Mvfr1 = *regMvfr1;
86
87 vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
88
89 if (vfpPresent) {
90 Cpacr = *regCpacr;
91 Cpacr |= (0xF << 20);
92 *regCpacr = Cpacr; // enable CP10 and CP11 for full access
93 }
94 #endif /* __FPU_PRESENT != 0 */
95 }
96
97 #endif /* defined(CORE_M4 */