LPCOpen Platform for LPC18XX/43XX microcontrollers
18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
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chip_18xx_43xx
chip_18xx_43xx.c
Go to the documentation of this file.
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/*
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* @brief LPC18xx/LPC43xx chip driver source
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "
chip.h
"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/* USB PLL pre-initialized setup values for 480MHz output rate */
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static
const
CGU_USBAUDIO_PLL_SETUP_T
usbPLLSetup
= {
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0x0000601D,
/* Default control with main osc input, PLL disabled */
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0x06167FFA,
/* M-divider value for 480MHz output from 12MHz input */
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0x00000000,
/* N-divider value */
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0x00000000,
/* Not applicable for USB PLL */
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480000000
/* PLL output frequency */
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};
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/* System Clock Frequency (Core Clock) */
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uint32_t
SystemCoreClock
;
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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static
void
Chip_USB_PllSetup
(
void
)
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{
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/* No need to setup anything if PLL is already setup for the frequency */
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if
(
Chip_Clock_GetClockInputHz
(
CLKIN_USBPLL
) == usbPLLSetup.
freq
)
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return ;
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/* Setup default USB PLL state for a 480MHz output and attach */
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Chip_Clock_SetupPLL
(
CLKIN_CRYSTAL
,
CGU_USB_PLL
, &usbPLLSetup);
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/* enable USB PLL */
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Chip_Clock_EnablePLL
(
CGU_USB_PLL
);
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/* Wait for PLL lock */
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while
(!(
Chip_Clock_GetPLLStatus
(
CGU_USB_PLL
) &
CGU_PLL_LOCKED
)) {}
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}
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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void
Chip_USB0_Init
(
void
)
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{
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/* Set up USB PLL */
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Chip_USB_PllSetup
();
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/* Setup USB0 base clock as clock out from USB PLL */
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Chip_Clock_SetBaseClock
(
CLK_BASE_USB0
,
CLKIN_USBPLL
,
true
,
true
);
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/* enable USB main clock */
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Chip_Clock_EnableBaseClock
(
CLK_BASE_USB0
);
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Chip_Clock_EnableOpts
(
CLK_MX_USB0
,
true
,
true
, 1);
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/* enable USB0 phy */
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Chip_CREG_EnableUSB0Phy
();
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}
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void
Chip_USB1_Init
(
void
)
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{
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/* Setup and enable the PLL */
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Chip_USB_PllSetup
();
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/* USB1 needs a 60MHz clock. To get it, a divider of 4 and then 2 are
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chained to make a divide by 8 function. Connect the output of
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divider D to the USB1 base clock. */
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Chip_Clock_SetDivider
(
CLK_IDIV_A
,
CLKIN_USBPLL
, 4);
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Chip_Clock_SetDivider
(
CLK_IDIV_D
,
CLKIN_IDIVA
, 2);
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Chip_Clock_SetBaseClock
(
CLK_BASE_USB1
,
CLKIN_IDIVD
,
true
,
true
);
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/* enable USB main clock */
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Chip_Clock_EnableBaseClock
(
CLK_BASE_USB1
);
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Chip_Clock_EnableOpts
(
CLK_MX_USB1
,
true
,
true
, 1);
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/* enable USB1_DP and USB1_DN on chip FS phy.*/
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LPC_SCU
->SFSUSB = 0x12;
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}
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/* Update system core clock rate, should be called if the system has
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a clock rate change */
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void
SystemCoreClockUpdate
(
void
)
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{
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/* CPU core speed */
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SystemCoreClock
=
Chip_Clock_GetRate
(
CLK_MX_MXCORE
);
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}
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