LPCOpen Platform for LPC18XX/43XX microcontrollers  18XX43XX
LPCOpen Platform for the NXP LPC18XX/43XX family of Microcontrollers
clock_18xx_43xx.h
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1 /*
2  * @brief LPC18xx/43xx clock driver
3  *
4  * @note
5  * Copyright(C) NXP Semiconductors, 2012
6  * All rights reserved.
7  *
8  * @par
9  * Software that is described herein is for illustrative purposes only
10  * which provides customers with programming information regarding the
11  * LPC products. This software is supplied "AS IS" without any warranties of
12  * any kind, and NXP Semiconductors and its licenser disclaim any and
13  * all warranties, express or implied, including all implied warranties of
14  * merchantability, fitness for a particular purpose and non-infringement of
15  * intellectual property rights. NXP Semiconductors assumes no responsibility
16  * or liability for the use of the software, conveys no license or rights under any
17  * patent, copyright, mask work right, or any other intellectual property rights in
18  * or to any products. NXP Semiconductors reserves the right to make changes
19  * in the software without notification. NXP Semiconductors also makes no
20  * representation or warranty that such application will be suitable for the
21  * specified use without further testing or modification.
22  *
23  * @par
24  * Permission to use, copy, modify, and distribute this software and its
25  * documentation is hereby granted, under NXP Semiconductors' and its
26  * licensor's relevant copyrights in the software, without fee, provided that it
27  * is used in conjunction with NXP Semiconductors microcontrollers. This
28  * copyright, permission, and disclaimer notice must appear in all copies of
29  * this code.
30  */
31 
32 #ifndef __CLOCK_18XX_43XX_H_
33 #define __CLOCK_18XX_43XX_H_
34 
35 #include "cguccu_18xx_43xx.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
63 /* Internal oscillator frequency */
64 #define CGU_IRC_FREQ (12000000)
65 
66 #ifndef MAX_CLOCK_FREQ
67 #if defined(CHIP_LPC43XX)
68 #define MAX_CLOCK_FREQ (204000000)
69 #else
70 #define MAX_CLOCK_FREQ (180000000)
71 #endif
72 #endif
73 
74 #define PLL_MIN_CCO_FREQ 156000000
75 #define PLL_MAX_CCO_FREQ 320000000
80 typedef struct {
81  int ctrl;
83  int nsel;
84  int psel;
85  int msel;
86  uint32_t fin;
87  uint32_t fout;
88  uint32_t fcco;
89 } PLL_PARAM_T;
90 
95 void Chip_Clock_EnableCrystal(void);
96 
101 void Chip_Clock_DisableCrystal(void);
102 
114 uint32_t Chip_Clock_SetupMainPLLHz(CHIP_CGU_CLKIN_T Input, uint32_t MinHz, uint32_t DesiredHz, uint32_t MaxHz);
115 
122 uint32_t Chip_Clock_SetupMainPLLMult(CHIP_CGU_CLKIN_T Input, uint32_t mult);
123 
129 uint32_t Chip_Clock_GetMainPLLHz(void);
130 
137 __STATIC_INLINE void Chip_Clock_DisableMainPLL(void)
138 {
139  /* power down main PLL */
140  LPC_CGU->PLL1_CTRL |= 1;
141 }
142 
148 __STATIC_INLINE void Chip_Clock_EnableMainPLL(void)
149 {
150  /* power up main PLL */
151  LPC_CGU->PLL1_CTRL &= ~1;
152 }
159 __STATIC_INLINE void Chip_Clock_SetupMainPLL(const PLL_PARAM_T *ppll)
160 {
161  /* power up main PLL */
162  LPC_CGU->PLL1_CTRL = ppll->ctrl | ((uint32_t) ppll->srcin << 24) | (ppll->msel << 16) | (ppll->nsel << 12) | (ppll->psel << 8);
163 }
164 
174 void Chip_Clock_SetDivider(CHIP_CGU_IDIV_T Divider, CHIP_CGU_CLKIN_T Input, uint32_t Divisor);
175 
182 
189 
198 
207 
216 void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn);
217 
226 void Chip_Clock_GetBaseClockOpts(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T *Input, bool *autoblocken,
227  bool *powerdn);
228 
235 
242 
249 
256 
265 void Chip_Clock_EnableOpts(CHIP_CCU_CLK_T clk, bool autoen, bool wakeupen, int div);
266 
273 
278 void Chip_Clock_RTCEnable(void);
279 
286 
292 uint32_t Chip_Clock_GetRate(CHIP_CCU_CLK_T clk);
293 
298 uint32_t Chip_Clock_GetEMCRate(void);
299 
306 void Chip_Clock_StartPowerDown(void);
307 
314 void Chip_Clock_ClearPowerDown(void);
315 
319 typedef struct {
320  uint32_t ctrl; /* Default control word for PLL */
321  uint32_t mdiv; /* Default M-divider value for PLL */
322  uint32_t ndiv; /* Default NP-divider value for PLL */
323  uint32_t fract; /* Default fractional value for audio PLL only */
324  uint32_t freq; /* Output frequency of the pll */
326 
336  const CGU_USBAUDIO_PLL_SETUP_T *pPLLSetup);
337 
344 
351 
352 #define CGU_PLL_LOCKED (1 << 0) /* PLL locked status */
353 #define CGU_PLL_FR (1 << 1) /* PLL free running indicator status */
354 
361 
372 int Chip_Clock_CalcMainPLLValue(uint32_t freq, PLL_PARAM_T *ppll);
373 
374 
380 __STATIC_INLINE int Chip_Clock_MainPLLLocked(void)
381 {
382  /* Return true if locked */
383  return (LPC_CGU->PLL1_STAT & 1) != 0;
384 }
385 
390 #ifdef __cplusplus
391 }
392 #endif
393 
394 #endif /* __CLOCK_18XX_43XX_H_ */