<?xml version="1.0" encoding="utf-8"?><!DOCTYPE article  PUBLIC '-//OASIS//DTD DocBook XML V4.4//EN'  'http://www.docbook.org/xml/4.4/docbookx.dtd'><article><articleinfo><title>WebHome/ClasesTeoricas</title><revhistory><revision><revnumber>10</revnumber><date>2020-04-21 21:52:10</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>9</revnumber><date>2020-04-21 21:50:31</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>8</revnumber><date>2020-04-21 21:09:28</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>7</revnumber><date>2020-04-21 21:05:29</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>6</revnumber><date>2020-04-21 20:48:44</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>5</revnumber><date>2020-04-21 19:52:07</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>4</revnumber><date>2020-04-13 22:33:56</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>3</revnumber><date>2020-04-13 22:30:42</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>2</revnumber><date>2020-03-31 21:10:59</date><authorinitials>GuillermoSteiner</authorinitials></revision><revision><revnumber>1</revnumber><date>2020-03-31 20:38:54</date><authorinitials>GuillermoSteiner</authorinitials></revision></revhistory></articleinfo><section><title>Clases Teóricas 4R2</title><informaltable><tgroup cols="6"><colspec colname="col_0"/><colspec colname="col_1"/><colspec colname="col_2"/><colspec colname="col_3"/><colspec colname="col_4"/><colspec colname="col_5"/><tbody><row rowsep="1"><entry align="center" colsep="1" nameend="col_4" namest="col_0" rowsep="1"><para> <emphasis role="strong">1er Cuatrimestre</emphasis> </para></entry></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>##</para></entry><entry colsep="1" rowsep="1"><para> Titulo                                   </para></entry><entry colsep="1" rowsep="1"><para> Clases </para></entry><entry colsep="1" rowsep="1"><para> Material de estudio </para></entry><entry colsep="1" rowsep="1"><para> Autoevaluación </para></entry><entry colsep="1" rowsep="1"><para>Bibliografía </para></entry></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>1</para></entry><entry colsep="1" rowsep="1"><para> Transferencia entre registros Microoperaciones </para></entry><entry colsep="1" rowsep="1"><para> 31-Marzo - 14-Abril </para></entry><entry colsep="1" rowsep="1"><para> <ulink url="https://ciii.frc.utn.edu.ar/TecnicasDigitalesII/WebHome/ClasesTeoricas/TecnicasDigitalesII/WebHome/ClasesTeoricas?action=AttachFile&amp;do=get&amp;target=clase_cpu.pdf">clase_cpu.pdf</ulink> </para></entry><entry colsep="1" rowsep="1"><para>  <ulink url="https://ciii.frc.utn.edu.ar/TecnicasDigitalesII/WebHome/ClasesTeoricas/TecnicasDigitalesII/WebHome/ClasesTeoricas?action=AttachFile&amp;do=get&amp;target=Autoevaluacion_1_4R2_resuelto.pdf">Solución de la Autoevaluación</ulink>   </para></entry><entry colsep="1" rowsep="1"><para> 232 a 251 Morris Mano. Ingeniería computacional: diseño del hardware. Prentice Hall,1991. Capítulo 7 </para></entry></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>2</para></entry><entry colsep="1" rowsep="1"><para> Unidad Procesadora y ALU (unidad aritmética)   </para></entry><entry colsep="1" rowsep="1"><para> 31-Marzo - 14-Abril </para></entry><entry colsep="1" rowsep="1"><para> idem  </para></entry><entry colsep="1" rowsep="1"><para>idem  </para></entry><entry colsep="1" rowsep="1"><para> 251 a 257  Morris Mano. Ingeniería computacional: diseño del hardware. Prentice Hall,1991. Capítulo 7 </para></entry></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>3</para></entry><entry colsep="1" rowsep="1"><para> ALU (unidad lógica) y Unida de Corrimiento     </para></entry><entry colsep="1" rowsep="1"><para> 31-Marzo - 14-Abril </para></entry><entry colsep="1" rowsep="1"><para> idem  </para></entry><entry colsep="1" rowsep="1"><para>idem  </para></entry><entry colsep="1" rowsep="1"><para> 257 a 262 Morris Mano. Ingeniería computacional: diseño del hardware. Prentice Hall,1991. Capítulo 7 </para></entry></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>4</para></entry><entry colsep="1" rowsep="1"><para> Unidad de Control                              </para></entry><entry colsep="1" rowsep="1"><para> 31-Marzo - 14-Abril </para></entry><entry colsep="1" rowsep="1"><para> idem  </para></entry><entry colsep="1" rowsep="1"><para>idem  </para></entry><entry colsep="1" rowsep="1"><para> 262 a 265 Morris Mano. Ingeniería computacional: diseño del hardware. Prentice Hall,1991. Capítulo 7 </para></entry></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>5</para></entry><entry colsep="1" rowsep="1"><para> Arq.ARM / Registros y Memoria                  </para></entry><entry colsep="1" rowsep="1"><para> 21-Abril </para></entry><entry colsep="1" rowsep="1"><para> <ulink url="https://ciii.frc.utn.edu.ar/TecnicasDigitalesII/WebHome/ClasesTeoricas/TecnicasDigitalesII/WebHome/ClasesTeoricas?action=AttachFile&amp;do=get&amp;target=clase_regymem.pdf">clase_regymem.pdf</ulink> </para><para> Link de Video: <ulink url="https://drive.google.com/open?id=1_BwXzbqrzWCc0SM08TuWQOHCkED0thQ_"/> </para></entry><entry colsep="1" rowsep="1"/><entry colsep="1" rowsep="1"><para> 295 a 303 Harris &amp; Harris. Digital design and computer architecture: ARM edition. Elsevier, 2015. Capítulo 6. </para></entry></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>6</para></entry><entry colsep="1" rowsep="1"><para> Instrucciones de Procesamiento de Datos  </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>7</para></entry><entry colsep="1" rowsep="1"><para> Banderas y Ejecución Condicional         </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>8</para></entry><entry colsep="1" rowsep="1"><para> Bifurcaciones                            </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>9</para></entry><entry colsep="1" rowsep="1"><para> Acceso a Memoria                         </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>10</para></entry><entry colsep="1" rowsep="1"><para> Llamado a Funciones                      </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>11</para></entry><entry colsep="1" rowsep="1"><para> Lenguaje Máquina                         </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>12</para></entry><entry colsep="1" rowsep="1"><para> Compilador                               </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>13</para></entry><entry colsep="1" rowsep="1"><para> Excepciones                              </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>14</para></entry><entry colsep="1" rowsep="1"><para> Datapath de ciclo único                  </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry colsep="1" rowsep="1"><para>15</para></entry><entry colsep="1" rowsep="1"><para> Control de ciclo único                   </para></entry><entry colsep="1" rowsep="1"/></row></tbody></tgroup></informaltable><informaltable><tgroup cols="3"><colspec colname="col_0"/><colspec colname="col_1"/><colspec colname="col_2"/><tbody><row rowsep="1"><entry align="center" colsep="1" nameend="col_2" namest="col_0" rowsep="1"><para> <emphasis role="strong">2do Cuatrimestre</emphasis> </para></entry></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> Entrada/Salida                           </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> GPIO                                     </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> SPI                                      </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> UART                                     </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> Timer                                    </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> ADC y DAC                                </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> Tipos de DAC y de ADC                    </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> ADC doble rampa, delta y sigma delta     </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> ADC sigma delta (cont) flash y de aproximación sucesivas </para></entry><entry colsep="1" rowsep="1"/></row><row rowsep="1"><entry align="center" colsep="1" nameend="col_1" namest="col_0" rowsep="1"><para> ADC subrango y pipeline </para></entry><entry colsep="1" rowsep="1"/></row></tbody></tgroup></informaltable></section></article>