1 #ifndef lpc2114_h
   2 #define lpc2114_h
   3 /*******************************************************************************
   4 lpc2114.h - Register defs for Philips LPC2114, LPC2124
   5 
   6 
   7 THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND, 
   8 EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY 
   9 WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY 
  10 PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS 
  11 OF OTHERS.
  12            
  13 This file may be freely used for commercial and non-commercial applications, 
  14 including being redistributed with any tools.
  15 
  16 If you find a problem with the file, please report it so that it can be fixed.
  17 
  18 Created by Sten Larsson (sten_larsson at yahoo com)
  19 *******************************************************************************/
  20 
  21 #define REG8  (volatile unsigned char*)
  22 #define REG16 (volatile unsigned short*)
  23 #define REG32 (volatile unsigned int*)
  24 
  25 
  26 /*##############################################################################
  27 ## MISC
  28 ##############################################################################*/
  29 
  30         /* Constants for data to put in IRQ/FIQ Exception Vectors */
  31 #define VECTDATA_IRQ  0xE51FFFF0  /* LDR PC,[PC,#-0xFF0] */
  32 #define VECTDATA_FIQ  /* __TODO */
  33 
  34 
  35 /*##############################################################################
  36 ## VECTORED INTERRUPT CONTROLLER
  37 ##############################################################################*/
  38 
  39 #define VICIRQStatus    (*(REG32 (0xFFFFF000)))
  40 #define VICFIQStatus    (*(REG32 (0xFFFFF004)))
  41 #define VICRawIntr      (*(REG32 (0xFFFFF008)))
  42 #define VICIntSelect    (*(REG32 (0xFFFFF00C)))
  43 #define VICIntEnable    (*(REG32 (0xFFFFF010)))
  44 #define VICIntEnClear   (*(REG32 (0xFFFFF014)))
  45 #define VICSoftInt      (*(REG32 (0xFFFFF018)))
  46 #define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
  47 #define VICProtection   (*(REG32 (0xFFFFF020)))
  48 #define VICVectAddr     (*(REG32 (0xFFFFF030)))
  49 #define VICDefVectAddr  (*(REG32 (0xFFFFF034)))
  50 
  51 #define VICVectAddr0    (*(REG32 (0xFFFFF100)))
  52 #define VICVectAddr1    (*(REG32 (0xFFFFF104)))
  53 #define VICVectAddr2    (*(REG32 (0xFFFFF108)))
  54 #define VICVectAddr3    (*(REG32 (0xFFFFF10C)))
  55 #define VICVectAddr4    (*(REG32 (0xFFFFF110)))
  56 #define VICVectAddr5    (*(REG32 (0xFFFFF114)))
  57 #define VICVectAddr6    (*(REG32 (0xFFFFF118)))
  58 #define VICVectAddr7    (*(REG32 (0xFFFFF11C)))
  59 #define VICVectAddr8    (*(REG32 (0xFFFFF120)))
  60 #define VICVectAddr9    (*(REG32 (0xFFFFF124)))
  61 #define VICVectAddr10   (*(REG32 (0xFFFFF128)))
  62 #define VICVectAddr11   (*(REG32 (0xFFFFF12C)))
  63 #define VICVectAddr12   (*(REG32 (0xFFFFF130)))
  64 #define VICVectAddr13   (*(REG32 (0xFFFFF134)))
  65 #define VICVectAddr14   (*(REG32 (0xFFFFF138)))
  66 #define VICVectAddr15   (*(REG32 (0xFFFFF13C)))
  67 
  68 #define VICVectCntl0    (*(REG32 (0xFFFFF200)))
  69 #define VICVectCntl1    (*(REG32 (0xFFFFF204)))
  70 #define VICVectCntl2    (*(REG32 (0xFFFFF208)))
  71 #define VICVectCntl3    (*(REG32 (0xFFFFF20C)))
  72 #define VICVectCntl4    (*(REG32 (0xFFFFF210)))
  73 #define VICVectCntl5    (*(REG32 (0xFFFFF214)))
  74 #define VICVectCntl6    (*(REG32 (0xFFFFF218)))
  75 #define VICVectCntl7    (*(REG32 (0xFFFFF21C)))
  76 #define VICVectCntl8    (*(REG32 (0xFFFFF220)))
  77 #define VICVectCntl9    (*(REG32 (0xFFFFF224)))
  78 #define VICVectCntl10   (*(REG32 (0xFFFFF228)))
  79 #define VICVectCntl11   (*(REG32 (0xFFFFF22C)))
  80 #define VICVectCntl12   (*(REG32 (0xFFFFF230)))
  81 #define VICVectCntl13   (*(REG32 (0xFFFFF234)))
  82 #define VICVectCntl14   (*(REG32 (0xFFFFF238)))
  83 #define VICVectCntl15   (*(REG32 (0xFFFFF23C)))
  84 
  85 #define VICITCR         (*(REG32 (0xFFFFF300)))
  86 #define VICITIP1        (*(REG32 (0xFFFFF304)))
  87 #define VICITIP2        (*(REG32 (0xFFFFF308)))
  88 #define VICITOP1        (*(REG32 (0xFFFFF30C)))
  89 #define VICITOP2        (*(REG32 (0xFFFFF310)))
  90 #define VICPeriphID0    (*(REG32 (0xFFFFFFE0)))
  91 #define VICPeriphID1    (*(REG32 (0xFFFFFFE4)))
  92 #define VICPeriphID2    (*(REG32 (0xFFFFFFE8)))
  93 #define VICPeriphID3    (*(REG32 (0xFFFFFFEC)))
  94 
  95 #define VICIntEnClr     VICIntEnClear
  96 #define VICSoftIntClr   VICSoftIntClear
  97 
  98 
  99 /*##############################################################################
 100 ## PCB - Pin Connect Block
 101 ##############################################################################*/
 102 
 103 #define PCB_PINSEL0     (*(REG32 (0xE002C000)))
 104 #define PCB_PINSEL1     (*(REG32 (0xE002C004)))
 105 #define PCB_PINSEL2     (*(REG32 (0xE002C014)))
 106 
 107 
 108 /*##############################################################################
 109 ## GPIO - General Purpose I/O
 110 ##############################################################################*/
 111 
 112 #define IOPIN0         (*((volatile unsigned long *) 0xE0028000))
 113 #define IOSET0         (*((volatile unsigned long *) 0xE0028004))
 114 #define IODIR0         (*((volatile unsigned long *) 0xE0028008))
 115 #define IOCLR0         (*((volatile unsigned long *) 0xE002800C))
 116 #define IOPIN1         (*((volatile unsigned long *) 0xE0028010))
 117 #define IOSET1         (*((volatile unsigned long *) 0xE0028014))
 118 #define IODIR1         (*((volatile unsigned long *) 0xE0028018))
 119 #define IOCLR1         (*((volatile unsigned long *) 0xE002801C))
 120 
 121 
 122 /*##############################################################################
 123 ## UART0 / UART1
 124 ##############################################################################*/
 125 
 126 /* ---- UART 0 --------------------------------------------- */
 127 #define UART0_RBR       (*(REG32 (0xE000C000)))
 128 #define UART0_THR       (*(REG32 (0xE000C000)))
 129 #define UART0_IER       (*(REG32 (0xE000C004)))
 130 #define UART0_IIR       (*(REG32 (0xE000C008)))
 131 #define UART0_FCR       (*(REG32 (0xE000C008)))
 132 #define UART0_LCR       (*(REG32 (0xE000C00C)))
 133 #define UART0_LSR       (*(REG32 (0xE000C014)))
 134 #define UART0_SCR       (*(REG32 (0xE000C01C)))
 135 #define UART0_DLL       (*(REG32 (0xE000C000)))
 136 #define UART0_DLM       (*(REG32 (0xE000C004)))
 137 
 138 /* ---- UART 1 --------------------------------------------- */
 139 #define UART1_RBR       (*(REG32 (0xE0010000)))
 140 #define UART1_THR       (*(REG32 (0xE0010000)))
 141 #define UART1_IER       (*(REG32 (0xE0010004)))
 142 #define UART1_IIR       (*(REG32 (0xE0010008)))
 143 #define UART1_FCR       (*(REG32 (0xE0010008)))
 144 #define UART1_LCR       (*(REG32 (0xE001000C)))
 145 #define UART1_LSR       (*(REG32 (0xE0010014)))
 146 #define UART1_SCR       (*(REG32 (0xE001001C)))
 147 #define UART1_DLL       (*(REG32 (0xE0010000)))
 148 #define UART1_DLM       (*(REG32 (0xE0010004)))
 149 #define UART1_MCR       (*(REG32 (0xE0010010)))
 150 #define UART1_MSR       (*(REG32 (0xE0010018)))
 151 
 152 
 153 /*##############################################################################
 154 ## I2C
 155 ##############################################################################*/
 156 
 157 #define I2C_I2CONSET    (*(REG32 (0xE001C000)))
 158 #define I2C_I2STAT      (*(REG32 (0xE001C004)))
 159 #define I2C_I2DAT       (*(REG32 (0xE001C008)))
 160 #define I2C_I2ADR       (*(REG32 (0xE001C00C)))
 161 #define I2C_I2SCLH      (*(REG32 (0xE001C010)))
 162 #define I2C_I2SCLL      (*(REG32 (0xE001C014)))
 163 #define I2C_I2CONCLR    (*(REG32 (0xE001C018)))
 164 
 165 
 166 /*##############################################################################
 167 ## SPI - Serial Peripheral Interface 
 168 ##############################################################################*/
 169 
 170 #define SPI_SPCR        (*(REG32 (0xE0020000)))  /* SPI = SPI0 */
 171 #define SPI_SPSR        (*(REG32 (0xE0020004)))
 172 #define SPI_SPDR        (*(REG32 (0xE0020008)))
 173 #define SPI_SPCCR       (*(REG32 (0xE002000C)))
 174 #define SPI_SPTCR       (*(REG32 (0xE0020010)))
 175 #define SPI_SPTSR       (*(REG32 (0xE0020014)))
 176 #define SPI_SPTOR       (*(REG32 (0xE0020018)))
 177 #define SPI_SPINT       (*(REG32 (0xE002001C)))
 178 
 179 #define SPI0_SPCR       (*(REG32 (0xE0020000)))  /* SPI = SPI0 */
 180 #define SPI0_SPSR       (*(REG32 (0xE0020004)))
 181 #define SPI0_SPDR       (*(REG32 (0xE0020008)))
 182 #define SPI0_SPCCR      (*(REG32 (0xE002000C)))
 183 #define SPI0_SPTCR      (*(REG32 (0xE0020010)))
 184 #define SPI0_SPTSR      (*(REG32 (0xE0020014)))
 185 #define SPI0_SPTOR      (*(REG32 (0xE0020018)))
 186 #define SPI0_SPINT      (*(REG32 (0xE002001C)))
 187 
 188 #define SPI1_SPCR       (*(REG32 (0xE0030000)))
 189 #define SPI1_SPSR       (*(REG32 (0xE0030004)))
 190 #define SPI1_SPDR       (*(REG32 (0xE0030008)))
 191 #define SPI1_SPCCR      (*(REG32 (0xE003000C)))
 192 #define SPI1_SPTCR      (*(REG32 (0xE0030010)))
 193 #define SPI1_SPTSR      (*(REG32 (0xE0030014)))
 194 #define SPI1_SPTOR      (*(REG32 (0xE0030018)))
 195 #define SPI1_SPINT      (*(REG32 (0xE003001C)))
 196 
 197 
 198 /*##############################################################################
 199 ## Timer 0 and Timer 1
 200 ##############################################################################*/
 201 
 202 /* ---- Timer 0 -------------------------------------------- */
 203 #define T0IR           (*((volatile unsigned long *) 0xE0004000))
 204 #define T0TCR          (*((volatile unsigned long *) 0xE0004004))
 205 #define T0TC           (*((volatile unsigned long *) 0xE0004008))
 206 #define T0PR           (*((volatile unsigned long *) 0xE000400C))
 207 #define T0PC           (*((volatile unsigned long *) 0xE0004010))
 208 #define T0MCR          (*((volatile unsigned long *) 0xE0004014))
 209 #define T0MR0          (*((volatile unsigned long *) 0xE0004018))
 210 #define T0MR1          (*((volatile unsigned long *) 0xE000401C))
 211 #define T0MR2          (*((volatile unsigned long *) 0xE0004020))
 212 #define T0MR3          (*((volatile unsigned long *) 0xE0004024))
 213 #define T0CCR          (*((volatile unsigned long *) 0xE0004028))
 214 #define T0CR0          (*((volatile unsigned long *) 0xE000402C))
 215 #define T0CR1          (*((volatile unsigned long *) 0xE0004030))
 216 #define T0CR2          (*((volatile unsigned long *) 0xE0004034))
 217 #define T0CR3          (*((volatile unsigned long *) 0xE0004038))
 218 #define T0EMR          (*((volatile unsigned long *) 0xE000403C))
 219 #define T0CTCR         (*((volatile unsigned long *) 0xE0004070))
 220 
 221 /* ---- Timer 1 -------------------------------------------- */
 222 #define T1_IR           (*(REG32 (0xE0008000)))
 223 #define T1_TCR          (*(REG32 (0xE0008004)))
 224 #define T1_TC           (*(REG32 (0xE0008008)))
 225 #define T1_PR           (*(REG32 (0xE000800C)))
 226 #define T1_PC           (*(REG32 (0xE0008010)))
 227 #define T1_MCR          (*(REG32 (0xE0008014)))
 228 #define T1_MR0          (*(REG32 (0xE0008018)))
 229 #define T1_MR1          (*(REG32 (0xE000801C)))
 230 #define T1_MR2          (*(REG32 (0xE0008020)))
 231 #define T1_MR3          (*(REG32 (0xE0008024)))
 232 #define T1_CCR          (*(REG32 (0xE0008028)))
 233 #define T1_CR0          (*(REG32 (0xE000802C)))
 234 #define T1_CR1          (*(REG32 (0xE0008030)))
 235 #define T1_CR2          (*(REG32 (0xE0008034)))
 236 #define T1_CR3          (*(REG32 (0xE0008038)))
 237 #define T1_EMR          (*(REG32 (0xE000803C)))
 238 
 239 
 240 /*##############################################################################
 241 ## PWM
 242 ##############################################################################*/
 243 
 244 #define PWM_IR          (*(REG32 (0xE0014000)))
 245 #define PWM_TCR         (*(REG32 (0xE0014004)))
 246 #define PWM_TC          (*(REG32 (0xE0014008)))
 247 #define PWM_PR          (*(REG32 (0xE001400C)))
 248 #define PWM_PC          (*(REG32 (0xE0014010)))
 249 #define PWM_MCR         (*(REG32 (0xE0014014)))
 250 #define PWM_MR0         (*(REG32 (0xE0014018)))
 251 #define PWM_MR1         (*(REG32 (0xE001401C)))
 252 #define PWM_MR2         (*(REG32 (0xE0014020)))
 253 #define PWM_MR3         (*(REG32 (0xE0014024)))
 254 #define PWM_MR4         (*(REG32 (0xE0014040)))
 255 #define PWM_MR5         (*(REG32 (0xE0014044)))
 256 #define PWM_MR6         (*(REG32 (0xE0014048)))
 257 #define PWM_EMR         (*(REG32 (0xE001403C)))
 258 #define PWM_PCR         (*(REG32 (0xE001404C)))
 259 #define PWM_LER         (*(REG32 (0xE0014050)))
 260 #define PWM_CCR         (*(REG32 (0xE0014028)))
 261 #define PWM_CR0         (*(REG32 (0xE001402C)))
 262 #define PWM_CR1         (*(REG32 (0xE0014030)))
 263 #define PWM_CR2         (*(REG32 (0xE0014034)))
 264 #define PWM_CR3         (*(REG32 (0xE0014038)))
 265 
 266 /*##############################################################################
 267 ## RTC
 268 ##############################################################################*/
 269 
 270 /* ---- RTC: Miscellaneous Register Group ------------------ */
 271 #define RTC_ILR         (*(REG32 (0xE0024000)))
 272 #define RTC_CTC         (*(REG32 (0xE0024004)))
 273 #define RTC_CCR         (*(REG32 (0xE0024008)))  
 274 #define RTC_CIIR        (*(REG32 (0xE002400C)))
 275 #define RTC_AMR         (*(REG32 (0xE0024010)))
 276 #define RTC_CTIME0      (*(REG32 (0xE0024014)))
 277 #define RTC_CTIME1      (*(REG32 (0xE0024018)))
 278 #define RTC_CTIME2      (*(REG32 (0xE002401C)))
 279 
 280 /* ---- RTC: Timer Control Group --------------------------- */
 281 #define RTC_SEC         (*(REG32 (0xE0024020)))
 282 #define RTC_MIN         (*(REG32 (0xE0024024)))
 283 #define RTC_HOUR        (*(REG32 (0xE0024028)))
 284 #define RTC_DOM         (*(REG32 (0xE002402C)))
 285 #define RTC_DOW         (*(REG32 (0xE0024030)))
 286 #define RTC_DOY         (*(REG32 (0xE0024034)))
 287 #define RTC_MONTH       (*(REG32 (0xE0024038)))
 288 #define RTC_YEAR        (*(REG32 (0xE002403C)))
 289 
 290 /* ---- RTC: Alarm Control Group --------------------------- */
 291 #define RTC_ALSEC       (*(REG32 (0xE0024060)))
 292 #define RTC_ALMIN       (*(REG32 (0xE0024064)))
 293 #define RTC_ALHOUR      (*(REG32 (0xE0024068)))
 294 #define RTC_ALDOM       (*(REG32 (0xE002406C)))
 295 #define RTC_ALDOW       (*(REG32 (0xE0024070)))
 296 #define RTC_ALDOY       (*(REG32 (0xE0024074)))
 297 #define RTC_ALMON       (*(REG32 (0xE0024078)))
 298 #define RTC_ALYEAR      (*(REG32 (0xE002407C)))
 299 
 300 /* ---- RTC: Reference Clock Divider Group ----------------- */
 301 #define RTC_PREINT      (*(REG32 (0xE0024080)))
 302 #define RTC_PREFRAC     (*(REG32 (0xE0024084)))
 303 
 304 
 305 /*##############################################################################
 306 ## AE - AD Converter
 307 ##############################################################################*/
 308 
 309 #define AD_ADCR        (*(REG32 (0xE0034000)))
 310 #define AD_ADDR        (*(REG32 (0xE0034004)))
 311 
 312 
 313 /*##############################################################################
 314 ## WD - Watchdog
 315 ##############################################################################*/
 316 
 317 #define WD_WDMOD        (*(REG32 (0xE0000000)))
 318 #define WD_WDTC         (*(REG32 (0xE0000004)))
 319 #define WD_WDFEED       (*(REG32 (0xE0000008)))
 320 #define WD_WDTV         (*(REG32 (0xE000000C)))
 321 
 322 
 323 /*##############################################################################
 324 ## SCB - System Control Block
 325 ##############################################################################*/
 326 
 327 #define SCB_EXTINT      (*(REG32 (0xE01FC140)))
 328 #define SCB_EXTWAKE     (*(REG32 (0xE01FC144)))
 329 #define SCB_EXTMODE     (*(REG32 (0xE01FC148)))
 330 #define SCB_EXTPOLAR    (*(REG32 (0xE01FC14C)))
 331 #define SCB_MEMMAP      (*(REG32 (0xE01FC040)))
 332 #define SCB_PLLCON      (*(REG32 (0xE01FC080)))
 333 #define SCB_PLLCFG      (*(REG32 (0xE01FC084)))
 334 #define SCB_PLLSTAT     (*(REG32 (0xE01FC088)))
 335 #define SCB_PLLFEED     (*(REG32 (0xE01FC08C)))
 336 #define SCB_PCON        (*(REG32 (0xE01FC0C0)))
 337 #define SCB_PCONP       (*(REG32 (0xE01FC0C4)))
 338 #define SCB_VPBDIV      (*(REG32 (0xE01FC100)))
 339 
 340 
 341 /*##############################################################################
 342 ## MAM - Memory Accelerator Module
 343 ##############################################################################*/
 344 
 345 #define MAM_MAMCR       (*(REG32 (0xE01FC000)))
 346 #define MAM_MAMTIM      (*(REG32 (0xE01FC004)))
 347 #define MAM_MAMMAP      (*(REG32 (0xE01FC040)))
 348 
 349 
 350 #endif /* lpc2114_h */
 351