Specifying Target Machine and Compiler Version
The usual way to run GCC is to run the executable called gcc, or
<machine>-gcc when cross-compiling, or
<machine>-gcc-<version> to run a version other than the one that
was installed last. Sometimes this is inconvenient, so GCC provides
options that will switch to another cross-compiler or version.
- -b machine
-
The argument machine specifies the target machine for compilation.
The value to use for machine is the same as was specified as the
machine type when configuring GCC as a cross-compiler. For
example, if a cross-compiler was configured with configure
i386v, meaning to compile for an 80386 running System V, then you
would specify -b i386v to run that cross compiler.
- -V version
-
The argument version specifies which version of GCC to run.
This is useful when multiple versions are installed. For example,
version might be 2.0, meaning to run GCC version 2.0.
The -V and -b options work by running the
<machine>-gcc-<version> executable, so there's no real reason to
use them if you can just run that directly.
Hardware Models and Configurations
Earlier we discussed the standard option -b which chooses among
different installed compilers for completely different target
machines, such as VAX vs. 68000 vs. 80386.
In addition, each of these target machine types can have its own
special options, starting with -m, to choose among various
hardware models or configurations---for example, 68010 vs 68020,
floating coprocessor or none. A single installed version of the
compiler can compile for any model or configuration, according to the
options specified.
Some configurations of the compiler also support additional special
options, usually for compatibility with other compilers on the same
platform.
These options are defined by the macro "TARGET_SWITCHES" in the
machine description. The default for the options is also defined by
that macro, which enables you to change the defaults.
M680x0 Options
These are the -m options defined for the 68000 series. The default
values for these options depends on which style of 68000 was selected when
the compiler was configured; the defaults for the most common choices are
given below.
- -m68000
-
- -mc68000
-
Generate output for a 68000. This is the default
when the compiler is configured for 68000-based systems.
Use this option for microcontrollers with a 68000 or EC000 core,
including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
- -m68020
-
- -mc68020
-
Generate output for a 68020. This is the default
when the compiler is configured for 68020-based systems.
- -m68881
-
Generate output containing 68881 instructions for floating point.
This is the default for most 68020 systems unless --nfp was
specified when the compiler was configured.
- -m68030
-
Generate output for a 68030. This is the default when the compiler is
configured for 68030-based systems.
- -m68040
-
Generate output for a 68040. This is the default when the compiler is
configured for 68040-based systems.
This option inhibits the use of 68881/68882 instructions that have to be
emulated by software on the 68040. Use this option if your 68040 does not
have code to emulate those instructions.
- -m68060
-
Generate output for a 68060. This is the default when the compiler is
configured for 68060-based systems.
This option inhibits the use of 68020 and 68881/68882 instructions that
have to be emulated by software on the 68060. Use this option if your 68060
does not have code to emulate those instructions.
- -mcpu32
-
Generate output for a CPU32. This is the default
when the compiler is configured for CPU32-based systems.
Use this option for microcontrollers with a
CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334,
68336, 68340, 68341, 68349 and 68360.
- -m5200
-
Generate output for a 520X ``coldfire'' family cpu. This is the default
when the compiler is configured for 520X-based systems.
Use this option for microcontroller with a 5200 core, including
the MCF5202, MCF5203, MCF5204 and MCF5202.
- -m68020-40
-
Generate output for a 68040, without using any of the new instructions.
This results in code which can run relatively efficiently on either a
68020/68881 or a 68030 or a 68040. The generated code does use the
68881 instructions that are emulated on the 68040.
- -m68020-60
-
Generate output for a 68060, without using any of the new instructions.
This results in code which can run relatively efficiently on either a
68020/68881 or a 68030 or a 68040. The generated code does use the
68881 instructions that are emulated on the 68060.
- -msoft-float
-
Generate output containing library calls for floating point.
Warning: the requisite libraries are not available for all m68k
targets. Normally the facilities of the machine's usual C compiler are
used, but this can't be done directly in cross-compilation. You must
make your own arrangements to provide suitable library functions for
cross-compilation. The embedded targets m68k-*-aout and
m68k-*-coff do provide software floating point support.
- -mshort
-
Consider type "int" to be 16 bits wide, like "short int".
- -mnobitfield
-
Do not use the bit-field instructions. The -m68000, -mcpu32
and -m5200 options imply -mnobitfield.
- -mbitfield
-
Do use the bit-field instructions. The -m68020 option implies
-mbitfield. This is the default if you use a configuration
designed for a 68020.
- -mrtd
-
Use a different function-calling convention, in which functions
that take a fixed number of arguments return with the "rtd"
instruction, which pops their arguments while returning. This
saves one instruction in the caller since there is no need to pop
the arguments there.
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including "printf");
otherwise incorrect code will be generated for calls to those
functions.
In addition, seriously incorrect code will result if you call a
function with too many arguments. (Normally, extra arguments are
harmlessly ignored.)
The "rtd" instruction is supported by the 68010, 68020, 68030,
68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
- -malign-int
-
- -mno-align-int
-
Control whether GCC aligns "int", "long", "long long",
"float", "double", and "long double" variables on a 32-bit
boundary (-malign-int) or a 16-bit boundary (-mno-align-int).
Aligning variables on 32-bit boundaries produces code that runs somewhat
faster on processors with 32-bit busses at the expense of more memory.
Warning: if you use the -malign-int switch, GCC will
align structures containing the above types differently than
most published application binary interface specifications for the m68k.
- -mpcrel
-
Use the pc-relative addressing mode of the 68000 directly, instead of
using a global offset table. At present, this option implies -fpic,
allowing at most a 16-bit offset for pc-relative addressing. -fPIC is
not presently supported with -mpcrel, though this could be supported for
68020 and higher processors.
- -mno-strict-align
-
- -mstrict-align
-
Do not (do) assume that unaligned memory references will be handled by
the system.
- -msep-data
-
Generate code that allows the data segment to be located in a different
area of memory from the text segment. This allows for execute in place in
an environment without virtual memory management. This option implies -fPIC.
- -mno-sep-data
-
Generate code that assumes that the data segment follows the text segment.
This is the default.
- -mid-shared-library
-
Generate code that supports shared libraries via the library ID method.
This allows for execute in place and shared libraries in an environment
without virtual memory management. This option implies -fPIC.
- -mno-id-shared-library
-
Generate code that doesn't assume ID based shared libraries are being used.
This is the default.
- -mshared-library-id=n
-
Specified the identification number of the ID based shared library being
compiled. Specifying a value of 0 will generate more compact code, specifying
other values will force the allocation of that number to the current
library but is no more space or time efficient than omitting this option.
M68hc1x Options
These are the -m options defined for the 68hc11 and 68hc12
microcontrollers. The default values for these options depends on
which style of microcontroller was selected when the compiler was configured;
the defaults for the most common choices are given below.
- -m6811
-
- -m68hc11
-
Generate output for a 68HC11. This is the default
when the compiler is configured for 68HC11-based systems.
- -m6812
-
- -m68hc12
-
Generate output for a 68HC12. This is the default
when the compiler is configured for 68HC12-based systems.
- -m68S12
-
- -m68hcs12
-
Generate output for a 68HCS12.
- -mauto-incdec
-
Enable the use of 68HC12 pre and post auto-increment and auto-decrement
addressing modes.
- -minmax
-
- -nominmax
-
Enable the use of 68HC12 min and max instructions.
- -mlong-calls
-
- -mno-long-calls
-
Treat all calls as being far away (near). If calls are assumed to be
far away, the compiler will use the "call" instruction to
call a function and the "rtc" instruction for returning.
- -mshort
-
Consider type "int" to be 16 bits wide, like "short int".
- -msoft-reg-count=count
-
Specify the number of pseudo-soft registers which are used for the
code generation. The maximum number is 32. Using more pseudo-soft
register may or may not result in better code depending on the program.
The default is 4 for 68HC11 and 2 for 68HC12.
VAX Options
These -m options are defined for the VAX:
- -munix
-
Do not output certain jump instructions ("aobleq" and so on)
that the Unix assembler for the VAX cannot handle across long
ranges.
- -mgnu
-
Do output those jump instructions, on the assumption that you
will assemble with the GNU assembler.
- -mg
-
Output code for g-format floating point numbers instead of d-format.
SPARC Options
These -m options are supported on the SPARC:
- -mno-app-regs
-
- -mapp-regs
-
Specify -mapp-regs to generate output using the global registers
2 through 4, which the SPARC SVR4 ABI reserves for applications. This
is the default, except on Solaris.
To be fully SVR4 ABI compliant at the cost of some performance loss,
specify -mno-app-regs. You should compile libraries and system
software with this option.
- -mfpu
-
- -mhard-float
-
Generate output containing floating point instructions. This is the
default.
- -mno-fpu
-
- -msoft-float
-
Generate output containing library calls for floating point.
Warning: the requisite libraries are not available for all SPARC
targets. Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation. You must make
your own arrangements to provide suitable library functions for
cross-compilation. The embedded targets sparc-*-aout and
sparclite-*-* do provide software floating point support.
-msoft-float changes the calling convention in the output file;
therefore, it is only useful if you compile all of a program with
this option. In particular, you need to compile libgcc.a, the
library that comes with GCC, with -msoft-float in order for
this to work.
- -mhard-quad-float
-
Generate output containing quad-word (long double) floating point
instructions.
- -msoft-quad-float
-
Generate output containing library calls for quad-word (long double)
floating point instructions. The functions called are those specified
in the SPARC ABI. This is the default.
As of this writing, there are no SPARC implementations that have hardware
support for the quad-word floating point instructions. They all invoke
a trap handler for one of these instructions, and then the trap handler
emulates the effect of the instruction. Because of the trap handler overhead,
this is much slower than calling the ABI library routines. Thus the
-msoft-quad-float option is the default.
- -mno-flat
-
- -mflat
-
With -mflat, the compiler does not generate save/restore instructions
and will use a ``flat'' or single register window calling convention.
This model uses %i7 as the frame pointer and is compatible with the normal
register window model. Code from either may be intermixed.
The local registers and the input registers (0--5) are still treated as
``call saved'' registers and will be saved on the stack as necessary.
With -mno-flat (the default), the compiler emits save/restore
instructions (except for leaf functions) and is the normal mode of operation.
These options are deprecated and will be deleted in a future GCC release.
- -mno-unaligned-doubles
-
- -munaligned-doubles
-
Assume that doubles have 8 byte alignment. This is the default.
With -munaligned-doubles, GCC assumes that doubles have 8 byte
alignment only if they are contained in another type, or if they have an
absolute address. Otherwise, it assumes they have 4 byte alignment.
Specifying this option avoids some rare compatibility problems with code
generated by other compilers. It is not the default because it results
in a performance loss, especially for floating point code.
- -mno-faster-structs
-
- -mfaster-structs
-
With -mfaster-structs, the compiler assumes that structures
should have 8 byte alignment. This enables the use of pairs of
"ldd" and "std" instructions for copies in structure
assignment, in place of twice as many "ld" and "st" pairs.
However, the use of this changed alignment directly violates the SPARC
ABI. Thus, it's intended only for use on targets where the developer
acknowledges that their resulting code will not be directly in line with
the rules of the ABI.
- -mimpure-text
-
-mimpure-text, used in addition to -shared, tells
the compiler to not pass -z text to the linker when linking a
shared object. Using this option, you can link position-dependent
code into a shared object.
-mimpure-text suppresses the ``relocations remain against
allocatable but non-writable sections'' linker error message.
However, the necessary relocations will trigger copy-on-write, and the
shared object is not actually shared across processes. Instead of
using -mimpure-text, you should compile all source code with
-fpic or -fPIC.
This option is only available on SunOS and Solaris.
- -mv8
-
- -msparclite
-
These two options select variations on the SPARC architecture.
These options are deprecated and will be deleted in a future GCC release.
They have been replaced with -mcpu=xxx.
- -mcypress
-
- -msupersparc
-
- -mf930
-
- -mf934
-
These four options select the processor for which the code is optimized.
These options are deprecated and will be deleted in a future GCC release.
They have been replaced with -mcpu=xxx.
- -mcpu=cpu_type
-
Set the instruction set, register set, and instruction scheduling parameters
for machine type cpu_type. Supported values for cpu_type are
v7, cypress, v8, supersparc, sparclite,
f930, f934, hypersparc, sparclite86x,
sparclet, tsc701, v9, ultrasparc, and
ultrasparc3.
Default instruction scheduling parameters are used for values that select
an architecture and not an implementation. These are v7, v8,
sparclite, sparclet, v9.
Here is a list of each supported architecture and their supported
implementations.
v7: cypress
v8: supersparc, hypersparc
sparclite: f930, f934, sparclite86x
sparclet: tsc701
v9: ultrasparc, ultrasparc3
By default (unless configured otherwise), GCC generates code for the V7
variant of the SPARC architecture. With -mcpu=cypress, the compiler
additionally optimizes it for the Cypress CY7C602 chip, as used in the
SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
SPARCStation 1, 2, IPX etc.
With -mcpu=v8, GCC generates code for the V8 variant of the SPARC
architecture. The only difference from V7 code is that the compiler emits
the integer multiply and integer divide instructions which exist in SPARC-V8
but not in SPARC-V7. With -mcpu=supersparc, the compiler additionally
optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
2000 series.
With -mcpu=sparclite, GCC generates code for the SPARClite variant of
the SPARC architecture. This adds the integer multiply, integer divide step
and scan ("ffs") instructions which exist in SPARClite but not in SPARC-V7.
With -mcpu=f930, the compiler additionally optimizes it for the
Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
-mcpu=f934, the compiler additionally optimizes it for the Fujitsu
MB86934 chip, which is the more recent SPARClite with FPU.
With -mcpu=sparclet, GCC generates code for the SPARClet variant of
the SPARC architecture. This adds the integer multiply, multiply/accumulate,
integer divide step and scan ("ffs") instructions which exist in SPARClet
but not in SPARC-V7. With -mcpu=tsc701, the compiler additionally
optimizes it for the TEMIC SPARClet chip.
With -mcpu=v9, GCC generates code for the V9 variant of the SPARC
architecture. This adds 64-bit integer and floating-point move instructions,
3 additional floating-point condition code registers and conditional move
instructions. With -mcpu=ultrasparc, the compiler additionally
optimizes it for the Sun UltraSPARC I/II chips. With
-mcpu=ultrasparc3, the compiler additionally optimizes it for the
Sun UltraSPARC III chip.
- -mtune=cpu_type
-
Set the instruction scheduling parameters for machine type
cpu_type, but do not set the instruction set or register set that the
option -mcpu=cpu_type would.
The same values for -mcpu=cpu_type can be used for
-mtune=cpu_type, but the only useful values are those
that select a particular cpu implementation. Those are cypress,
supersparc, hypersparc, f930, f934,
sparclite86x, tsc701, ultrasparc, and
ultrasparc3.
- -mv8plus
-
- -mno-v8plus
-
With -mv8plus, GCC generates code for the SPARC-V8+ ABI. The
difference from the V8 ABI is that the global and out registers are
considered 64-bit wide. This is enabled by default on Solaris in 32-bit
mode for all SPARC-V9 processors.
- -mvis
-
- -mno-vis
-
With -mvis, GCC generates code that takes advantage of the UltraSPARC
Visual Instruction Set extensions. The default is -mno-vis.
These -m options are supported in addition to the above
on SPARC-V9 processors in 64-bit environments:
- -mlittle-endian
-
Generate code for a processor running in little-endian mode. It is only
available for a few configurations and most notably not on Solaris and Linux.
- -m32
-
- -m64
-
Generate code for a 32-bit or 64-bit environment.
The 32-bit environment sets int, long and pointer to 32 bits.
The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits.
- -mcmodel=medlow
-
Generate code for the Medium/Low code model: 64-bit addresses, programs
must be linked in the low 32 bits of memory. Programs can be statically
or dynamically linked.
- -mcmodel=medmid
-
Generate code for the Medium/Middle code model: 64-bit addresses, programs
must be linked in the low 44 bits of memory, the text and data segments must
be less than 2GB in size and the data segment must be located within 2GB of
the text segment.
- -mcmodel=medany
-
Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
may be linked anywhere in memory, the text and data segments must be less
than 2GB in size and the data segment must be located within 2GB of the
text segment.
- -mcmodel=embmedany
-
Generate code for the Medium/Anywhere code model for embedded systems:
64-bit addresses, the text and data segments must be less than 2GB in
size, both starting anywhere in memory (determined at link time). The
global register %g4 points to the base of the data segment. Programs
are statically linked and PIC is not supported.
- -mstack-bias
-
- -mno-stack-bias
-
With -mstack-bias, GCC assumes that the stack pointer, and
frame pointer if present, are offset by -2047 which must be added back
when making stack frame references. This is the default in 64-bit mode.
Otherwise, assume no such offset is present.
These switches are supported in addition to the above on Solaris:
- -threads
-
Add support for multithreading using the Solaris threads library. This
option sets flags for both the preprocessor and linker. This option does
not affect the thread safety of object code produced by the compiler or
that of libraries supplied with it.
- -pthreads
-
Add support for multithreading using the POSIX threads library. This
option sets flags for both the preprocessor and linker. This option does
not affect the thread safety of object code produced by the compiler or
that of libraries supplied with it.
ARM Options
These -m options are defined for Advanced RISC Machines (ARM)
architectures:
- -mapcs-frame
-
Generate a stack frame that is compliant with the ARM Procedure Call
Standard for all functions, even if this is not strictly necessary for
correct execution of the code. Specifying -fomit-frame-pointer
with this option will cause the stack frames not to be generated for
leaf functions. The default is -mno-apcs-frame.
- -mapcs
-
This is a synonym for -mapcs-frame.
- -mapcs-26
-
Generate code for a processor running with a 26-bit program counter,
and conforming to the function calling standards for the APCS 26-bit
option.
This option is deprecated. Future releases of the GCC will only support
generating code that runs in apcs-32 mode.
- -mapcs-32
-
Generate code for a processor running with a 32-bit program counter,
and conforming to the function calling standards for the APCS 32-bit
option.
This flag is deprecated. Future releases of GCC will make this flag
unconditional.
- -mthumb-interwork
-
Generate code which supports calling between the ARM and Thumb
instruction sets. Without this option the two instruction sets cannot
be reliably used inside one program. The default is
-mno-thumb-interwork, since slightly larger code is generated
when -mthumb-interwork is specified.
- -mno-sched-prolog
-
Prevent the reordering of instructions in the function prolog, or the
merging of those instruction with the instructions in the function's
body. This means that all functions will start with a recognizable set
of instructions (or in fact one of a choice from a small set of
different function prologues), and this information can be used to
locate the start if functions inside an executable piece of code. The
default is -msched-prolog.
- -mhard-float
-
Generate output containing floating point instructions. This is the
default.
- -msoft-float
-
Generate output containing library calls for floating point.
Warning: the requisite libraries are not available for all ARM
targets. Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation. You must make
your own arrangements to provide suitable library functions for
cross-compilation.
-msoft-float changes the calling convention in the output file;
therefore, it is only useful if you compile all of a program with
this option. In particular, you need to compile libgcc.a, the
library that comes with GCC, with -msoft-float in order for
this to work.
- -mlittle-endian
-
Generate code for a processor running in little-endian mode. This is
the default for all standard configurations.
- -mbig-endian
-
Generate code for a processor running in big-endian mode; the default is
to compile code for a little-endian processor.
- -mwords-little-endian
-
This option only applies when generating code for big-endian processors.
Generate code for a little-endian word order but a big-endian byte
order. That is, a byte order of the form 32107654. Note: this
option should only be used if you require compatibility with code for
big-endian ARM processors generated by versions of the compiler prior to
2.8.
- -malignment-traps
-
Generate code that will not trap if the MMU has alignment traps enabled.
On ARM architectures prior to ARMv4, there were no instructions to
access half-word objects stored in memory. However, when reading from
memory a feature of the ARM architecture allows a word load to be used,
even if the address is unaligned, and the processor core will rotate the
data as it is being loaded. This option tells the compiler that such
misaligned accesses will cause a MMU trap and that it should instead
synthesize the access as a series of byte accesses. The compiler can
still use word accesses to load half-word data if it knows that the
address is aligned to a word boundary.
This option has no effect when compiling for ARM architecture 4 or later,
since these processors have instructions to directly access half-word
objects in memory.
- -mno-alignment-traps
-
Generate code that assumes that the MMU will not trap unaligned
accesses. This produces better code when the target instruction set
does not have half-word memory operations (i.e. implementations prior to
ARMv4).
Note that you cannot use this option to access unaligned word objects,
since the processor will only fetch one 32-bit aligned object from
memory.
The default setting is -malignment-traps, since this produces
code that will also run on processors implementing ARM architecture
version 6 or later.
This option is deprecated and will be removed in the next release of GCC.
- -mcpu=name
-
This specifies the name of the target ARM processor. GCC uses this name
to determine what kind of instructions it can emit when generating
assembly code. Permissible names are: arm2, arm250,
arm3, arm6, arm60, arm600, arm610,
arm620, arm7, arm7m, arm7d, arm7dm,
arm7di, arm7dmi, arm70, arm700,
arm700i, arm710, arm710c, arm7100,
arm7500, arm7500fe, arm7tdmi, arm8,
strongarm, strongarm110, strongarm1100,
arm8, arm810, arm9, arm9e, arm920,
arm920t, arm926ejs, arm940t, arm9tdmi,
arm10tdmi, arm1020t, arm1026ejs,
arm1136js, arm1136jfs ,xscale, iwmmxt,
ep9312.
- -mtune=name
-
This option is very similar to the -mcpu= option, except that
instead of specifying the actual target processor type, and hence
restricting which instructions can be used, it specifies that GCC should
tune the performance of the code as if the target were of the type
specified in this option, but still choosing the instructions that it
will generate based on the cpu specified by a -mcpu= option.
For some ARM implementations better performance can be obtained by using
this option.
- -march=name
-
This specifies the name of the target ARM architecture. GCC uses this
name to determine what kind of instructions it can emit when generating
assembly code. This option can be used in conjunction with or instead
of the -mcpu= option. Permissible names are: armv2,
armv2a, armv3, armv3m, armv4, armv4t,
armv5, armv5t, armv5te, armv6j,
iwmmxt, ep9312.
- -mfpe=number
-
- -mfp=number
-
This specifies the version of the floating point emulation available on
the target. Permissible values are 2 and 3. -mfp= is a synonym
for -mfpe=, for compatibility with older versions of GCC.
- -mstructure-size-boundary=n
-
The size of all structures and unions will be rounded up to a multiple
of the number of bits set by this option. Permissible values are 8 and
32. The default value varies for different toolchains. For the COFF
targeted toolchain the default value is 8. Specifying the larger number
can produce faster, more efficient code, but can also increase the size
of the program. The two values are potentially incompatible. Code
compiled with one value cannot necessarily expect to work with code or
libraries compiled with the other value, if they exchange information
using structures or unions.
- -mabort-on-noreturn
-
Generate a call to the function "abort" at the end of a
"noreturn" function. It will be executed if the function tries to
return.
- -mlong-calls
-
- -mno-long-calls
-
Tells the compiler to perform function calls by first loading the
address of the function into a register and then performing a subroutine
call on this register. This switch is needed if the target function
will lie outside of the 64 megabyte addressing range of the offset based
version of subroutine call instruction.
Even if this switch is enabled, not all function calls will be turned
into long calls. The heuristic is that static functions, functions
which have the short-call attribute, functions that are inside
the scope of a #pragma no_long_calls directive and functions whose
definitions have already been compiled within the current compilation
unit, will not be turned into long calls. The exception to this rule is
that weak function definitions, functions with the long-call
attribute or the section attribute, and functions that are within
the scope of a #pragma long_calls directive, will always be
turned into long calls.
This feature is not enabled by default. Specifying
-mno-long-calls will restore the default behavior, as will
placing the function calls within the scope of a #pragma
long_calls_off directive. Note these switches have no effect on how
the compiler generates code to handle function calls via function
pointers.
- -mnop-fun-dllimport
-
Disable support for the "dllimport" attribute.
- -msingle-pic-base
-
Treat the register used for PIC addressing as read-only, rather than
loading it in the prologue for each function. The run-time system is
responsible for initializing this register with an appropriate value
before execution begins.
- -mpic-register=reg
-
Specify the register to be used for PIC addressing. The default is R10
unless stack-checking is enabled, when R9 is used.
- -mcirrus-fix-invalid-insns
-
Insert NOPs into the instruction stream to in order to work around
problems with invalid Maverick instruction combinations. This option
is only valid if the -mcpu=ep9312 option has been used to
enable generation of instructions for the Cirrus Maverick floating
point co-processor. This option is not enabled by default, since the
problem is only present in older Maverick implementations. The default
can be re-enabled by use of the -mno-cirrus-fix-invalid-insns
switch.
- -mpoke-function-name
-
Write the name of each function into the text section, directly
preceding the function prologue. The generated code is similar to this:
t0
.ascii "arm_poke_function_name", 0
.align
t1
.word 0xff000000 + (t1 - t0)
arm_poke_function_name
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
When performing a stack backtrace, code can inspect the value of
"pc" stored at "fp + 0". If the trace function then looks at
location "pc - 12" and the top 8 bits are set, then we know that
there is a function name embedded immediately preceding this location
and has length "((pc[-3]) & 0xff000000)".
- -mthumb
-
Generate code for the 16-bit Thumb instruction set. The default is to
use the 32-bit ARM instruction set.
- -mtpcs-frame
-
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all non-leaf functions. (A leaf function is one that does
not call any other functions.) The default is -mno-tpcs-frame.
- -mtpcs-leaf-frame
-
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all leaf functions. (A leaf function is one that does
not call any other functions.) The default is -mno-apcs-leaf-frame.
- -mcallee-super-interworking
-
Gives all externally visible functions in the file being compiled an ARM
instruction set header which switches to Thumb mode before executing the
rest of the function. This allows these functions to be called from
non-interworking code.
- -mcaller-super-interworking
-
Allows calls via function pointers (including virtual functions) to
execute correctly regardless of whether the target code has been
compiled for interworking or not. There is a small overhead in the cost
of executing a function pointer if this option is enabled.
MN10300 Options
These -m options are defined for Matsushita MN10300 architectures:
- -mmult-bug
-
Generate code to avoid bugs in the multiply instructions for the MN10300
processors. This is the default.
- -mno-mult-bug
-
Do not generate code to avoid bugs in the multiply instructions for the
MN10300 processors.
- -mam33
-
Generate code which uses features specific to the AM33 processor.
- -mno-am33
-
Do not generate code which uses features specific to the AM33 processor. This
is the default.
- -mno-crt0
-
Do not link in the C run-time initialization object file.
- -mrelax
-
Indicate to the linker that it should perform a relaxation optimization pass
to shorten branches, calls and absolute memory addresses. This option only
has an effect when used on the command line for the final link step.
This option makes symbolic debugging impossible.
M32R/D Options
These -m options are defined for Renesas M32R/D architectures:
- -m32r2
-
Generate code for the M32R/2.
- -m32rx
-
Generate code for the M32R/X.
- -m32r
-
Generate code for the M32R. This is the default.
- -mmodel=small
-
Assume all objects live in the lower 16MB of memory (so that their addresses
can be loaded with the "ld24" instruction), and assume all subroutines
are reachable with the "bl" instruction.
This is the default.
The addressability of a particular object can be set with the
"model" attribute.
- -mmodel=medium
-
Assume objects may be anywhere in the 32-bit address space (the compiler
will generate "seth/add3" instructions to load their addresses), and
assume all subroutines are reachable with the "bl" instruction.
- -mmodel=large
-
Assume objects may be anywhere in the 32-bit address space (the compiler
will generate "seth/add3" instructions to load their addresses), and
assume subroutines may not be reachable with the "bl" instruction
(the compiler will generate the much slower "seth/add3/jl"
instruction sequence).
- -msdata=none
-
Disable use of the small data area. Variables will be put into
one of .data, bss, or .rodata (unless the
"section" attribute has been specified).
This is the default.
The small data area consists of sections .sdata and .sbss.
Objects may be explicitly put in the small data area with the
"section" attribute using one of these sections.
- -msdata=sdata
-
Put small global and static data in the small data area, but do not
generate special code to reference them.
- -msdata=use
-
Put small global and static data in the small data area, and generate
special instructions to reference them.
- -G num
-
Put global and static objects less than or equal to num bytes
into the small data or bss sections instead of the normal data or bss
sections. The default value of num is 8.
The -msdata option must be set to one of sdata or use
for this option to have any effect.
All modules should be compiled with the same -G num value.
Compiling with different values of num may or may not work; if it
doesn't the linker will give an error message---incorrect code will not be
generated.
- -mdebug
-
Makes the M32R specific code in the compiler display some statistics
that might help in debugging programs.
- -malign-loops
-
Align all loops to a 32-byte boundary.
- -mno-align-loops
-
Do not enforce a 32-byte alignment for loops. This is the default.
- -missue-rate=number
-
Issue number instructions per cycle. number can only be 1
or 2.
- -mbranch-cost=number
-
number can only be 1 or 2. If it is 1 then branches will be
preferred over conditional code, if it is 2, then the opposite will
apply.
- -mflush-trap=number
-
Specifies the trap number to use to flush the cache. The default is
12. Valid numbers are between 0 and 15 inclusive.
- -mno-flush-trap
-
Specifies that the cache cannot be flushed by using a trap.
- -mflush-func=name
-
Specifies the name of the operating system function to call to flush
the cache. The default is _flush_cache, but a function call
will only be used if a trap is not available.
- -mno-flush-func
-
Indicates that there is no OS function for flushing the cache.
IBM RS/6000 and PowerPC Options
These -m options are defined for the IBM RS/6000 and PowerPC:
- -mpower
-
- -mno-power
-
- -mpower2
-
- -mno-power2
-
- -mpowerpc
-
- -mno-powerpc
-
- -mpowerpc-gpopt
-
- -mno-powerpc-gpopt
-
- -mpowerpc-gfxopt
-
- -mno-powerpc-gfxopt
-
- -mpowerpc64
-
- -mno-powerpc64
-
GCC supports two related instruction set architectures for the
RS/6000 and PowerPC. The POWER instruction set are those
instructions supported by the rios chip set used in the original
RS/6000 systems and the PowerPC instruction set is the
architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
the IBM 4xx microprocessors.
Neither architecture is a subset of the other. However there is a
large common subset of instructions supported by both. An MQ
register is included in processors supporting the POWER architecture.
You use these options to specify which instructions are available on the
processor you are using. The default value of these options is
determined when configuring GCC. Specifying the
-mcpu=cpu_type overrides the specification of these
options. We recommend you use the -mcpu=cpu_type option
rather than the options listed above.
The -mpower option allows GCC to generate instructions that
are found only in the POWER architecture and to use the MQ register.
Specifying -mpower2 implies -power and also allows GCC
to generate instructions that are present in the POWER2 architecture but
not the original POWER architecture.
The -mpowerpc option allows GCC to generate instructions that
are found only in the 32-bit subset of the PowerPC architecture.
Specifying -mpowerpc-gpopt implies -mpowerpc and also allows
GCC to use the optional PowerPC architecture instructions in the
General Purpose group, including floating-point square root. Specifying
-mpowerpc-gfxopt implies -mpowerpc and also allows GCC to
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
The -mpowerpc64 option allows GCC to generate the additional
64-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
-mno-powerpc64.
If you specify both -mno-power and -mno-powerpc, GCC
will use only the instructions in the common subset of both
architectures plus some special AIX common-mode calls, and will not use
the MQ register. Specifying both -mpower and -mpowerpc
permits GCC to use any instruction from either architecture and to
allow use of the MQ register; specify this for the Motorola MPC601.
- -mnew-mnemonics
-
- -mold-mnemonics
-
Select which mnemonics to use in the generated assembler code. With
-mnew-mnemonics, GCC uses the assembler mnemonics defined for
the PowerPC architecture. With -mold-mnemonics it uses the
assembler mnemonics defined for the POWER architecture. Instructions
defined in only one architecture have only one mnemonic; GCC uses that
mnemonic irrespective of which of these options is specified.
GCC defaults to the mnemonics appropriate for the architecture in
use. Specifying -mcpu=cpu_type sometimes overrides the
value of these option. Unless you are building a cross-compiler, you
should normally not specify either -mnew-mnemonics or
-mold-mnemonics, but should instead accept the default.
- -mcpu=cpu_type
-
Set architecture type, register usage, choice of mnemonics, and
instruction scheduling parameters for machine type cpu_type.
Supported values for cpu_type are 401, 403,
405, 405fp, 440, 440fp, 505,
601, 602, 603, 603e, 604,
604e, 620, 630, 740, 7400,
7450, 750, 801, 821, 823,
860, 970, 8540, common, ec603e, G3,
G4, G5, power, power2, power3,
power4, power5, powerpc, powerpc64,
rios, rios1, rios2, rsc, and rs64a.
-mcpu=common selects a completely generic processor. Code
generated under this option will run on any POWER or PowerPC processor.
GCC will use only the instructions in the common subset of both
architectures, and will not use the MQ register. GCC assumes a generic
processor model for scheduling purposes.
-mcpu=power, -mcpu=power2, -mcpu=powerpc, and
-mcpu=powerpc64 specify generic POWER, POWER2, pure 32-bit
PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine
types, with an appropriate, generic processor model assumed for
scheduling purposes.
The other options specify a specific processor. Code generated under
those options will run best on that processor, and may not run at all on
others.
The -mcpu options automatically enable or disable the
following options: -maltivec, -mhard-float,
-mmfcrf, -mmultiple, -mnew-mnemonics,
-mpower, -mpower2, -mpowerpc64,
-mpowerpc-gpopt, -mpowerpc-gfxopt,
-mstring. The particular options set for any particular CPU
will vary between compiler versions, depending on what setting seems
to produce optimal code for that CPU; it doesn't necessarily reflect
the actual hardware's capabilities. If you wish to set an individual
option to a particular value, you may specify it after the
-mcpu option, like -mcpu=970 -mno-altivec.
On AIX, the -maltivec and -mpowerpc64 options are
not enabled or disabled by the -mcpu option at present, since
AIX does not have full support for these options. You may still
enable or disable them individually if you're sure it'll work in your
environment.
- -mtune=cpu_type
-
Set the instruction scheduling parameters for machine type
cpu_type, but do not set the architecture type, register usage, or
choice of mnemonics, as -mcpu=cpu_type would. The same
values for cpu_type are used for -mtune as for
-mcpu. If both are specified, the code generated will use the
architecture, registers, and mnemonics set by -mcpu, but the
scheduling parameters set by -mtune.
- -maltivec
-
- -mno-altivec
-
These switches enable or disable the use of built-in functions that
allow access to the AltiVec instruction set. You may also need to set
-mabi=altivec to adjust the current ABI with AltiVec ABI
enhancements.
- -mabi=spe
-
Extend the current ABI with SPE ABI extensions. This does not change
the default ABI, instead it adds the SPE ABI extensions to the current
ABI.
- -mabi=no-spe
-
Disable Booke SPE ABI extensions for the current ABI.
- -misel=yes/no
-
- -misel
-
This switch enables or disables the generation of ISEL instructions.
- -mspe=yes/no
-
- -mspe
-
This switch enables or disables the generation of SPE simd
instructions.
- -mfloat-gprs=yes/no
-
- -mfloat-gprs
-
This switch enables or disables the generation of floating point
operations on the general purpose registers for architectures that
support it. This option is currently only available on the MPC8540.
- -mfull-toc
-
- -mno-fp-in-toc
-
- -mno-sum-in-toc
-
- -mminimal-toc
-
Modify generation of the TOC (Table Of Contents), which is created for
every executable file. The -mfull-toc option is selected by
default. In that case, GCC will allocate at least one TOC entry for
each unique non-automatic variable reference in your program. GCC
will also place floating-point constants in the TOC. However, only
16,384 entries are available in the TOC.
If you receive a linker error message that saying you have overflowed
the available TOC space, you can reduce the amount of TOC space used
with the -mno-fp-in-toc and -mno-sum-in-toc options.
-mno-fp-in-toc prevents GCC from putting floating-point
constants in the TOC and -mno-sum-in-toc forces GCC to
generate code to calculate the sum of an address and a constant at
run-time instead of putting that sum into the TOC. You may specify one
or both of these options. Each causes GCC to produce very slightly
slower and larger code at the expense of conserving TOC space.
If you still run out of space in the TOC even when you specify both of
these options, specify -mminimal-toc instead. This option causes
GCC to make only one TOC entry for every file. When you specify this
option, GCC will produce code that is slower and larger but which
uses extremely little TOC space. You may wish to use this option
only on files that contain less frequently executed code.
- -maix64
-
- -maix32
-
Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
"long" type, and the infrastructure needed to support them.
Specifying -maix64 implies -mpowerpc64 and
-mpowerpc, while -maix32 disables the 64-bit ABI and
implies -mno-powerpc64. GCC defaults to -maix32.
- -mxl-compat
-
- -mno-xl-compat
-
Produce code that conforms more closely to IBM XLC semantics when using
AIX-compatible ABI. Pass floating-point arguments to prototyped
functions beyond the register save area (RSA) on the stack in addition
to argument FPRs. Do not assume that most significant double in 128
bit long double value is properly rounded when comparing values.
The AIX calling convention was extended but not initially documented to
handle an obscure K&R C case of calling a function that takes the
address of its arguments with fewer arguments than declared. AIX XL
compilers access floating point arguments which do not fit in the
RSA from the stack when a subroutine is compiled without
optimization. Because always storing floating-point arguments on the
stack is inefficient and rarely needed, this option is not enabled by
default and only is necessary when calling subroutines compiled by AIX
XL compilers without optimization.
- -mpe
-
Support IBM RS/6000 SP Parallel Environment (PE). Link an
application written to use message passing with special startup code to
enable the application to run. The system must have PE installed in the
standard location (/usr/lpp/ppe.poe/), or the specs file
must be overridden with the -specs= option to specify the
appropriate directory location. The Parallel Environment does not
support threads, so the -mpe option and the -pthread
option are incompatible.
- -malign-natural
-
- -malign-power
-
On AIX, Darwin, and 64-bit PowerPC GNU/Linux, the option
-malign-natural overrides the ABI-defined alignment of larger
types, such as floating-point doubles, on their natural size-based boundary.
The option -malign-power instructs GCC to follow the ABI-specified
alignment rules. GCC defaults to the standard alignment defined in the ABI.
- -msoft-float
-
- -mhard-float
-
Generate code that does not use (uses) the floating-point register set.
Software floating point emulation is provided if you use the
-msoft-float option, and pass the option to GCC when linking.
- -mmultiple
-
- -mno-multiple
-
Generate code that uses (does not use) the load multiple word
instructions and the store multiple word instructions. These
instructions are generated by default on POWER systems, and not
generated on PowerPC systems. Do not use -mmultiple on little
endian PowerPC systems, since those instructions do not work when the
processor is in little endian mode. The exceptions are PPC740 and
PPC750 which permit the instructions usage in little endian mode.
- -mstring
-
- -mno-string
-
Generate code that uses (does not use) the load string instructions
and the store string word instructions to save multiple registers and
do small block moves. These instructions are generated by default on
POWER systems, and not generated on PowerPC systems. Do not use
-mstring on little endian PowerPC systems, since those
instructions do not work when the processor is in little endian mode.
The exceptions are PPC740 and PPC750 which permit the instructions
usage in little endian mode.
- -mupdate
-
- -mno-update
-
Generate code that uses (does not use) the load or store instructions
that update the base register to the address of the calculated memory
location. These instructions are generated by default. If you use
-mno-update, there is a small window between the time that the
stack pointer is updated and the address of the previous frame is
stored, which means code that walks the stack frame across interrupts or
signals may get corrupted data.
- -mfused-madd
-
- -mno-fused-madd
-
Generate code that uses (does not use) the floating point multiply and
accumulate instructions. These instructions are generated by default if
hardware floating is used.
- -mno-bit-align
-
- -mbit-align
-
On System V.4 and embedded PowerPC systems do not (do) force structures
and unions that contain bit-fields to be aligned to the base type of the
bit-field.
For example, by default a structure containing nothing but 8
"unsigned" bit-fields of length 1 would be aligned to a 4 byte
boundary and have a size of 4 bytes. By using -mno-bit-align,
the structure would be aligned to a 1 byte boundary and be one byte in
size.
- -mno-strict-align
-
- -mstrict-align
-
On System V.4 and embedded PowerPC systems do not (do) assume that
unaligned memory references will be handled by the system.
- -mrelocatable
-
- -mno-relocatable
-
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime. If you
use -mrelocatable on any module, all objects linked together must
be compiled with -mrelocatable or -mrelocatable-lib.
- -mrelocatable-lib
-
- -mno-relocatable-lib
-
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime. Modules
compiled with -mrelocatable-lib can be linked with either modules
compiled without -mrelocatable and -mrelocatable-lib or
with modules compiled with the -mrelocatable options.
- -mno-toc
-
- -mtoc
-
On System V.4 and embedded PowerPC systems do not (do) assume that
register 2 contains a pointer to a global area pointing to the addresses
used in the program.
- -mlittle
-
- -mlittle-endian
-
On System V.4 and embedded PowerPC systems compile code for the
processor in little endian mode. The -mlittle-endian option is
the same as -mlittle.
- -mbig
-
- -mbig-endian
-
On System V.4 and embedded PowerPC systems compile code for the
processor in big endian mode. The -mbig-endian option is
the same as -mbig.
- -mdynamic-no-pic
-
On Darwin and Mac OS X systems, compile code so that it is not
relocatable, but that its external references are relocatable. The
resulting code is suitable for applications, but not shared
libraries.
- -mprioritize-restricted-insns=priority
-
This option controls the priority that is assigned to
dispatch-slot restricted instructions during the second scheduling
pass. The argument priority takes the value 0/1/2 to assign
no/highest/second-highest priority to dispatch slot restricted
instructions.
- -msched-costly-dep=dependence_type
-
This option controls which dependences are considered costly
by the target during instruction scheduling. The argument
dependence_type takes one of the following values:
no: no dependence is costly,
all: all dependences are costly,
true_store_to_load: a true dependence from store to load is costly,
store_to_load: any dependence from store to load is costly,
number: any dependence which latency >= number is costly.
- -minsert-sched-nops=scheme
-
This option controls which nop insertion scheme will be used during
the second scheduling pass. The argument scheme takes one of the
following values:
no: Don't insert nops.
pad: Pad with nops any dispatch group which has vacant issue slots,
according to the scheduler's grouping.
regroup_exact: Insert nops to force costly dependent insns into
separate groups. Insert exactly as many nops as needed to force an insn
to a new group, according to the estimated processor grouping.
number: Insert nops to force costly dependent insns into
separate groups. Insert number nops to force an insn to a new group.
- -mcall-sysv
-
On System V.4 and embedded PowerPC systems compile code using calling
conventions that adheres to the March 1995 draft of the System V
Application Binary Interface, PowerPC processor supplement. This is the
default unless you configured GCC using powerpc-*-eabiaix.
- -mcall-sysv-eabi
-
Specify both -mcall-sysv and -meabi options.
- -mcall-sysv-noeabi
-
Specify both -mcall-sysv and -mno-eabi options.
- -mcall-solaris
-
On System V.4 and embedded PowerPC systems compile code for the Solaris
operating system.
- -mcall-linux
-
On System V.4 and embedded PowerPC systems compile code for the
Linux-based GNU system.
- -mcall-gnu
-
On System V.4 and embedded PowerPC systems compile code for the
Hurd-based GNU system.
- -mcall-netbsd
-
On System V.4 and embedded PowerPC systems compile code for the
NetBSD operating system.
- -maix-struct-return
-
Return all structures in memory (as specified by the AIX ABI).
- -msvr4-struct-return
-
Return structures smaller than 8 bytes in registers (as specified by the
SVR4 ABI).
- -mabi=altivec
-
Extend the current ABI with AltiVec ABI extensions. This does not
change the default ABI, instead it adds the AltiVec ABI extensions to
the current ABI.
- -mabi=no-altivec
-
Disable AltiVec ABI extensions for the current ABI.
- -mprototype
-
- -mno-prototype
-
On System V.4 and embedded PowerPC systems assume that all calls to
variable argument functions are properly prototyped. Otherwise, the
compiler must insert an instruction before every non prototyped call to
set or clear bit 6 of the condition code register (CR) to
indicate whether floating point values were passed in the floating point
registers in case the function takes a variable arguments. With
-mprototype, only calls to prototyped variable argument functions
will set or clear the bit.
- -msim
-
On embedded PowerPC systems, assume that the startup module is called
sim-crt0.o and that the standard C libraries are libsim.a and
libc.a. This is the default for powerpc-*-eabisim.
configurations.
- -mmvme
-
On embedded PowerPC systems, assume that the startup module is called
crt0.o and the standard C libraries are libmvme.a and
libc.a.
- -mads
-
On embedded PowerPC systems, assume that the startup module is called
crt0.o and the standard C libraries are libads.a and
libc.a.
- -myellowknife
-
On embedded PowerPC systems, assume that the startup module is called
crt0.o and the standard C libraries are libyk.a and
libc.a.
- -mvxworks
-
On System V.4 and embedded PowerPC systems, specify that you are
compiling for a VxWorks system.
- -mwindiss
-
Specify that you are compiling for the WindISS simulation environment.
- -memb
-
On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags
header to indicate that eabi extended relocations are used.
- -meabi
-
- -mno-eabi
-
On System V.4 and embedded PowerPC systems do (do not) adhere to the
Embedded Applications Binary Interface (eabi) which is a set of
modifications to the System V.4 specifications. Selecting -meabi
means that the stack is aligned to an 8 byte boundary, a function
"__eabi" is called to from "main" to set up the eabi
environment, and the -msdata option can use both "r2" and
"r13" to point to two separate small data areas. Selecting
-mno-eabi means that the stack is aligned to a 16 byte boundary,
do not call an initialization function from "main", and the
-msdata option will only use "r13" to point to a single
small data area. The -meabi option is on by default if you
configured GCC using one of the powerpc*-*-eabi* options.
- -msdata=eabi
-
On System V.4 and embedded PowerPC systems, put small initialized
"const" global and static data in the .sdata2 section, which
is pointed to by register "r2". Put small initialized
non-"const" global and static data in the .sdata section,
which is pointed to by register "r13". Put small uninitialized
global and static data in the .sbss section, which is adjacent to
the .sdata section. The -msdata=eabi option is
incompatible with the -mrelocatable option. The
-msdata=eabi option also sets the -memb option.
- -msdata=sysv
-
On System V.4 and embedded PowerPC systems, put small global and static
data in the .sdata section, which is pointed to by register
"r13". Put small uninitialized global and static data in the
.sbss section, which is adjacent to the .sdata section.
The -msdata=sysv option is incompatible with the
-mrelocatable option.
- -msdata=default
-
- -msdata
-
On System V.4 and embedded PowerPC systems, if -meabi is used,
compile code the same as -msdata=eabi, otherwise compile code the
same as -msdata=sysv.
- -msdata-data
-
On System V.4 and embedded PowerPC systems, put small global and static
data in the .sdata section. Put small uninitialized global and
static data in the .sbss section. Do not use register "r13"
to address small data however. This is the default behavior unless
other -msdata options are used.
- -msdata=none
-
- -mno-sdata
-
On embedded PowerPC systems, put all initialized global and static data
in the .data section, and all uninitialized data in the
.bss section.
- -G num
-
On embedded PowerPC systems, put global and static items less than or
equal to num bytes into the small data or bss sections instead of
the normal data or bss section. By default, num is 8. The
-G num switch is also passed to the linker.
All modules should be compiled with the same -G num value.
- -mregnames
-
- -mno-regnames
-
On System V.4 and embedded PowerPC systems do (do not) emit register
names in the assembly language output using symbolic forms.
- -mlongcall
-
- -mno-longcall
-
Default to making all function calls via pointers, so that functions
which reside further than 64 megabytes (67,108,864 bytes) from the
current location can be called. This setting can be overridden by the
"shortcall" function attribute, or by "#pragma longcall(0)".
Some linkers are capable of detecting out-of-range calls and generating
glue code on the fly. On these systems, long calls are unnecessary and
generate slower code. As of this writing, the AIX linker can do this,
as can the GNU linker for PowerPC/64. It is planned to add this feature
to the GNU linker for 32-bit PowerPC systems as well.
On Mach-O (Darwin) systems, this option directs the compiler emit to
the glue for every direct call, and the Darwin linker decides whether
to use or discard it.
In the future, we may cause GCC to ignore all longcall specifications
when the linker is known to generate glue.
- -pthread
-
Adds support for multithreading with the pthreads library.
This option sets flags for both the preprocessor and linker.
Darwin Options
These options are defined for all architectures running the Darwin operating
system. They are useful for compatibility with other Mac OS compilers.
- -all_load
-
Loads all members of static archive libraries.
See man ld(1) for more information.
- -arch_errors_fatal
-
Cause the errors having to do with files that have the wrong architecture
to be fatal.
- -bind_at_load
-
Causes the output file to be marked such that the dynamic linker will
bind all undefined references when the file is loaded or launched.
- -bundle
-
Produce a Mach-o bundle format file.
See man ld(1) for more information.
- -bundle_loader executable
-
This specifies the executable that will be loading the build
output file being linked. See man ld(1) for more information.
- -allowable_client client_name
-
- -arch_only
-
- -client_name
-
- -compatibility_version
-
- -current_version
-
- -dependency-file
-
- -dylib_file
-
- -dylinker_install_name
-
- -dynamic
-
- -dynamiclib
-
- -exported_symbols_list
-
- -filelist
-
- -flat_namespace
-
- -force_cpusubtype_ALL
-
- -force_flat_namespace
-
- -headerpad_max_install_names
-
- -image_base
-
- -init
-
- -install_name
-
- -keep_private_externs
-
- -multi_module
-
- -multiply_defined
-
- -multiply_defined_unused
-
- -noall_load
-
- -nofixprebinding
-
- -nomultidefs
-
- -noprebind
-
- -noseglinkedit
-
- -pagezero_size
-
- -prebind
-
- -prebind_all_twolevel_modules
-
- -private_bundle
-
- -read_only_relocs
-
- -sectalign
-
- -sectobjectsymbols
-
- -whyload
-
- -seg1addr
-
- -sectcreate
-
- -sectobjectsymbols
-
- -sectorder
-
- -seg_addr_table
-
- -seg_addr_table_filename
-
- -seglinkedit
-
- -segprot
-
- -segs_read_only_addr
-
- -segs_read_write_addr
-
- -single_module
-
- -static
-
- -sub_library
-
- -sub_umbrella
-
- -twolevel_namespace
-
- -umbrella
-
- -undefined
-
- -unexported_symbols_list
-
- -weak_reference_mismatches
-
- -whatsloaded
-
These options are available for Darwin linker. Darwin linker man page
describes them in detail.
MIPS Options
- -EB
-
Generate big-endian code.
- -EL
-
Generate little-endian code. This is the default for mips*el-*-*
configurations.
- -march=arch
-
Generate code that will run on arch, which can be the name of a
generic MIPS ISA, or the name of a particular processor.
The ISA names are:
mips1, mips2, mips3, mips4,
mips32, mips32r2, and mips64.
The processor names are:
4kc, 4kp, 5kc, 20kc,
m4k,
r2000, r3000, r3900, r4000, r4400,
r4600, r4650, r6000, r8000, rm7000,
rm9000,
orion,
sb1,
vr4100, vr4111, vr4120, vr4300,
vr5000, vr5400 and vr5500.
The special value from-abi selects the
most compatible architecture for the selected ABI (that is,
mips1 for 32-bit ABIs and mips3 for 64-bit ABIs).
In processor names, a final 000 can be abbreviated as k
(for example, -march=r2k). Prefixes are optional, and
vr may be written r.
GCC defines two macros based on the value of this option. The first
is _MIPS_ARCH, which gives the name of target architecture, as
a string. The second has the form _MIPS_ARCH_foo,
where foo is the capitalized value of _MIPS_ARCH.
For example, -march=r2000 will set _MIPS_ARCH
to ``r2000'' and define the macro _MIPS_ARCH_R2000.
Note that the _MIPS_ARCH macro uses the processor names given
above. In other words, it will have the full prefix and will not
abbreviate 000 as k. In the case of from-abi,
the macro names the resolved architecture (either ``mips1'' or
``mips3''). It names the default architecture when no
-march option is given.
- -mtune=arch
-
Optimize for arch. Among other things, this option controls
the way instructions are scheduled, and the perceived cost of arithmetic
operations. The list of arch values is the same as for
-march.
When this option is not used, GCC will optimize for the processor
specified by -march. By using -march and
-mtune together, it is possible to generate code that will
run on a family of processors, but optimize the code for one
particular member of that family.
-mtune defines the macros _MIPS_TUNE and
_MIPS_TUNE_foo, which work in the same way as the
-march ones described above.
- -mips1
-
Equivalent to -march=mips1.
- -mips2
-
Equivalent to -march=mips2.
- -mips3
-
Equivalent to -march=mips3.
- -mips4
-
Equivalent to -march=mips4.
- -mips32
-
Equivalent to -march=mips32.
- -mips32r2
-
Equivalent to -march=mips32r2.
- -mips64
-
Equivalent to -march=mips64.
- -mips16
-
- -mno-mips16
-
Use (do not use) the MIPS16 ISA.
- -mabi=32
-
- -mabi=o64
-
- -mabi=n32
-
- -mabi=64
-
- -mabi=eabi
-
Generate code for the given ABI.
Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
generates 64-bit code when you select a 64-bit architecture, but you
can use -mgp32 to get 32-bit code instead.
- -mabicalls
-
- -mno-abicalls
-
Generate (do not generate) SVR4-style position-independent code.
-mabicalls is the default for SVR4-based systems.
- -mxgot
-
- -mno-xgot
-
Lift (do not lift) the usual restrictions on the size of the global
offset table.
GCC normally uses a single instruction to load values from the GOT.
While this is relatively efficient, it will only work if the GOT
is smaller than about 64k. Anything larger will cause the linker
to report an error such as:
relocation truncated to fit: R_MIPS_GOT16 foobar
If this happens, you should recompile your code with -mxgot.
It should then work with very large GOTs, although it will also be
less efficient, since it will take three instructions to fetch the
value of a global symbol.
Note that some linkers can create multiple GOTs. If you have such a
linker, you should only need to use -mxgot when a single object
file accesses more than 64k's worth of GOT entries. Very few do.
These options have no effect unless GCC is generating position
independent code.
- -membedded-pic
-
- -mno-embedded-pic
-
Generate (do not generate) position-independent code suitable for some
embedded systems. All calls are made using PC relative addresses, and
all data is addressed using the $gp register. No more than 65536
bytes of global data may be used. This requires GNU as and GNU ld,
which do most of the work.
- -mgp32
-
Assume that general-purpose registers are 32 bits wide.
- -mgp64
-
Assume that general-purpose registers are 64 bits wide.
- -mfp32
-
Assume that floating-point registers are 32 bits wide.
- -mfp64
-
Assume that floating-point registers are 64 bits wide.
- -mhard-float
-
Use floating-point coprocessor instructions.
- -msoft-float
-
Do not use floating-point coprocessor instructions. Implement
floating-point calculations using library calls instead.
- -msingle-float
-
Assume that the floating-point coprocessor only supports single-precision
operations.
- -mdouble-float
-
Assume that the floating-point coprocessor supports double-precision
operations. This is the default.
- -mint64
-
Force "int" and "long" types to be 64 bits wide. See
-mlong32 for an explanation of the default and the way
that the pointer size is determined.
- -mlong64
-
Force "long" types to be 64 bits wide. See -mlong32 for
an explanation of the default and the way that the pointer size is
determined.
- -mlong32
-
Force "long", "int", and pointer types to be 32 bits wide.
The default size of "int"s, "long"s and pointers depends on
the ABI. All the supported ABIs use 32-bit "int"s. The n64 ABI
uses 64-bit "long"s, as does the 64-bit EABI; the others use
32-bit "long"s. Pointers are the same size as "long"s,
or the same size as integer registers, whichever is smaller.
- -G num
-
Put global and static items less than or equal to num bytes into
the small data or bss section instead of the normal data or bss section.
This allows the data to be accessed using a single instruction.
All modules should be compiled with the same -G num
value.
- -membedded-data
-
- -mno-embedded-data
-
Allocate variables to the read-only data section first if possible, then
next in the small data section if possible, otherwise in data. This gives
slightly slower code than the default, but reduces the amount of RAM required
when executing, and thus may be preferred for some embedded systems.
- -muninit-const-in-rodata
-
- -mno-uninit-const-in-rodata
-
Put uninitialized "const" variables in the read-only data section.
This option is only meaningful in conjunction with -membedded-data.
- -msplit-addresses
-
- -mno-split-addresses
-
Enable (disable) use of the "%hi()" and "%lo()" assembler
relocation operators. This option has been superceded by
-mexplicit-relocs but is retained for backwards compatibility.
- -mexplicit-relocs
-
- -mno-explicit-relocs
-
Use (do not use) assembler relocation operators when dealing with symbolic
addresses. The alternative, selected by -mno-explicit-relocs,
is to use assembler macros instead.
-mexplicit-relocs is usually the default if GCC was
configured to use an assembler that supports relocation operators.
However, there are two exceptions:
-
- *
-
GCC is not yet able to generate explicit relocations for the combination
of -mabi=64 and -mno-abicalls. This will be addressed
in a future release.
- *
-
The combination of -mabicalls and -fno-unit-at-a-time
implies -mno-explicit-relocs unless explicitly overridden.
This is because, when generating abicalls, the choice of relocation
depends on whether a symbol is local or global. In some rare cases,
GCC will not be able to decide this until the whole compilation unit
has been read.
-
- -mrnames
-
- -mno-rnames
-
Generate (do not generate) code that refers to registers using their
software names. The default is -mno-rnames, which tells GCC
to use hardware names like $4 instead of software names like
a0. The only assembler known to support -rnames is
the Algorithmics assembler.
- -mcheck-zero-division
-
- -mno-check-zero-division
-
Trap (do not trap) on integer division by zero. The default is
-mcheck-zero-division.
- -mmemcpy
-
- -mno-memcpy
-
Force (do not force) the use of "memcpy()" for non-trivial block
moves. The default is -mno-memcpy, which allows GCC to inline
most constant-sized copies.
- -mlong-calls
-
- -mno-long-calls
-
Disable (do not disable) use of the "jal" instruction. Calling
functions using "jal" is more efficient but requires the caller
and callee to be in the same 256 megabyte segment.
This option has no effect on abicalls code. The default is
-mno-long-calls.
- -mmad
-
- -mno-mad
-
Enable (disable) use of the "mad", "madu" and "mul"
instructions, as provided by the R4650 ISA.
- -mfused-madd
-
- -mno-fused-madd
-
Enable (disable) use of the floating point multiply-accumulate
instructions, when they are available. The default is
-mfused-madd.
When multiply-accumulate instructions are used, the intermediate
product is calculated to infinite precision and is not subject to
the FCSR Flush to Zero bit. This may be undesirable in some
circumstances.
- -nocpp
-
Tell the MIPS assembler to not run its preprocessor over user
assembler files (with a .s suffix) when assembling them.
- -mfix-sb1
-
- -mno-fix-sb1
-
Work around certain SB-1 CPU core errata.
(This flag currently works around the SB-1 revision 2
``F1'' and ``F2'' floating point errata.)
- -mflush-func=func
-
- -mno-flush-func
-
Specifies the function to call to flush the I and D caches, or to not
call any such function. If called, the function must take the same
arguments as the common "_flush_func()", that is, the address of the
memory range for which the cache is being flushed, the size of the
memory range, and the number 3 (to flush both caches). The default
depends on the target GCC was configured for, but commonly is either
_flush_func or __cpu_flush.
- -mbranch-likely
-
- -mno-branch-likely
-
Enable or disable use of Branch Likely instructions, regardless of the
default for the selected architecture. By default, Branch Likely
instructions may be generated if they are supported by the selected
architecture. An exception is for the MIPS32 and MIPS64 architectures
and processors which implement those architectures; for those, Branch
Likely instructions will not be generated by default because the MIPS32
and MIPS64 architectures specifically deprecate their use.
Intel 386 and AMD x86-64 Options
These -m options are defined for the i386 and x86-64 family of
computers:
- -mtune=cpu-type
-
Tune to cpu-type everything applicable about the generated code, except
for the ABI and the set of available instructions. The choices for
cpu-type are:
-
- i386
-
Original Intel's i386 CPU.
- i486
-
Intel's i486 CPU. (No scheduling is implemented for this chip.)
- i586, pentium
-
Intel Pentium CPU with no MMX support.
- pentium-mmx
-
Intel PentiumMMX CPU based on Pentium core with MMX instruction set support.
- i686, pentiumpro
-
Intel PentiumPro CPU.
- pentium2
-
Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
- pentium3, pentium3m
-
Intel Pentium3 CPU based on PentiumPro core with MMX and SSE instruction set
support.
- pentium-m
-
Low power version of Intel Pentium3 CPU with MMX, SSE and SSE2 instruction set
support. Used by Centrino notebooks.
- pentium4, pentium4m
-
Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support.
- prescott
-
Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 and SSE3 instruction
set support.
- nocona
-
Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
SSE2 and SSE3 instruction set support.
- k6
-
AMD K6 CPU with MMX instruction set support.
- k6-2, k6-3
-
Improved versions of AMD K6 CPU with MMX and 3dNOW! instruction set support.
- athlon, athlon-tbird
-
AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE prefetch instructions
support.
- athlon-4, athlon-xp, athlon-mp
-
Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
instruction set support.
- k8, opteron, athlon64, athlon-fx
-
AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
- winchip-c6
-
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.
- winchip2
-
IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
instruction set support.
- c3
-
Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
implemented for this chip.)
- c3-2
-
Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
implemented for this chip.)
-
While picking a specific cpu-type will schedule things appropriately
for that particular chip, the compiler will not generate any code that
does not run on the i386 without the -march=cpu-type option
being used.
- -march=cpu-type
-
Generate instructions for the machine type cpu-type. The choices
for cpu-type are the same as for -mtune. Moreover,
specifying -march=cpu-type implies -mtune=cpu-type.
- -mcpu=cpu-type
-
A deprecated synonym for -mtune.
- -m386
-
- -m486
-
- -mpentium
-
- -mpentiumpro
-
These options are synonyms for -mtune=i386, -mtune=i486,
-mtune=pentium, and -mtune=pentiumpro respectively.
These synonyms are deprecated.
- -mfpmath=unit
-
Generate floating point arithmetics for selected unit unit. The choices
for unit are:
-
- 387
-
Use the standard 387 floating point coprocessor present majority of chips and
emulated otherwise. Code compiled with this option will run almost everywhere.
The temporary results are computed in 80bit precision instead of precision
specified by the type resulting in slightly different results compared to most
of other chips. See -ffloat-store for more detailed description.
This is the default choice for i386 compiler.
- sse
-
Use scalar floating point instructions present in the SSE instruction set.
This instruction set is supported by Pentium3 and newer chips, in the AMD line
by Athlon-4, Athlon-xp and Athlon-mp chips. The earlier version of SSE
instruction set supports only single precision arithmetics, thus the double and
extended precision arithmetics is still done using 387. Later version, present
only in Pentium4 and the future AMD x86-64 chips supports double precision
arithmetics too.
For i387 you need to use -march=cpu-type, -msse or
-msse2 switches to enable SSE extensions and make this option
effective. For x86-64 compiler, these extensions are enabled by default.
The resulting code should be considerably faster in the majority of cases and avoid
the numerical instability problems of 387 code, but may break some existing
code that expects temporaries to be 80bit.
This is the default choice for the x86-64 compiler.
- sse,387
-
Attempt to utilize both instruction sets at once. This effectively double the
amount of available registers and on chips with separate execution units for
387 and SSE the execution resources too. Use this option with care, as it is
still experimental, because the GCC register allocator does not model separate
functional units well resulting in instable performance.
-
- -masm=dialect
-
Output asm instructions using selected dialect. Supported choices are
intel or att (the default one).
- -mieee-fp
-
- -mno-ieee-fp
-
Control whether or not the compiler uses IEEE floating point
comparisons. These handle correctly the case where the result of a
comparison is unordered.
- -msoft-float
-
Generate output containing library calls for floating point.
Warning: the requisite libraries are not part of GCC.
Normally the facilities of the machine's usual C compiler are used, but
this can't be done directly in cross-compilation. You must make your
own arrangements to provide suitable library functions for
cross-compilation.
On machines where a function returns floating point results in the 80387
register stack, some floating point opcodes may be emitted even if
-msoft-float is used.
- -mno-fp-ret-in-387
-
Do not use the FPU registers for return values of functions.
The usual calling convention has functions return values of types
"float" and "double" in an FPU register, even if there
is no FPU. The idea is that the operating system should emulate
an FPU.
The option -mno-fp-ret-in-387 causes such values to be returned
in ordinary CPU registers instead.
- -mno-fancy-math-387
-
Some 387 emulators do not support the "sin", "cos" and
"sqrt" instructions for the 387. Specify this option to avoid
generating those instructions. This option is the default on FreeBSD,
OpenBSD and NetBSD. This option is overridden when -march
indicates that the target cpu will always have an FPU and so the
instruction will not need emulation. As of revision 2.6.1, these
instructions are not generated unless you also use the
-funsafe-math-optimizations switch.
- -malign-double
-
- -mno-align-double
-
Control whether GCC aligns "double", "long double", and
"long long" variables on a two word boundary or a one word
boundary. Aligning "double" variables on a two word boundary will
produce code that runs somewhat faster on a Pentium at the
expense of more memory.
Warning: if you use the -malign-double switch,
structures containing the above types will be aligned differently than
the published application binary interface specifications for the 386
and will not be binary compatible with structures in code compiled
without that switch.
- -m96bit-long-double
-
- -m128bit-long-double
-
These switches control the size of "long double" type. The i386
application binary interface specifies the size to be 96 bits,
so -m96bit-long-double is the default in 32 bit mode.
Modern architectures (Pentium and newer) would prefer "long double"
to be aligned to an 8 or 16 byte boundary. In arrays or structures
conforming to the ABI, this would not be possible. So specifying a
-m128bit-long-double will align "long double"
to a 16 byte boundary by padding the "long double" with an additional
32 bit zero.
In the x86-64 compiler, -m128bit-long-double is the default choice as
its ABI specifies that "long double" is to be aligned on 16 byte boundary.
Notice that neither of these options enable any extra precision over the x87
standard of 80 bits for a "long double".
Warning: if you override the default value for your target ABI, the
structures and arrays containing "long double" variables will change
their size as well as function calling convention for function taking
"long double" will be modified. Hence they will not be binary
compatible with arrays or structures in code compiled without that switch.
- -msvr3-shlib
-
- -mno-svr3-shlib
-
Control whether GCC places uninitialized local variables into the
"bss" or "data" segments. -msvr3-shlib places them
into "bss". These options are meaningful only on System V Release 3.
- -mrtd
-
Use a different function-calling convention, in which functions that
take a fixed number of arguments return with the "ret" num
instruction, which pops their arguments while returning. This saves one
instruction in the caller since there is no need to pop the arguments
there.
You can specify that an individual function is called with this calling
sequence with the function attribute stdcall. You can also
override the -mrtd option by using the function attribute
cdecl.
Warning: this calling convention is incompatible with the one
normally used on Unix, so you cannot use it if you need to call
libraries compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including "printf");
otherwise incorrect code will be generated for calls to those
functions.
In addition, seriously incorrect code will result if you call a
function with too many arguments. (Normally, extra arguments are
harmlessly ignored.)
- -mregparm=num
-
Control how many registers are used to pass integer arguments. By
default, no registers are used to pass arguments, and at most 3
registers can be used. You can control this behavior for a specific
function by using the function attribute regparm.
Warning: if you use this switch, and
num is nonzero, then you must build all modules with the same
value, including any libraries. This includes the system libraries and
startup modules.
- -mpreferred-stack-boundary=num
-
Attempt to keep the stack boundary aligned to a 2 raised to num
byte boundary. If -mpreferred-stack-boundary is not specified,
the default is 4 (16 bytes or 128 bits), except when optimizing for code
size (-Os), in which case the default is the minimum correct
alignment (4 bytes for x86, and 8 bytes for x86-64).
On Pentium and PentiumPro, "double" and "long double" values
should be aligned to an 8 byte boundary (see -malign-double) or
suffer significant run time performance penalties. On Pentium III, the
Streaming SIMD Extension (SSE) data type "__m128" suffers similar
penalties if it is not 16 byte aligned.
To ensure proper alignment of this values on the stack, the stack boundary
must be as aligned as that required by any value stored on the stack.
Further, every function must be generated such that it keeps the stack
aligned. Thus calling a function compiled with a higher preferred
stack boundary from a function compiled with a lower preferred stack
boundary will most likely misalign the stack. It is recommended that
libraries that use callbacks always use the default setting.
This extra alignment does consume extra stack space, and generally
increases code size. Code that is sensitive to stack space usage, such
as embedded systems and operating system kernels, may want to reduce the
preferred alignment to -mpreferred-stack-boundary=2.
- -mmmx
-
- -mno-mmx
-
- -msse
-
- -mno-sse
-
- -msse2
-
- -mno-sse2
-
- -msse3
-
- -mno-sse3
-
- -m3dnow
-
- -mno-3dnow
-
These switches enable or disable the use of built-in functions that allow
direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
instruction set.
To have SSE/SSE2 instructions generated automatically from floating-point
code, see -mfpmath=sse.
- -mpush-args
-
- -mno-push-args
-
Use PUSH operations to store outgoing parameters. This method is shorter
and usually equally fast as method using SUB/MOV operations and is enabled
by default. In some cases disabling it may improve performance because of
improved scheduling and reduced dependencies.
- -maccumulate-outgoing-args
-
If enabled, the maximum amount of space required for outgoing arguments will be
computed in the function prologue. This is faster on most modern CPUs
because of reduced dependencies, improved scheduling and reduced stack usage
when preferred stack boundary is not equal to 2. The drawback is a notable
increase in code size. This switch implies -mno-push-args.
- -mthreads
-
Support thread-safe exception handling on Mingw32. Code that relies
on thread-safe exception handling must compile and link all code with the
-mthreads option. When compiling, -mthreads defines
-D_MT; when linking, it links in a special thread helper library
-lmingwthrd which cleans up per thread exception handling data.
- -mno-align-stringops
-
Do not align destination of inlined string operations. This switch reduces
code size and improves performance in case the destination is already aligned,
but GCC doesn't know about it.
- -minline-all-stringops
-
By default GCC inlines string operations only when destination is known to be
aligned at least to 4 byte boundary. This enables more inlining, increase code
size, but may improve performance of code that depends on fast memcpy, strlen
and memset for short lengths.
- -momit-leaf-frame-pointer
-
Don't keep the frame pointer in a register for leaf functions. This
avoids the instructions to save, set up and restore frame pointers and
makes an extra register available in leaf functions. The option
-fomit-frame-pointer removes the frame pointer for all functions
which might make debugging harder.
- -mtls-direct-seg-refs
-
- -mno-tls-direct-seg-refs
-
Controls whether TLS variables may be accessed with offsets from the
TLS segment register (%gs for 32-bit, %fs for 64-bit),
or whether the thread base pointer must be added. Whether or not this
is legal depends on the operating system, and whether it maps the
segment to cover the entire TLS area.
For systems that use GNU libc, the default is on.
These -m switches are supported in addition to the above
on AMD x86-64 processors in 64-bit environments.
- -m32
-
- -m64
-
Generate code for a 32-bit or 64-bit environment.
The 32-bit environment sets int, long and pointer to 32 bits and
generates code that runs on any i386 system.
The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits and generates code for AMD's x86-64 architecture.
- -mno-red-zone
-
Do not use a so called red zone for x86-64 code. The red zone is mandated
by the x86-64 ABI, it is a 128-byte area beyond the location of the
stack pointer that will not be modified by signal or interrupt handlers
and therefore can be used for temporary data without adjusting the stack
pointer. The flag -mno-red-zone disables this red zone.
- -mcmodel=small
-
Generate code for the small code model: the program and its symbols must
be linked in the lower 2 GB of the address space. Pointers are 64 bits.
Programs can be statically or dynamically linked. This is the default
code model.
- -mcmodel=kernel
-
Generate code for the kernel code model. The kernel runs in the
negative 2 GB of the address space.
This model has to be used for Linux kernel code.
- -mcmodel=medium
-
Generate code for the medium model: The program is linked in the lower 2
GB of the address space but symbols can be located anywhere in the
address space. Programs can be statically or dynamically linked, but
building of shared libraries are not supported with the medium model.
- -mcmodel=large
-
Generate code for the large model: This model makes no assumptions
about addresses and sizes of sections. Currently GCC does not implement
this model.
HPPA Options
These -m options are defined for the HPPA family of computers:
- -march=architecture-type
-
Generate code for the specified architecture. The choices for
architecture-type are 1.0 for PA 1.0, 1.1 for PA
1.1, and 2.0 for PA 2.0 processors. Refer to
/usr/lib/sched.models on an HP-UX system to determine the proper
architecture option for your machine. Code compiled for lower numbered
architectures will run on higher numbered architectures, but not the
other way around.
PA 2.0 support currently requires gas snapshot 19990413 or later. The
next release of binutils (current is 2.9.1) will probably contain PA 2.0
support.
- -mpa-risc-1-0
-
- -mpa-risc-1-1
-
- -mpa-risc-2-0
-
Synonyms for -march=1.0, -march=1.1, and -march=2.0 respectively.
- -mbig-switch
-
Generate code suitable for big switch tables. Use this option only if
the assembler/linker complain about out of range branches within a switch
table.
- -mjump-in-delay
-
Fill delay slots of function calls with unconditional jump instructions
by modifying the return pointer for the function call to be the target
of the conditional jump.
- -mdisable-fpregs
-
Prevent floating point registers from being used in any manner. This is
necessary for compiling kernels which perform lazy context switching of
floating point registers. If you use this option and attempt to perform
floating point operations, the compiler will abort.
- -mdisable-indexing
-
Prevent the compiler from using indexing address modes. This avoids some
rather obscure problems when compiling MIG generated code under MACH.
- -mno-space-regs
-
Generate code that assumes the target has no space registers. This allows
GCC to generate faster indirect calls and use unscaled index address modes.
Such code is suitable for level 0 PA systems and kernels.
- -mfast-indirect-calls
-
Generate code that assumes calls never cross space boundaries. This
allows GCC to emit code which performs faster indirect calls.
This option will not work in the presence of shared libraries or nested
functions.
- -mlong-load-store
-
Generate 3-instruction load and store sequences as sometimes required by
the HP-UX 10 linker. This is equivalent to the +k option to
the HP compilers.
- -mportable-runtime
-
Use the portable calling conventions proposed by HP for ELF systems.
- -mgas
-
Enable the use of assembler directives only GAS understands.
- -mschedule=cpu-type
-
Schedule code according to the constraints for the machine type
cpu-type. The choices for cpu-type are 700
7100, 7100LC, 7200, 7300 and 8000. Refer
to /usr/lib/sched.models on an HP-UX system to determine the
proper scheduling option for your machine. The default scheduling is
8000.
- -mlinker-opt
-
Enable the optimization pass in the HP-UX linker. Note this makes symbolic
debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
linkers in which they give bogus error messages when linking some programs.
- -msoft-float
-
Generate output containing library calls for floating point.
Warning: the requisite libraries are not available for all HPPA
targets. Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation. You must make
your own arrangements to provide suitable library functions for
cross-compilation. The embedded target hppa1.1-*-pro
does provide software floating point support.
-msoft-float changes the calling convention in the output file;
therefore, it is only useful if you compile all of a program with
this option. In particular, you need to compile libgcc.a, the
library that comes with GCC, with -msoft-float in order for
this to work.
- -msio
-
Generate the predefine, "_SIO", for server IO. The default is
-mwsio. This generates the predefines, "__hp9000s700",
"__hp9000s700__" and "_WSIO", for workstation IO. These
options are available under HP-UX and HI-UX.
- -mgnu-ld
-
Use GNU ld specific options. This passes -shared to ld when
building a shared library. It is the default when GCC is configured,
explicitly or implicitly, with the GNU linker. This option does not
have any affect on which ld is called, it only changes what parameters
are passed to that ld. The ld that is called is determined by the
--with-ld configure option, GCC's program search path, and
finally by the user's PATH. The linker used by GCC can be printed
using which `gcc -print-prog-name=ld`. This option is only available
on the 64 bit HP-UX GCC, i.e. configured with hppa*64*-*-hpux*.
- -mhp-ld
-
Use HP ld specific options. This passes -b to ld when building
a shared library and passes +Accept TypeMismatch to ld on all
links. It is the default when GCC is configured, explicitly or
implicitly, with the HP linker. This option does not have any affect on
which ld is called, it only changes what parameters are passed to that
ld. The ld that is called is determined by the --with-ld
configure option, GCC's program search path, and finally by the user's
PATH. The linker used by GCC can be printed using which
`gcc -print-prog-name=ld`. This option is only available on the 64 bit
HP-UX GCC, i.e. configured with hppa*64*-*-hpux*.
- -mlong-calls
-
Generate code that uses long call sequences. This ensures that a call
is always able to reach linker generated stubs. The default is to generate
long calls only when the distance from the call site to the beginning
of the function or translation unit, as the case may be, exceeds a
predefined limit set by the branch type being used. The limits for
normal calls are 7,600,000 and 240,000 bytes, respectively for the
PA 2.0 and PA 1.X architectures. Sibcalls are always limited at
240,000 bytes.
Distances are measured from the beginning of functions when using the
-ffunction-sections option, or when using the -mgas
and -mno-portable-runtime options together under HP-UX with
the SOM linker.
It is normally not desirable to use this option as it will degrade
performance. However, it may be useful in large applications,
particularly when partial linking is used to build the application.
The types of long calls used depends on the capabilities of the
assembler and linker, and the type of code being generated. The
impact on systems that support long absolute calls, and long pic
symbol-difference or pc-relative calls should be relatively small.
However, an indirect call is used on 32-bit ELF systems in pic code
and it is quite long.
- -nolibdld
-
Suppress the generation of link options to search libdld.sl when the
-static option is specified on HP-UX 10 and later.
- -static
-
The HP-UX implementation of setlocale in libc has a dependency on
libdld.sl. There isn't an archive version of libdld.sl. Thus,
when the -static option is specified, special link options
are needed to resolve this dependency.
On HP-UX 10 and later, the GCC driver adds the necessary options to
link with libdld.sl when the -static option is specified.
This causes the resulting binary to be dynamic. On the 64-bit port,
the linkers generate dynamic binaries by default in any case. The
-nolibdld option can be used to prevent the GCC driver from
adding these link options.
- -threads
-
Add support for multithreading with the dce thread library
under HP-UX. This option sets flags for both the preprocessor and
linker.
Intel 960 Options
These -m options are defined for the Intel 960 implementations:
- -mcpu-type
-
Assume the defaults for the machine type cpu-type for some of
the other options, including instruction scheduling, floating point
support, and addressing modes. The choices for cpu-type are
ka, kb, mc, ca, cf,
sa, and sb.
The default is
kb.
- -mnumerics
-
- -msoft-float
-
The -mnumerics option indicates that the processor does support
floating-point instructions. The -msoft-float option indicates
that floating-point support should not be assumed.
- -mleaf-procedures
-
- -mno-leaf-procedures
-
Do (or do not) attempt to alter leaf procedures to be callable with the
"bal" instruction as well as "call". This will result in more
efficient code for explicit calls when the "bal" instruction can be
substituted by the assembler or linker, but less efficient code in other
cases, such as calls via function pointers, or using a linker that doesn't
support this optimization.
- -mtail-call
-
- -mno-tail-call
-
Do (or do not) make additional attempts (beyond those of the
machine-independent portions of the compiler) to optimize tail-recursive
calls into branches. You may not want to do this because the detection of
cases where this is not valid is not totally complete. The default is
-mno-tail-call.
- -mcomplex-addr
-
- -mno-complex-addr
-
Assume (or do not assume) that the use of a complex addressing mode is a
win on this implementation of the i960. Complex addressing modes may not
be worthwhile on the K-series, but they definitely are on the C-series.
The default is currently -mcomplex-addr for all processors except
the CB and CC.
- -mcode-align
-
- -mno-code-align
-
Align code to 8-byte boundaries for faster fetching (or don't bother).
Currently turned on by default for C-series implementations only.
- -mic-compat
-
- -mic2.0-compat
-
- -mic3.0-compat
-
Enable compatibility with iC960 v2.0 or v3.0.
- -masm-compat
-
- -mintel-asm
-
Enable compatibility with the iC960 assembler.
- -mstrict-align
-
- -mno-strict-align
-
Do not permit (do permit) unaligned accesses.
- -mold-align
-
Enable structure-alignment compatibility with Intel's gcc release version
1.3 (based on gcc 1.37). This option implies -mstrict-align.
- -mlong-double-64
-
Implement type long double as 64-bit floating point numbers.
Without the option long double is implemented by 80-bit
floating point numbers. The only reason we have it because there is
no 128-bit long double support in fp-bit.c yet. So it
is only useful for people using soft-float targets. Otherwise, we
should recommend against use of it.
DEC Alpha Options
These -m options are defined for the DEC Alpha implementations:
- -mno-soft-float
-
- -msoft-float
-
Use (do not use) the hardware floating-point instructions for
floating-point operations. When -msoft-float is specified,
functions in libgcc.a will be used to perform floating-point
operations. Unless they are replaced by routines that emulate the
floating-point operations, or compiled in such a way as to call such
emulations routines, these routines will issue floating-point
operations. If you are compiling for an Alpha without floating-point
operations, you must ensure that the library is built so as not to call
them.
Note that Alpha implementations without floating-point operations are
required to have floating-point registers.
- -mfp-reg
-
- -mno-fp-regs
-
Generate code that uses (does not use) the floating-point register set.
-mno-fp-regs implies -msoft-float. If the floating-point
register set is not used, floating point operands are passed in integer
registers as if they were integers and floating-point results are passed
in $0 instead of $f0. This is a non-standard calling sequence,
so any function with a floating-point argument or return value called by code
compiled with -mno-fp-regs must also be compiled with that
option.
A typical use of this option is building a kernel that does not use,
and hence need not save and restore, any floating-point registers.
- -mieee
-
The Alpha architecture implements floating-point hardware optimized for
maximum performance. It is mostly compliant with the IEEE floating
point standard. However, for full compliance, software assistance is
required. This option generates code fully IEEE compliant code
except that the inexact-flag is not maintained (see below).
If this option is turned on, the preprocessor macro "_IEEE_FP" is
defined during compilation. The resulting code is less efficient but is
able to correctly support denormalized numbers and exceptional IEEE
values such as not-a-number and plus/minus infinity. Other Alpha
compilers call this option -ieee_with_no_inexact.
- -mieee-with-inexact
-
This is like -mieee except the generated code also maintains
the IEEE inexact-flag. Turning on this option causes the
generated code to implement fully-compliant IEEE math. In addition to
"_IEEE_FP", "_IEEE_FP_EXACT" is defined as a preprocessor
macro. On some Alpha implementations the resulting code may execute
significantly slower than the code generated by default. Since there is
very little code that depends on the inexact-flag, you should
normally not specify this option. Other Alpha compilers call this
option -ieee_with_inexact.
- -mfp-trap-mode=trap-mode
-
This option controls what floating-point related traps are enabled.
Other Alpha compilers call this option -fptm trap-mode.
The trap mode can be set to one of four values:
-
- n
-
This is the default (normal) setting. The only traps that are enabled
are the ones that cannot be disabled in software (e.g., division by zero
trap).
- u
-
In addition to the traps enabled by n, underflow traps are enabled
as well.
- su
-
Like su, but the instructions are marked to be safe for software
completion (see Alpha architecture manual for details).
- sui
-
Like su, but inexact traps are enabled as well.
-
- -mfp-rounding-mode=rounding-mode
-
Selects the IEEE rounding mode. Other Alpha compilers call this option
-fprm rounding-mode. The rounding-mode can be one
of:
-
- n
-
Normal IEEE rounding mode. Floating point numbers are rounded towards
the nearest machine number or towards the even machine number in case
of a tie.
- m
-
Round towards minus infinity.
- c
-
Chopped rounding mode. Floating point numbers are rounded towards zero.
- d
-
Dynamic rounding mode. A field in the floating point control register
(fpcr, see Alpha architecture reference manual) controls the
rounding mode in effect. The C library initializes this register for
rounding towards plus infinity. Thus, unless your program modifies the
fpcr, d corresponds to round towards plus infinity.
-
- -mtrap-precision=trap-precision
-
In the Alpha architecture, floating point traps are imprecise. This
means without software assistance it is impossible to recover from a
floating trap and program execution normally needs to be terminated.
GCC can generate code that can assist operating system trap handlers
in determining the exact location that caused a floating point trap.
Depending on the requirements of an application, different levels of
precisions can be selected:
-
- p
-
Program precision. This option is the default and means a trap handler
can only identify which program caused a floating point exception.
- f
-
Function precision. The trap handler can determine the function that
caused a floating point exception.
- i
-
Instruction precision. The trap handler can determine the exact
instruction that caused a floating point exception.
-
Other Alpha compilers provide the equivalent options called
-scope_safe and -resumption_safe.
- -mieee-conformant
-
This option marks the generated code as IEEE conformant. You must not
use this option unless you also specify -mtrap-precision=i and either
-mfp-trap-mode=su or -mfp-trap-mode=sui. Its only effect
is to emit the line .eflag 48 in the function prologue of the
generated assembly file. Under DEC Unix, this has the effect that
IEEE-conformant math library routines will be linked in.
- -mbuild-constants
-
Normally GCC examines a 32- or 64-bit integer constant to
see if it can construct it from smaller constants in two or three
instructions. If it cannot, it will output the constant as a literal and
generate code to load it from the data segment at runtime.
Use this option to require GCC to construct all integer constants
using code, even if it takes more instructions (the maximum is six).
You would typically use this option to build a shared library dynamic
loader. Itself a shared library, it must relocate itself in memory
before it can find the variables and constants in its own data segment.
- -malpha-as
-
- -mgas
-
Select whether to generate code to be assembled by the vendor-supplied
assembler (-malpha-as) or by the GNU assembler -mgas.
- -mbwx
-
- -mno-bwx
-
- -mcix
-
- -mno-cix
-
- -mfix
-
- -mno-fix
-
- -mmax
-
- -mno-max
-
Indicate whether GCC should generate code to use the optional BWX,
CIX, FIX and MAX instruction sets. The default is to use the instruction
sets supported by the CPU type specified via -mcpu= option or that
of the CPU on which GCC was built if none was specified.
- -mfloat-vax
-
- -mfloat-ieee
-
Generate code that uses (does not use) VAX F and G floating point
arithmetic instead of IEEE single and double precision.
- -mexplicit-relocs
-
- -mno-explicit-relocs
-
Older Alpha assemblers provided no way to generate symbol relocations
except via assembler macros. Use of these macros does not allow
optimal instruction scheduling. GNU binutils as of version 2.12
supports a new syntax that allows the compiler to explicitly mark
which relocations should apply to which instructions. This option
is mostly useful for debugging, as GCC detects the capabilities of
the assembler when it is built and sets the default accordingly.
- -msmall-data
-
- -mlarge-data
-
When -mexplicit-relocs is in effect, static data is
accessed via gp-relative relocations. When -msmall-data
is used, objects 8 bytes long or smaller are placed in a small data area
(the ".sdata" and ".sbss" sections) and are accessed via
16-bit relocations off of the $gp register. This limits the
size of the small data area to 64KB, but allows the variables to be
directly accessed via a single instruction.
The default is -mlarge-data. With this option the data area
is limited to just below 2GB. Programs that require more than 2GB of
data must use "malloc" or "mmap" to allocate the data in the
heap instead of in the program's data segment.
When generating code for shared libraries, -fpic implies
-msmall-data and -fPIC implies -mlarge-data.
- -msmall-text
-
- -mlarge-text
-
When -msmall-text is used, the compiler assumes that the
code of the entire program (or shared library) fits in 4MB, and is
thus reachable with a branch instruction. When -msmall-data
is used, the compiler can assume that all local symbols share the
same $gp value, and thus reduce the number of instructions
required for a function call from 4 to 1.
The default is -mlarge-text.
- -mcpu=cpu_type
-
Set the instruction set and instruction scheduling parameters for
machine type cpu_type. You can specify either the EV
style name or the corresponding chip number. GCC supports scheduling
parameters for the EV4, EV5 and EV6 family of processors and will
choose the default values for the instruction set from the processor
you specify. If you do not specify a processor type, GCC will default
to the processor on which the compiler was built.
Supported values for cpu_type are
-
- ev4
-
- ev45
-
- 21064
-
Schedules as an EV4 and has no instruction set extensions.
- ev5
-
- 21164
-
Schedules as an EV5 and has no instruction set extensions.
- ev56
-
- 21164a
-
Schedules as an EV5 and supports the BWX extension.
- pca56
-
- 21164pc
-
- 21164PC
-
Schedules as an EV5 and supports the BWX and MAX extensions.
- ev6
-
- 21264
-
Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
- ev67
-
- 21264a
-
Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
-
- -mtune=cpu_type
-
Set only the instruction scheduling parameters for machine type
cpu_type. The instruction set is not changed.
- -mmemory-latency=time
-
Sets the latency the scheduler should assume for typical memory
references as seen by the application. This number is highly
dependent on the memory access patterns used by the application
and the size of the external cache on the machine.
Valid options for time are
-
- number
-
A decimal number representing clock cycles.
- L1
-
- L2
-
- L3
-
- main
-
The compiler contains estimates of the number of clock cycles for
``typical'' EV4 & EV5 hardware for the Level 1, 2 & 3 caches
(also called Dcache, Scache, and Bcache), as well as to main memory.
Note that L3 is only valid for EV5.
-
DEC Alpha/VMS Options
These -m options are defined for the DEC Alpha/VMS implementations:
- -mvms-return-codes
-
Return VMS condition codes from main. The default is to return POSIX
style condition (e.g. error) codes.
H8/300 Options
These -m options are defined for the H8/300 implementations:
- -mrelax
-
Shorten some address references at link time, when possible; uses the
linker option -relax.
- -mh
-
Generate code for the H8/300H.
- -ms
-
Generate code for the H8S.
- -mn
-
Generate code for the H8S and H8/300H in the normal mode. This switch
must be used either with -mh or -ms.
- -ms2600
-
Generate code for the H8S/2600. This switch must be used with -ms.
- -mint32
-
Make "int" data 32 bits by default.
- -malign-300
-
On the H8/300H and H8S, use the same alignment rules as for the H8/300.
The default for the H8/300H and H8S is to align longs and floats on 4
byte boundaries.
-malign-300 causes them to be aligned on 2 byte boundaries.
This option has no effect on the H8/300.
SH Options
These -m options are defined for the SH implementations:
- -m1
-
Generate code for the SH1.
- -m2
-
Generate code for the SH2.
- -m2e
-
Generate code for the SH2e.
- -m3
-
Generate code for the SH3.
- -m3e
-
Generate code for the SH3e.
- -m4-nofpu
-
Generate code for the SH4 without a floating-point unit.
- -m4-single-only
-
Generate code for the SH4 with a floating-point unit that only
supports single-precision arithmetic.
- -m4-single
-
Generate code for the SH4 assuming the floating-point unit is in
single-precision mode by default.
- -m4
-
Generate code for the SH4.
- -mb
-
Compile code for the processor in big endian mode.
- -ml
-
Compile code for the processor in little endian mode.
- -mdalign
-
Align doubles at 64-bit boundaries. Note that this changes the calling
conventions, and thus some functions from the standard C library will
not work unless you recompile it first with -mdalign.
- -mrelax
-
Shorten some address references at link time, when possible; uses the
linker option -relax.
- -mbigtable
-
Use 32-bit offsets in "switch" tables. The default is to use
16-bit offsets.
- -mfmovd
-
Enable the use of the instruction "fmovd".
- -mhitachi
-
Comply with the calling conventions defined by Renesas.
- -mnomacsave
-
Mark the "MAC" register as call-clobbered, even if
-mhitachi is given.
- -mieee
-
Increase IEEE-compliance of floating-point code.
- -misize
-
Dump instruction size and location in the assembly code.
- -mpadstruct
-
This option is deprecated. It pads structures to multiple of 4 bytes,
which is incompatible with the SH ABI.
- -mspace
-
Optimize for space instead of speed. Implied by -Os.
- -mprefergot
-
When generating position-independent code, emit function calls using
the Global Offset Table instead of the Procedure Linkage Table.
- -musermode
-
Generate a library function call to invalidate instruction cache
entries, after fixing up a trampoline. This library function call
doesn't assume it can write to the whole memory address space. This
is the default when the target is "sh-*-linux*".
Options for System V
These additional options are available on System V Release 4 for
compatibility with other compilers on those systems:
- -G
-
Create a shared object.
It is recommended that -symbolic or -shared be used instead.
- -Qy
-
Identify the versions of each tool used by the compiler, in a
".ident" assembler directive in the output.
- -Qn
-
Refrain from adding ".ident" directives to the output file (this is
the default).
- -YP,dirs
-
Search the directories dirs, and no others, for libraries
specified with -l.
- -Ym,dir
-
Look in the directory dir to find the M4 preprocessor.
The assembler uses this option.
TMS320C3x/C4x Options
These -m options are defined for TMS320C3x/C4x implementations:
- -mcpu=cpu_type
-
Set the instruction set, register set, and instruction scheduling
parameters for machine type cpu_type. Supported values for
cpu_type are c30, c31, c32, c40, and
c44. The default is c40 to generate code for the
TMS320C40.
- -mbig-memory
-
- -mbig
-
- -msmall-memory
-
- -msmall
-
Generates code for the big or small memory model. The small memory
model assumed that all data fits into one 64K word page. At run-time
the data page (DP) register must be set to point to the 64K page
containing the .bss and .data program sections. The big memory model is
the default and requires reloading of the DP register for every direct
memory access.
- -mbk
-
- -mno-bk
-
Allow (disallow) allocation of general integer operands into the block
count register BK.
- -mdb
-
- -mno-db
-
Enable (disable) generation of code using decrement and branch,
DBcond(D), instructions. This is enabled by default for the C4x. To be
on the safe side, this is disabled for the C3x, since the maximum
iteration count on the C3x is 2^{23 + 1} (but who iterates loops more than
2^{23} times on the C3x?). Note that GCC will try to reverse a loop so
that it can utilize the decrement and branch instruction, but will give
up if there is more than one memory reference in the loop. Thus a loop
where the loop counter is decremented can generate slightly more
efficient code, in cases where the RPTB instruction cannot be utilized.
- -mdp-isr-reload
-
- -mparanoid
-
Force the DP register to be saved on entry to an interrupt service
routine (ISR), reloaded to point to the data section, and restored on
exit from the ISR. This should not be required unless someone has
violated the small memory model by modifying the DP register, say within
an object library.
- -mmpyi
-
- -mno-mpyi
-
For the C3x use the 24-bit MPYI instruction for integer multiplies
instead of a library call to guarantee 32-bit results. Note that if one
of the operands is a constant, then the multiplication will be performed
using shifts and adds. If the -mmpyi option is not specified for the C3x,
then squaring operations are performed inline instead of a library call.
- -mfast-fix
-
- -mno-fast-fix
-
The C3x/C4x FIX instruction to convert a floating point value to an
integer value chooses the nearest integer less than or equal to the
floating point value rather than to the nearest integer. Thus if the
floating point number is negative, the result will be incorrectly
truncated an additional code is necessary to detect and correct this
case. This option can be used to disable generation of the additional
code required to correct the result.
- -mrptb
-
- -mno-rptb
-
Enable (disable) generation of repeat block sequences using the RPTB
instruction for zero overhead looping. The RPTB construct is only used
for innermost loops that do not call functions or jump across the loop
boundaries. There is no advantage having nested RPTB loops due to the
overhead required to save and restore the RC, RS, and RE registers.
This is enabled by default with -O2.
- -mrpts=count
-
- -mno-rpts
-
Enable (disable) the use of the single instruction repeat instruction
RPTS. If a repeat block contains a single instruction, and the loop
count can be guaranteed to be less than the value count, GCC will
emit a RPTS instruction instead of a RPTB. If no value is specified,
then a RPTS will be emitted even if the loop count cannot be determined
at compile time. Note that the repeated instruction following RPTS does
not have to be reloaded from memory each iteration, thus freeing up the
CPU buses for operands. However, since interrupts are blocked by this
instruction, it is disabled by default.
- -mloop-unsigned
-
- -mno-loop-unsigned
-
The maximum iteration count when using RPTS and RPTB (and DB on the C40)
is 2^{31 + 1} since these instructions test if the iteration count is
negative to terminate the loop. If the iteration count is unsigned
there is a possibility than the 2^{31 + 1} maximum iteration count may be
exceeded. This switch allows an unsigned iteration count.
- -mti
-
Try to emit an assembler syntax that the TI assembler (asm30) is happy
with. This also enforces compatibility with the API employed by the TI
C3x C compiler. For example, long doubles are passed as structures
rather than in floating point registers.
- -mregparm
-
- -mmemparm
-
Generate code that uses registers (stack) for passing arguments to functions.
By default, arguments are passed in registers where possible rather
than by pushing arguments on to the stack.
- -mparallel-insns
-
- -mno-parallel-insns
-
Allow the generation of parallel instructions. This is enabled by
default with -O2.
- -mparallel-mpy
-
- -mno-parallel-mpy
-
Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
provided -mparallel-insns is also specified. These instructions have
tight register constraints which can pessimize the code generation
of large functions.
V850 Options
These -m options are defined for V850 implementations:
- -mlong-calls
-
- -mno-long-calls
-
Treat all calls as being far away (near). If calls are assumed to be
far away, the compiler will always load the functions address up into a
register, and call indirect through the pointer.
- -mno-ep
-
- -mep
-
Do not optimize (do optimize) basic blocks that use the same index
pointer 4 or more times to copy pointer into the "ep" register, and
use the shorter "sld" and "sst" instructions. The -mep
option is on by default if you optimize.
- -mno-prolog-function
-
- -mprolog-function
-
Do not use (do use) external functions to save and restore registers
at the prologue and epilogue of a function. The external functions
are slower, but use less code space if more than one function saves
the same number of registers. The -mprolog-function option
is on by default if you optimize.
- -mspace
-
Try to make the code as small as possible. At present, this just turns
on the -mep and -mprolog-function options.
- -mtda=n
-
Put static or global variables whose size is n bytes or less into
the tiny data area that register "ep" points to. The tiny data
area can hold up to 256 bytes in total (128 bytes for byte references).
- -msda=n
-
Put static or global variables whose size is n bytes or less into
the small data area that register "gp" points to. The small data
area can hold up to 64 kilobytes.
- -mzda=n
-
Put static or global variables whose size is n bytes or less into
the first 32 kilobytes of memory.
- -mv850
-
Specify that the target processor is the V850.
- -mbig-switch
-
Generate code suitable for big switch tables. Use this option only if
the assembler/linker complain about out of range branches within a switch
table.
- -mapp-regs
-
This option will cause r2 and r5 to be used in the code generated by
the compiler. This setting is the default.
- -mno-app-regs
-
This option will cause r2 and r5 to be treated as fixed registers.
- -mv850e1
-
Specify that the target processor is the V850E1. The preprocessor
constants __v850e1__ and __v850e__ will be defined if
this option is used.
- -mv850e
-
Specify that the target processor is the V850E. The preprocessor
constant __v850e__ will be defined if this option is used.
If neither -mv850 nor -mv850e nor -mv850e1
are defined then a default target processor will be chosen and the
relevant __v850*__ preprocessor constant will be defined.
The preprocessor constants __v850 and __v851__ are always
defined, regardless of which processor variant is the target.
- -mdisable-callt
-
This option will suppress generation of the CALLT instruction for the
v850e and v850e1 flavors of the v850 architecture. The default is
-mno-disable-callt which allows the CALLT instruction to be used.
ARC Options
These options are defined for ARC implementations:
- -EL
-
Compile code for little endian mode. This is the default.
- -EB
-
Compile code for big endian mode.
- -mmangle-cpu
-
Prepend the name of the cpu to all public symbol names.
In multiple-processor systems, there are many ARC variants with different
instruction and register set characteristics. This flag prevents code
compiled for one cpu to be linked with code compiled for another.
No facility exists for handling variants that are ``almost identical''.
This is an all or nothing option.
- -mcpu=cpu
-
Compile code for ARC variant cpu.
Which variants are supported depend on the configuration.
All variants support -mcpu=base, this is the default.
- -mtext=text-section
-
- -mdata=data-section
-
- -mrodata=readonly-data-section
-
Put functions, data, and readonly data in text-section,
data-section, and readonly-data-section respectively
by default. This can be overridden with the "section" attribute.
NS32K Options
These are the -m options defined for the 32000 series. The default
values for these options depends on which style of 32000 was selected when
the compiler was configured; the defaults for the most common choices are
given below.
- -m32032
-
- -m32032
-
Generate output for a 32032. This is the default
when the compiler is configured for 32032 and 32016 based systems.
- -m32332
-
- -m32332
-
Generate output for a 32332. This is the default
when the compiler is configured for 32332-based systems.
- -m32532
-
- -m32532
-
Generate output for a 32532. This is the default
when the compiler is configured for 32532-based systems.
- -m32081
-
Generate output containing 32081 instructions for floating point.
This is the default for all systems.
- -m32381
-
Generate output containing 32381 instructions for floating point. This
also implies -m32081. The 32381 is only compatible with the 32332
and 32532 cpus. This is the default for the pc532-netbsd configuration.
- -mmulti-add
-
Try and generate multiply-add floating point instructions "polyF"
and "dotF". This option is only available if the -m32381
option is in effect. Using these instructions requires changes to
register allocation which generally has a negative impact on
performance. This option should only be enabled when compiling code
particularly likely to make heavy use of multiply-add instructions.
- -mnomulti-add
-
Do not try and generate multiply-add floating point instructions
"polyF" and "dotF". This is the default on all platforms.
- -msoft-float
-
Generate output containing library calls for floating point.
Warning: the requisite libraries may not be available.
- -mieee-compare
-
- -mno-ieee-compare
-
Control whether or not the compiler uses IEEE floating point
comparisons. These handle correctly the case where the result of a
comparison is unordered.
Warning: the requisite kernel support may not be available.
- -mnobitfield
-
Do not use the bit-field instructions. On some machines it is faster to
use shifting and masking operations. This is the default for the pc532.
- -mbitfield
-
Do use the bit-field instructions. This is the default for all platforms
except the pc532.
- -mrtd
-
Use a different function-calling convention, in which functions
that take a fixed number of arguments return pop their
arguments on return with the "ret" instruction.
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including "printf");
otherwise incorrect code will be generated for calls to those
functions.
In addition, seriously incorrect code will result if you call a
function with too many arguments. (Normally, extra arguments are
harmlessly ignored.)
This option takes its name from the 680x0 "rtd" instruction.
- -mregparam
-
Use a different function-calling convention where the first two arguments
are passed in registers.
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
- -mnoregparam
-
Do not pass any arguments in registers. This is the default for all
targets.
- -msb
-
It is OK to use the sb as an index register which is always loaded with
zero. This is the default for the pc532-netbsd target.
- -mnosb
-
The sb register is not available for use or has not been initialized to
zero by the run time system. This is the default for all targets except
the pc532-netbsd. It is also implied whenever -mhimem or
-fpic is set.
- -mhimem
-
Many ns32000 series addressing modes use displacements of up to 512MB.
If an address is above 512MB then displacements from zero can not be used.
This option causes code to be generated which can be loaded above 512MB.
This may be useful for operating systems or ROM code.
- -mnohimem
-
Assume code will be loaded in the first 512MB of virtual address space.
This is the default for all platforms.
AVR Options
These options are defined for AVR implementations:
- -mmcu=mcu
-
Specify ATMEL AVR instruction set or MCU type.
Instruction set avr1 is for the minimal AVR core, not supported by the C
compiler, only for assembler programs (MCU types: at90s1200, attiny10,
attiny11, attiny12, attiny15, attiny28).
Instruction set avr2 (default) is for the classic AVR core with up to
8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
at90c8534, at90s8535).
Instruction set avr3 is for the classic AVR core with up to 128K program
memory space (MCU types: atmega103, atmega603, at43usb320, at76c711).
Instruction set avr4 is for the enhanced AVR core with up to 8K program
memory space (MCU types: atmega8, atmega83, atmega85).
Instruction set avr5 is for the enhanced AVR core with up to 128K program
memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
atmega64, atmega128, at43usb355, at94k).
- -msize
-
Output instruction sizes to the asm file.
- -minit-stack=N
-
Specify the initial stack address, which may be a symbol or numeric value,
__stack is the default.
- -mno-interrupts
-
Generated code is not compatible with hardware interrupts.
Code size will be smaller.
- -mcall-prologues
-
Functions prologues/epilogues expanded as call to appropriate
subroutines. Code size will be smaller.
- -mno-tablejump
-
Do not generate tablejump insns which sometimes increase code size.
- -mtiny-stack
-
Change only the low 8 bits of the stack pointer.
MCore Options
These are the -m options defined for the Motorola M*Core
processors.
- -mhardlit
-
- -mno-hardlit
-
Inline constants into the code stream if it can be done in two
instructions or less.
- -mdiv
-
- -mno-div
-
Use the divide instruction. (Enabled by default).
- -mrelax-immediate
-
- -mno-relax-immediate
-
Allow arbitrary sized immediates in bit operations.
- -mwide-bitfields
-
- -mno-wide-bitfields
-
Always treat bit-fields as int-sized.
- -m4byte-functions
-
- -mno-4byte-functions
-
Force all functions to be aligned to a four byte boundary.
- -mcallgraph-data
-
- -mno-callgraph-data
-
Emit callgraph information.
- -mslow-bytes
-
- -mno-slow-bytes
-
Prefer word access when reading byte quantities.
- -mlittle-endian
-
- -mbig-endian
-
Generate code for a little endian target.
- -m210
-
- -m340
-
Generate code for the 210 processor.
IA-64 Options
These are the -m options defined for the Intel IA-64 architecture.
- -mbig-endian
-
Generate code for a big endian target. This is the default for HP-UX.
- -mlittle-endian
-
Generate code for a little endian target. This is the default for AIX5
and GNU/Linux.
- -mgnu-as
-
- -mno-gnu-as
-
Generate (or don't) code for the GNU assembler. This is the default.
- -mgnu-ld
-
- -mno-gnu-ld
-
Generate (or don't) code for the GNU linker. This is the default.
- -mno-pic
-
Generate code that does not use a global pointer register. The result
is not position independent code, and violates the IA-64 ABI.
- -mvolatile-asm-stop
-
- -mno-volatile-asm-stop
-
Generate (or don't) a stop bit immediately before and after volatile asm
statements.
- -mb-step
-
Generate code that works around Itanium B step errata.
- -mregister-names
-
- -mno-register-names
-
Generate (or don't) in, loc, and out register names for
the stacked registers. This may make assembler output more readable.
- -mno-sdata
-
- -msdata
-
Disable (or enable) optimizations that use the small data section. This may
be useful for working around optimizer bugs.
- -mconstant-gp
-
Generate code that uses a single constant global pointer value. This is
useful when compiling kernel code.
- -mauto-pic
-
Generate code that is self-relocatable. This implies -mconstant-gp.
This is useful when compiling firmware code.
- -minline-float-divide-min-latency
-
Generate code for inline divides of floating point values
using the minimum latency algorithm.
- -minline-float-divide-max-throughput
-
Generate code for inline divides of floating point values
using the maximum throughput algorithm.
- -minline-int-divide-min-latency
-
Generate code for inline divides of integer values
using the minimum latency algorithm.
- -minline-int-divide-max-throughput
-
Generate code for inline divides of integer values
using the maximum throughput algorithm.
- -minline-sqrt-min-latency
-
Generate code for inline square roots
using the minimum latency algorithm.
- -minline-sqrt-max-throughput
-
Generate code for inline square roots
using the maximum throughput algorithm.
- -mno-dwarf2-asm
-
- -mdwarf2-asm
-
Don't (or do) generate assembler code for the DWARF2 line number debugging
info. This may be useful when not using the GNU assembler.
- -mearly-stop-bits
-
- -mno-early-stop-bits
-
Allow stop bits to be placed earlier than immediately preceding the
instruction that triggered the stop bit. This can improve instruction
scheduling, but does not always do so.
- -mfixed-range=register-range
-
Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator can not use. This is
useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
- -mtls-size=tls-size
-
Specify bit size of immediate TLS offsets. Valid values are 14, 22, and
64.
- -mtune=cpu-type
-
Tune the instruction scheduling for a particular CPU, Valid values are
itanium, itanium1, merced, itanium2, and mckinley.
- -mt
-
- -pthread
-
Add support for multithreading using the POSIX threads library. This
option sets flags for both the preprocessor and linker. It does
not affect the thread safety of object code produced by the compiler or
that of libraries supplied with it. These are HP-UX specific flags.
- -milp32
-
- -mlp64
-
Generate code for a 32-bit or 64-bit environment.
The 32-bit environment sets int, long and pointer to 32 bits.
The 64-bit environment sets int to 32 bits and long and pointer
to 64 bits. These are HP-UX specific flags.
D30V Options
These -m options are defined for D30V implementations:
- -mextmem
-
Link the .text, .data, .bss, .strings,
.rodata, .rodata1, .data1 sections into external
memory, which starts at location 0x80000000.
- -mextmemory
-
Same as the -mextmem switch.
- -monchip
-
Link the .text section into onchip text memory, which starts at
location 0x0. Also link .data, .bss,
.strings, .rodata, .rodata1, .data1 sections
into onchip data memory, which starts at location 0x20000000.
- -mno-asm-optimize
-
- -masm-optimize
-
Disable (enable) passing -O to the assembler when optimizing.
The assembler uses the -O option to automatically parallelize
adjacent short instructions where possible.
- -mbranch-cost=n
-
Increase the internal costs of branches to n. Higher costs means
that the compiler will issue more instructions to avoid doing a branch.
The default is 2.
- -mcond-exec=n
-
Specify the maximum number of conditionally executed instructions that
replace a branch. The default is 4.
S/390 and zSeries Options
These are the -m options defined for the S/390 and zSeries architecture.
- -mhard-float
-
- -msoft-float
-
Use (do not use) the hardware floating-point instructions and registers
for floating-point operations. When -msoft-float is specified,
functions in libgcc.a will be used to perform floating-point
operations. When -mhard-float is specified, the compiler
generates IEEE floating-point instructions. This is the default.
- -mbackchain
-
- -mno-backchain
-
Generate (or do not generate) code which maintains an explicit
backchain within the stack frame that points to the caller's frame.
This may be needed to allow debugging using tools that do not understand
DWARF-2 call frame information. The default is not to generate the
backchain.
- -msmall-exec
-
- -mno-small-exec
-
Generate (or do not generate) code using the "bras" instruction
to do subroutine calls.
This only works reliably if the total executable size does not
exceed 64k. The default is to use the "basr" instruction instead,
which does not have this limitation.
- -m64
-
- -m31
-
When -m31 is specified, generate code compliant to the
GNU/Linux for S/390 ABI. When -m64 is specified, generate
code compliant to the GNU/Linux for zSeries ABI. This allows GCC in
particular to generate 64-bit instructions. For the s390
targets, the default is -m31, while the s390x
targets default to -m64.
- -mzarch
-
- -mesa
-
When -mzarch is specified, generate code using the
instructions available on z/Architecture.
When -mesa is specified, generate code using the
instructions available on ESA/390. Note that -mesa is
not possible with -m64.
When generating code compliant to the GNU/Linux for S/390 ABI,
the default is -mesa. When generating code compliant
to the GNU/Linux for zSeries ABI, the default is -mzarch.
- -mmvcle
-
- -mno-mvcle
-
Generate (or do not generate) code using the "mvcle" instruction
to perform block moves. When -mno-mvcle is specified,
use a "mvc" loop instead. This is the default.
- -mdebug
-
- -mno-debug
-
Print (or do not print) additional debug information when compiling.
The default is to not print debug information.
- -march=cpu-type
-
Generate code that will run on cpu-type, which is the name of a system
representing a certain processor type. Possible values for
cpu-type are g5, g6, z900, and z990.
When generating code using the instructions available on z/Architecture,
the default is -march=z900. Otherwise, the default is
-march=g5.
- -mtune=cpu-type
-
Tune to cpu-type everything applicable about the generated code,
except for the ABI and the set of available instructions.
The list of cpu-type values is the same as for -march.
The default is the value used for -march.
- -mfused-madd
-
- -mno-fused-madd
-
Generate code that uses (does not use) the floating point multiply and
accumulate instructions. These instructions are generated by default if
hardware floating point is used.
CRIS Options
These options are defined specifically for the CRIS ports.
- -march=architecture-type
-
- -mcpu=architecture-type
-
Generate code for the specified architecture. The choices for
architecture-type are v3, v8 and v10 for
respectively ETRAX 4, ETRAX 100, and ETRAX 100 LX.
Default is v0 except for cris-axis-linux-gnu, where the default is
v10.
- -mtune=architecture-type
-
Tune to architecture-type everything applicable about the generated
code, except for the ABI and the set of available instructions. The
choices for architecture-type are the same as for
-march=architecture-type.
- -mmax-stack-frame=n
-
Warn when the stack frame of a function exceeds n bytes.
- -melinux-stacksize=n
-
Only available with the cris-axis-aout target. Arranges for
indications in the program to the kernel loader that the stack of the
program should be set to n bytes.
- -metrax4
-
- -metrax100
-
The options -metrax4 and -metrax100 are synonyms for
-march=v3 and -march=v8 respectively.
- -mmul-bug-workaround
-
- -mno-mul-bug-workaround
-
Work around a bug in the "muls" and "mulu" instructions for CPU
models where it applies. This option is active by default.
- -mpdebug
-
Enable CRIS-specific verbose debug-related information in the assembly
code. This option also has the effect to turn off the #NO_APP
formatted-code indicator to the assembler at the beginning of the
assembly file.
- -mcc-init
-
Do not use condition-code results from previous instruction; always emit
compare and test instructions before use of condition codes.
- -mno-side-effects
-
Do not emit instructions with side-effects in addressing modes other than
post-increment.
- -mstack-align
-
- -mno-stack-align
-
- -mdata-align
-
- -mno-data-align
-
- -mconst-align
-
- -mno-const-align
-
These options (no-options) arranges (eliminate arrangements) for the
stack-frame, individual data and constants to be aligned for the maximum
single data access size for the chosen CPU model. The default is to
arrange for 32-bit alignment. ABI details such as structure layout are
not affected by these options.
- -m32-bit
-
- -m16-bit
-
- -m8-bit
-
Similar to the stack- data- and const-align options above, these options
arrange for stack-frame, writable data and constants to all be 32-bit,
16-bit or 8-bit aligned. The default is 32-bit alignment.
- -mno-prologue-epilogue
-
- -mprologue-epilogue
-
With -mno-prologue-epilogue, the normal function prologue and
epilogue that sets up the stack-frame are omitted and no return
instructions or return sequences are generated in the code. Use this
option only together with visual inspection of the compiled code: no
warnings or errors are generated when call-saved registers must be saved,
or storage for local variable needs to be allocated.
- -mno-gotplt
-
- -mgotplt
-
With -fpic and -fPIC, don't generate (do generate)
instruction sequences that load addresses for functions from the PLT part
of the GOT rather than (traditional on other architectures) calls to the
PLT. The default is -mgotplt.
- -maout
-
Legacy no-op option only recognized with the cris-axis-aout target.
- -melf
-
Legacy no-op option only recognized with the cris-axis-elf and
cris-axis-linux-gnu targets.
- -melinux
-
Only recognized with the cris-axis-aout target, where it selects a
GNU/linux-like multilib, include files and instruction set for
-march=v8.
- -mlinux
-
Legacy no-op option only recognized with the cris-axis-linux-gnu target.
- -sim
-
This option, recognized for the cris-axis-aout and cris-axis-elf arranges
to link with input-output functions from a simulator library. Code,
initialized data and zero-initialized data are allocated consecutively.
- -sim2
-
Like -sim, but pass linker options to locate initialized data at
0x40000000 and zero-initialized data at 0x80000000.
MMIX Options
These options are defined for the MMIX:
- -mlibfuncs
-
- -mno-libfuncs
-
Specify that intrinsic library functions are being compiled, passing all
values in registers, no matter the size.
- -mepsilon
-
- -mno-epsilon
-
Generate floating-point comparison instructions that compare with respect
to the "rE" epsilon register.
- -mabi=mmixware
-
- -mabi=gnu
-
Generate code that passes function parameters and return values that (in
the called function) are seen as registers $0 and up, as opposed to
the GNU ABI which uses global registers $231 and up.
- -mzero-extend
-
- -mno-zero-extend
-
When reading data from memory in sizes shorter than 64 bits, use (do not
use) zero-extending load instructions by default, rather than
sign-extending ones.
- -mknuthdiv
-
- -mno-knuthdiv
-
Make the result of a division yielding a remainder have the same sign as
the divisor. With the default, -mno-knuthdiv, the sign of the
remainder follows the sign of the dividend. Both methods are
arithmetically valid, the latter being almost exclusively used.
- -mtoplevel-symbols
-
- -mno-toplevel-symbols
-
Prepend (do not prepend) a : to all global symbols, so the assembly
code can be used with the "PREFIX" assembly directive.
- -melf
-
Generate an executable in the ELF format, rather than the default
mmo format used by the mmix simulator.
- -mbranch-predict
-
- -mno-branch-predict
-
Use (do not use) the probable-branch instructions, when static branch
prediction indicates a probable branch.
- -mbase-addresses
-
- -mno-base-addresses
-
Generate (do not generate) code that uses base addresses. Using a
base address automatically generates a request (handled by the assembler
and the linker) for a constant to be set up in a global register. The
register is used for one or more base address requests within the range 0
to 255 from the value held in the register. The generally leads to short
and fast code, but the number of different data items that can be
addressed is limited. This means that a program that uses lots of static
data may require -mno-base-addresses.
- -msingle-exit
-
- -mno-single-exit
-
Force (do not force) generated code to have a single exit point in each
function.
PDP-11 Options
These options are defined for the PDP-11:
- -mfpu
-
Use hardware FPP floating point. This is the default. (FIS floating
point on the PDP-11/40 is not supported.)
- -msoft-float
-
Do not use hardware floating point.
- -mac0
-
Return floating-point results in ac0 (fr0 in Unix assembler syntax).
- -mno-ac0
-
Return floating-point results in memory. This is the default.
- -m40
-
Generate code for a PDP-11/40.
- -m45
-
Generate code for a PDP-11/45. This is the default.
- -m10
-
Generate code for a PDP-11/10.
- -mbcopy-builtin
-
Use inline "movstrhi" patterns for copying memory. This is the
default.
- -mbcopy
-
Do not use inline "movstrhi" patterns for copying memory.
- -mint16
-
- -mno-int32
-
Use 16-bit "int". This is the default.
- -mint32
-
- -mno-int16
-
Use 32-bit "int".
- -mfloat64
-
- -mno-float32
-
Use 64-bit "float". This is the default.
- -mfloat32
-
- -mno-float64
-
Use 32-bit "float".
- -mabshi
-
Use "abshi2" pattern. This is the default.
- -mno-abshi
-
Do not use "abshi2" pattern.
- -mbranch-expensive
-
Pretend that branches are expensive. This is for experimenting with
code generation only.
- -mbranch-cheap
-
Do not pretend that branches are expensive. This is the default.
- -msplit
-
Generate code for a system with split I&D.
- -mno-split
-
Generate code for a system without split I&D. This is the default.
- -munix-asm
-
Use Unix assembler syntax. This is the default when configured for
pdp11-*-bsd.
- -mdec-asm
-
Use DEC assembler syntax. This is the default when configured for any
PDP-11 target other than pdp11-*-bsd.
Xstormy16 Options
These options are defined for Xstormy16:
- -msim
-
Choose startup files and linker script suitable for the simulator.
FRV Options
- -mgpr-32
-
Only use the first 32 general purpose registers.
- -mgpr-64
-
Use all 64 general purpose registers.
- -mfpr-32
-
Use only the first 32 floating point registers.
- -mfpr-64
-
Use all 64 floating point registers
- -mhard-float
-
Use hardware instructions for floating point operations.
- -msoft-float
-
Use library routines for floating point operations.
- -malloc-cc
-
Dynamically allocate condition code registers.
- -mfixed-cc
-
Do not try to dynamically allocate condition code registers, only
use "icc0" and "fcc0".
- -mdword
-
Change ABI to use double word insns.
- -mno-dword
-
Do not use double word instructions.
- -mdouble
-
Use floating point double instructions.
- -mno-double
-
Do not use floating point double instructions.
- -mmedia
-
Use media instructions.
- -mno-media
-
Do not use media instructions.
- -mmuladd
-
Use multiply and add/subtract instructions.
- -mno-muladd
-
Do not use multiply and add/subtract instructions.
- -mlibrary-pic
-
Enable PIC support for building libraries
- -macc-4
-
Use only the first four media accumulator registers.
- -macc-8
-
Use all eight media accumulator registers.
- -mpack
-
Pack VLIW instructions.
- -mno-pack
-
Do not pack VLIW instructions.
- -mno-eflags
-
Do not mark ABI switches in e_flags.
- -mcond-move
-
Enable the use of conditional-move instructions (default).
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mno-cond-move
-
Disable the use of conditional-move instructions.
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mscc
-
Enable the use of conditional set instructions (default).
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mno-scc
-
Disable the use of conditional set instructions.
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mcond-exec
-
Enable the use of conditional execution (default).
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mno-cond-exec
-
Disable the use of conditional execution.
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mvliw-branch
-
Run a pass to pack branches into VLIW instructions (default).
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mno-vliw-branch
-
Do not run a pass to pack branches into VLIW instructions.
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mmulti-cond-exec
-
Enable optimization of "&&" and "||" in conditional execution
(default).
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mno-multi-cond-exec
-
Disable optimization of "&&" and "||" in conditional execution.
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mnested-cond-exec
-
Enable nested conditional execution optimizations (default).
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mno-nested-cond-exec
-
Disable nested conditional execution optimizations.
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
- -mtomcat-stats
-
Cause gas to print out tomcat statistics.
- -mcpu=cpu
-
Select the processor type for which to generate code. Possible values are
simple, tomcat, fr500, fr400, fr300,
frv.
Xtensa Options
These options are supported for Xtensa targets:
- -mconst16
-
- -mno-const16
-
Enable or disable use of "CONST16" instructions for loading
constant values. The "CONST16" instruction is currently not a
standard option from Tensilica. When enabled, "CONST16"
instructions are always used in place of the standard "L32R"
instructions. The use of "CONST16" is enabled by default only if
the "L32R" instruction is not available.
- -mfused-madd
-
- -mno-fused-madd
-
Enable or disable use of fused multiply/add and multiply/subtract
instructions in the floating-point option. This has no effect if the
floating-point option is not also enabled. Disabling fused multiply/add
and multiply/subtract instructions forces the compiler to use separate
instructions for the multiply and add/subtract operations. This may be
desirable in some cases where strict IEEE 754-compliant results are
required: the fused multiply add/subtract instructions do not round the
intermediate result, thereby producing results with more bits of
precision than specified by the IEEE standard. Disabling fused multiply
add/subtract instructions also ensures that the program output is not
sensitive to the compiler's ability to combine multiply and add/subtract
operations.
- -mtext-section-literals
-
- -mno-text-section-literals
-
Control the treatment of literal pools. The default is
-mno-text-section-literals, which places literals in a separate
section in the output file. This allows the literal pool to be placed
in a data RAM/ROM, and it also allows the linker to combine literal
pools from separate object files to remove redundant literals and
improve code size. With -mtext-section-literals, the literals
are interspersed in the text section in order to keep them as close as
possible to their references. This may be necessary for large assembly
files.
- -mtarget-align
-
- -mno-target-align
-
When this option is enabled, GCC instructs the assembler to
automatically align instructions to reduce branch penalties at the
expense of some code density. The assembler attempts to widen density
instructions to align branch targets and the instructions following call
instructions. If there are not enough preceding safe density
instructions to align a target, no widening will be performed. The
default is -mtarget-align. These options do not affect the
treatment of auto-aligned instructions like "LOOP", which the
assembler will always align, either by widening density instructions or
by inserting no-op instructions.
- -mlongcalls
-
- -mno-longcalls
-
When this option is enabled, GCC instructs the assembler to translate
direct calls to indirect calls unless it can determine that the target
of a direct call is in the range allowed by the call instruction. This
translation typically occurs for calls to functions in other source
files. Specifically, the assembler translates a direct "CALL"
instruction into an "L32R" followed by a "CALLX" instruction.
The default is -mno-longcalls. This option should be used in
programs where the call target can potentially be out of range. This
option is implemented in the assembler, not the compiler, so the
assembly code generated by GCC will still show direct call
instructions---look at the disassembled object code to see the actual
instructions. Note that the assembler will use an indirect call for
every cross-file call, not just those that really will be out of range.