Adjunto 'EasyPIO.h'
Descargar 1 /* EasyPIO.h
2 * Created: 8 October 2013
3 * Sarah_Lichtman@hmc.edu & Joshua_Vasquez@hmc.edu
4 * Last Modified: 5 April 2014
5 * Sarah_Lichtman@hmc.edu & Joshua_Vasquez@hmc.edu
6 * 15 August 2014
7 * David_Harris@hmc.edu (simplify pinMode)
8 *
9 * Library to simplify memory access on Raspberry Pi (Broadcom BCM2835).
10 * Must be run with root permissions using sudo.
11 */
12
13 #ifndef EASY_PIO_H
14 #define EASY_PIO_H
15
16 // Include statements
17 #include <sys/mman.h>
18 #include <stdio.h>
19 #include <stdlib.h>
20 #include <fcntl.h>
21 #include <unistd.h>
22
23 /////////////////////////////////////////////////////////////////////
24 // Constants
25 /////////////////////////////////////////////////////////////////////
26
27 // GPIO FSEL Types
28 #define INPUT 0
29 #define OUTPUT 1
30 #define ALT0 4
31 #define ALT1 5
32 #define ALT2 6
33 #define ALT3 7
34 #define ALT4 3
35 #define ALT5 2
36
37 // Clock Manager Bitfield offsets:
38 #define PWM_CLK_PASSWORD 0x5a000000
39 #define PWM_MASH 9
40 #define PWM_KILL 5
41 #define PWM_ENAB 4
42 #define PWM_SRC 0
43
44 // PWM Constants
45 #define PLL_FREQUENCY 500000000 // default PLLD value is 500 [MHz]
46 #define CM_FREQUENCY 25000000 // max pwm clk is 25 [MHz]
47 #define PLL_CLOCK_DIVISOR (PLL_FREQUENCY / CM_FREQUENCY)
48
49 /////////////////////////////////////////////////////////////////////
50 // Memory Map
51 /////////////////////////////////////////////////////////////////////
52
53 // These #define values are specific to the BCM2835, taken from "BCM2835 ARM Peripherals"
54 //#define BCM2835_PERI_BASE 0x20000000
55 // Updated to BCM2836 for Raspberry Pi 2.0 Fall 2015 dmh
56 #define BCM2835_PERI_BASE 0x3F000000
57
58 #define GPIO_BASE (BCM2835_PERI_BASE + 0x200000)
59 #define UART_BASE (BCM2835_PERI_BASE + 0x201000)
60 #define SPI0_BASE (BCM2835_PERI_BASE + 0x204000)
61 #define PWM_BASE (BCM2835_PERI_BASE + 0x20c000)
62
63 #define SYS_TIMER_BASE (BCM2835_PERI_BASE + 0x3000)
64 #define ARM_TIMER_BASE (BCM2835_PERI_BASE + 0xB000)
65
66 #define CM_PWM_BASE (BCM2835_PERI_BASE + 0x101000)
67
68 #define BLOCK_SIZE (4*1024)
69
70 // Pointers that will be memory mapped when pioInit() is called
71 volatile unsigned int *gpio; //pointer to base of gpio
72 volatile unsigned int *spi; //pointer to base of spi registers
73 volatile unsigned int *pwm;
74
75 volatile unsigned int *sys_timer;
76 volatile unsigned int *arm_timer; // pointer to base of arm timer registers
77
78 volatile unsigned int *uart;
79 volatile unsigned int *cm_pwm;
80
81 /////////////////////////////////////////////////////////////////////
82 // GPIO Registers
83 /////////////////////////////////////////////////////////////////////
84
85 // Function Select
86 #define GPFSEL ((volatile unsigned int *) (gpio + 0))
87 typedef struct
88 {
89 unsigned FSEL0 : 3;
90 unsigned FSEL1 : 3;
91 unsigned FSEL2 : 3;
92 unsigned FSEL3 : 3;
93 unsigned FSEL4 : 3;
94 unsigned FSEL5 : 3;
95 unsigned FSEL6 : 3;
96 unsigned FSEL7 : 3;
97 unsigned FSEL8 : 3;
98 unsigned FSEL9 : 3;
99 unsigned : 2;
100 }gpfsel0bits;
101 #define GPFSEL0bits (*(volatile gpfsel0bits*) (gpio + 0))
102 #define GPFSEL0 (*(volatile unsigned int*) (gpio + 0))
103
104 typedef struct
105 {
106 unsigned FSEL10 : 3;
107 unsigned FSEL11 : 3;
108 unsigned FSEL12 : 3;
109 unsigned FSEL13 : 3;
110 unsigned FSEL14 : 3;
111 unsigned FSEL15 : 3;
112 unsigned FSEL16 : 3;
113 unsigned FSEL17 : 3;
114 unsigned FSEL18 : 3;
115 unsigned FSEL19 : 3;
116 unsigned : 2;
117 }gpfsel1bits;
118 #define GPFSEL1bits (*(volatile gpfsel1bits*) (gpio + 1))
119 #define GPFSEL1 (*(volatile unsigned int*) (gpio + 1))
120
121 typedef struct
122 {
123 unsigned FSEL20 : 3;
124 unsigned FSEL21 : 3;
125 unsigned FSEL22 : 3;
126 unsigned FSEL23 : 3;
127 unsigned FSEL24 : 3;
128 unsigned FSEL25 : 3;
129 unsigned FSEL26 : 3;
130 unsigned FSEL27 : 3;
131 unsigned FSEL28 : 3;
132 unsigned FSEL29 : 3;
133 unsigned : 2;
134 }gpfsel2bits;
135 #define GPFSEL2bits (* (volatile gpfsel2bits*) (gpio + 2))
136 #define GPFSEL2 (* (volatile unsigned int *) (gpio + 2))
137
138 typedef struct
139 {
140 unsigned FSEL30 : 3;
141 unsigned FSEL31 : 3;
142 unsigned FSEL32 : 3;
143 unsigned FSEL33 : 3;
144 unsigned FSEL34 : 3;
145 unsigned FSEL35 : 3;
146 unsigned FSEL36 : 3;
147 unsigned FSEL37 : 3;
148 unsigned FSEL38 : 3;
149 unsigned FSEL39 : 3;
150 unsigned : 2;
151 }gpfsel3bits;
152 #define GPFSEL3bits (* (volatile gpfsel3bits*) (gpio + 3))
153 #define GPFSEL3 (* (volatile unsigned int *) (gpio + 3))
154
155
156 typedef struct
157 {
158 unsigned FSEL40 : 3;
159 unsigned FSEL41 : 3;
160 unsigned FSEL42 : 3;
161 unsigned FSEL43 : 3;
162 unsigned FSEL44 : 3;
163 unsigned FSEL45 : 3;
164 unsigned FSEL46 : 3;
165 unsigned FSEL47 : 3;
166 unsigned FSEL48 : 3;
167 unsigned FSEL49 : 3;
168 unsigned : 2;
169 }gpfsel4bits;
170 #define GPFSEL4bits (* (volatile gpfsel4bits*) (gpio + 4))
171 #define GPFSEL4 (* (volatile unsigned int *) (gpio + 4))
172
173 typedef struct
174 {
175 unsigned FSEL50 : 3;
176 unsigned FSEL51 : 3;
177 unsigned FSEL52 : 3;
178 unsigned FSEL53 : 3;
179 unsigned : 20;
180 }gpfsel5bits;
181 #define GPFSEL5bits (* (volatile gpfsel5bits*) (gpio + 5))
182 #define GPFSEL5 (* (volatile unsigned int *) (gpio + 5))
183
184 // Pin Output Select
185 #define GPSET ((volatile unsigned int *) (gpio + 7))
186 typedef struct
187 {
188 unsigned SET0 : 1;
189 unsigned SET1 : 1;
190 unsigned SET2 : 1;
191 unsigned SET3 : 1;
192 unsigned SET4 : 1;
193 unsigned SET5 : 1;
194 unsigned SET6 : 1;
195 unsigned SET7 : 1;
196 unsigned SET8 : 1;
197 unsigned SET9 : 1;
198 unsigned SET10 : 1;
199 unsigned SET11 : 1;
200 unsigned SET12 : 1;
201 unsigned SET13 : 1;
202 unsigned SET14 : 1;
203 unsigned SET15 : 1;
204 unsigned SET16 : 1;
205 unsigned SET17 : 1;
206 unsigned SET18 : 1;
207 unsigned SET19 : 1;
208 unsigned SET20 : 1;
209 unsigned SET21 : 1;
210 unsigned SET22 : 1;
211 unsigned SET23 : 1;
212 unsigned SET24 : 1;
213 unsigned SET25 : 1;
214 unsigned SET26 : 1;
215 unsigned SET27 : 1;
216 unsigned SET28 : 1;
217 unsigned SET29 : 1;
218 unsigned SET30 : 1;
219 unsigned SET31 : 1;
220 }gpset0bits;
221 #define GPSET0bits (* (volatile gpset0bits*) (gpio + 7))
222 #define GPSET0 (* (volatile unsigned int *) (gpio + 7))
223
224 typedef struct
225 {
226 unsigned SET32 : 1;
227 unsigned SET33 : 1;
228 unsigned SET34 : 1;
229 unsigned SET35 : 1;
230 unsigned SET36 : 1;
231 unsigned SET37 : 1;
232 unsigned SET38 : 1;
233 unsigned SET39 : 1;
234 unsigned SET40 : 1;
235 unsigned SET41 : 1;
236 unsigned SET42 : 1;
237 unsigned SET43 : 1;
238 unsigned SET44 : 1;
239 unsigned SET45 : 1;
240 unsigned SET46 : 1;
241 unsigned SET47 : 1;
242 unsigned SET48 : 1;
243 unsigned SET49 : 1;
244 unsigned SET50 : 1;
245 unsigned SET51 : 1;
246 unsigned SET52 : 1;
247 unsigned SET53 : 1;
248 unsigned : 10;
249 }gpset1bits;
250 #define GPSET1bits (* (volatile gpset1bits*) (gpio + 8))
251 #define GPSET1 (* (volatile unsigned int *) (gpio + 8))
252
253 // Pin Output Clear
254 #define GPCLR ((volatile unsigned int *) (gpio + 10))
255 typedef struct
256 {
257 unsigned CLR0 : 1;
258 unsigned CLR1 : 1;
259 unsigned CLR2 : 1;
260 unsigned CLR3 : 1;
261 unsigned CLR4 : 1;
262 unsigned CLR5 : 1;
263 unsigned CLR6 : 1;
264 unsigned CLR7 : 1;
265 unsigned CLR8 : 1;
266 unsigned CLR9 : 1;
267 unsigned CLR10 : 1;
268 unsigned CLR11 : 1;
269 unsigned CLR12 : 1;
270 unsigned CLR13 : 1;
271 unsigned CLR14 : 1;
272 unsigned CLR15 : 1;
273 unsigned CLR16 : 1;
274 unsigned CLR17 : 1;
275 unsigned CLR18 : 1;
276 unsigned CLR19 : 1;
277 unsigned CLR20 : 1;
278 unsigned CLR21 : 1;
279 unsigned CLR22 : 1;
280 unsigned CLR23 : 1;
281 unsigned CLR24 : 1;
282 unsigned CLR25 : 1;
283 unsigned CLR26 : 1;
284 unsigned CLR27 : 1;
285 unsigned CLR28 : 1;
286 unsigned CLR29 : 1;
287 unsigned CLR30 : 1;
288 unsigned CLR31 : 1;
289 }gpclr0bits;
290 #define GPCLR0bits (* (volatile gpclr0bits*) (gpio + 10))
291 #define GPCLR0 (* (volatile unsigned int *) (gpio + 10))
292
293 typedef struct
294 {
295 unsigned CLR32 : 1;
296 unsigned CLR33 : 1;
297 unsigned CLR34 : 1;
298 unsigned CLR35 : 1;
299 unsigned CLR36 : 1;
300 unsigned CLR37 : 1;
301 unsigned CLR38 : 1;
302 unsigned CLR39 : 1;
303 unsigned CLR40 : 1;
304 unsigned CLR41 : 1;
305 unsigned CLR42 : 1;
306 unsigned CLR43 : 1;
307 unsigned CLR44 : 1;
308 unsigned CLR45 : 1;
309 unsigned CLR46 : 1;
310 unsigned CLR47 : 1;
311 unsigned CLR48 : 1;
312 unsigned CLR49 : 1;
313 unsigned CLR50 : 1;
314 unsigned CLR51 : 1;
315 unsigned CLR52 : 1;
316 unsigned CLR53 : 1;
317 unsigned : 10;
318 }gpclr1bits;
319 #define GPCLR1bits (* (volatile gpclr1bits*) (gpio + 11))
320 #define GPCLR1 (* (volatile unsigned int *) (gpio + 11))
321
322 // Pin Level
323 #define GPLEV ((volatile unsigned int *) (gpio + 13))
324 typedef struct
325 {
326 unsigned LEV0 : 1;
327 unsigned LEV1 : 1;
328 unsigned LEV2 : 1;
329 unsigned LEV3 : 1;
330 unsigned LEV4 : 1;
331 unsigned LEV5 : 1;
332 unsigned LEV6 : 1;
333 unsigned LEV7 : 1;
334 unsigned LEV8 : 1;
335 unsigned LEV9 : 1;
336 unsigned LEV10 : 1;
337 unsigned LEV11 : 1;
338 unsigned LEV12 : 1;
339 unsigned LEV13 : 1;
340 unsigned LEV14 : 1;
341 unsigned LEV15 : 1;
342 unsigned LEV16 : 1;
343 unsigned LEV17 : 1;
344 unsigned LEV18 : 1;
345 unsigned LEV19 : 1;
346 unsigned LEV20 : 1;
347 unsigned LEV21 : 1;
348 unsigned LEV22 : 1;
349 unsigned LEV23 : 1;
350 unsigned LEV24 : 1;
351 unsigned LEV25 : 1;
352 unsigned LEV26 : 1;
353 unsigned LEV27 : 1;
354 unsigned LEV28 : 1;
355 unsigned LEV29 : 1;
356 unsigned LEV30 : 1;
357 unsigned LEV31 : 1;
358 }gplev0bits;
359 #define GPLEV0bits (* (volatile gplev0bits*) (gpio + 13))
360 #define GPLEV0 (* (volatile unsigned int *) (gpio + 13))
361
362
363 typedef struct
364 {
365 unsigned LEV32 : 1;
366 unsigned LEV33 : 1;
367 unsigned LEV34 : 1;
368 unsigned LEV35 : 1;
369 unsigned LEV36 : 1;
370 unsigned LEV37 : 1;
371 unsigned LEV38 : 1;
372 unsigned LEV39 : 1;
373 unsigned LEV40 : 1;
374 unsigned LEV41 : 1;
375 unsigned LEV42 : 1;
376 unsigned LEV43 : 1;
377 unsigned LEV44 : 1;
378 unsigned LEV45 : 1;
379 unsigned LEV46 : 1;
380 unsigned LEV47 : 1;
381 unsigned LEV48 : 1;
382 unsigned LEV49 : 1;
383 unsigned LEV50 : 1;
384 unsigned LEV51 : 1;
385 unsigned LEV52 : 1;
386 unsigned LEV53 : 1;
387 unsigned : 10;
388 }gplev1bits;
389 #define GPLEV1bits (* (volatile gplev1bits*) (gpio + 14))
390 #define GPLEV1 (* (volatile unsigned int *) (gpio + 14))
391
392 /////////////////////////////////////////////////////////////////////
393 // SPI Registers
394 /////////////////////////////////////////////////////////////////////
395
396 typedef struct
397 {
398 unsigned CS :2;
399 unsigned CPHA :1;
400 unsigned CPOL :1;
401 unsigned CLEAR :2;
402 unsigned CSPOL :1;
403 unsigned TA :1;
404 unsigned DMAEN :1;
405 unsigned INTD :1;
406 unsigned INTR :1;
407 unsigned ADCS :1;
408 unsigned REN :1;
409 unsigned LEN :1;
410 unsigned LMONO :1;
411 unsigned TE_EN :1;
412 unsigned DONE :1;
413 unsigned RXD :1;
414 unsigned TXD :1;
415 unsigned RXR :1;
416 unsigned RXF :1;
417 unsigned CSPOL0 :1;
418 unsigned CSPOL1 :1;
419 unsigned CSPOL2 :1;
420 unsigned DMA_LEN :1;
421 unsigned LEN_LONG :1;
422 unsigned :6;
423 }spi0csbits;
424 #define SPI0CSbits (* (volatile spi0csbits*) (spi + 0))
425 #define SPI0CS (* (volatile unsigned int *) (spi + 0))
426
427 #define SPI0FIFO (* (volatile unsigned int *) (spi + 1))
428 #define SPI0CLK (* (volatile unsigned int *) (spi + 2))
429 #define SPI0DLEN (* (volatile unsigned int *) (spi + 3))
430
431 /////////////////////////////////////////////////////////////////////
432 // System Timer Registers
433 /////////////////////////////////////////////////////////////////////
434
435 typedef struct
436 {
437 unsigned M0 :1;
438 unsigned M1 :1;
439 unsigned M2 :1;
440 unsigned M3 :1;
441 unsigned :28;
442 }sys_timer_csbits;
443 #define SYS_TIMER_CSbits (*(volatile sys_timer_csbits*) (sys_timer + 0))
444 #define SYS_TIMER_CS (* (volatile unsigned int*)(sys_timer + 0))
445
446 #define SYS_TIMER_CLO (* (volatile unsigned int*)(sys_timer + 1))
447 #define SYS_TIMER_CHI (* (volatile unsigned int*)(sys_timer + 2))
448 #define SYS_TIMER_C0 (* (volatile unsigned int*)(sys_timer + 3))
449 #define SYS_TIMER_C1 (* (volatile unsigned int*)(sys_timer + 4))
450 #define SYS_TIMER_C2 (* (volatile unsigned int*)(sys_timer + 5))
451 #define SYS_TIMER_C3 (* (volatile unsigned int*)(sys_timer + 6))
452
453 /////////////////////////////////////////////////////////////////////
454 // ARM Interrupt Registers
455 /////////////////////////////////////////////////////////////////////
456
457 #define IRQ_PENDING_BASIC (* (volatile unsigned int *) (arm_timer + 128))
458 #define IRQ_PENDING1 (* (volatile unsigned int *) (arm_timer + 129))
459 #define IRQ_PENDING2 (* (volatile unsigned int *) (arm_timer + 130))
460
461 #define IRQ_ENABLE1 (* (volatile unsigned int *) (arm_timer + 132))
462 #define IRQ_ENABLE2 (* (volatile unsigned int *) (arm_timer + 133))
463 #define IRQ_ENABLE_BASIC (* (volatile unsigned int *) (arm_timer + 134))
464 #define IRQ_DISABLE1 (* (volatile unsigned int *) (arm_timer + 135))
465 #define IRQ_DISABLE2 (* (volatile unsigned int *) (arm_timer + 136))
466 #define IRQ_DISABLE_BASIC (* (volatile unsigned int *) (arm_timer + 137))
467
468 /////////////////////////////////////////////////////////////////////
469 // ARM Timer Registers
470 /////////////////////////////////////////////////////////////////////
471
472 #define ARM_TIMER_LOAD (* (volatile unsigned int *) (arm_timer + 256))
473 //TODO: make timer control struct
474 #define ARM_TIMER_CONTROL (* (volatile unsigned int *) (arm_timer + 258))
475 #define ARM_TIMER_IRQCLR (* (volatile unsigned int*) (arm_timer + 259))
476 #define ARM_TIMER_RAWIRQ (* (volatile unsigned int *) (arm_timer + 260))
477 #define ARM_TIMER_RELOAD (* (volatile unsigned int *) (arm_timer + 262))
478 #define ARM_TIMER_DIV (* (volatile unsigned int *) (arm_timer + 263))
479
480 /////////////////////////////////////////////////////////////////////
481 // UART Registers
482 /////////////////////////////////////////////////////////////////////
483
484 typedef struct
485 {
486 unsigned DATA : 8;
487 unsigned FE : 1;
488 unsigned PE : 1;
489 unsigned BE : 1;
490 unsigned OE : 1;
491 unsigned : 20;
492 } uart_drbits;
493 #define UART_DRbits (* (volatile uart_drbits*) (uart + 0))
494 #define UART_DR (*(volatile unsigned int *) (uart + 0))
495
496 typedef struct
497 {
498 unsigned int CTS : 1;
499 unsigned int DSR : 1;
500 unsigned int DCD : 1;
501 unsigned int BUSY : 1;
502 unsigned int RXFE : 1;
503 unsigned int TXFF : 1;
504 unsigned int RXFF : 1;
505 unsigned int TXFE : 1;
506 unsigned int RI : 1;
507 unsigned int : 24;
508 } uart_frbits;
509 #define UART_FRbits (*(volatile uart_frbits*) (uart + 6))
510 #define UART_FR (*(volatile unsigned int *) (uart + 6))
511
512 typedef struct
513 {
514 unsigned int IBRD : 16;
515 unsigned int : 16;
516 } uart_ibrdbits;
517 #define UART_IBRDbits (*(volatile uart_ibrdbits*) (uart + 9))
518 #define UART_IBRD (*(volatile unsigned int *) (uart + 9))
519
520 typedef struct
521 {
522 unsigned int FBRD : 6;
523 unsigned int : 26;
524 } uart_fbrdbits;
525 #define UART_FBRDbits (*(volatile uart_fbrdbits*) (uart + 10))
526 #define UART_FBRD (*(volatile unsigned int *) (uart + 10))
527
528 typedef struct
529 {
530 unsigned int BRK : 1;
531 unsigned int PEN : 1;
532 unsigned int EPS : 1;
533 unsigned int STP2 : 1;
534 unsigned int FEN : 1;
535 unsigned int WLEN : 2;
536 unsigned int SPS : 1;
537 unsigned int : 24;
538 } uart_lcrhbits;
539 #define UART_LCRHbits (* (volatile uart_lcrhbits*) (uart + 11))
540 #define UART_LCRH (*(volatile unsigned int *) (uart + 11))
541
542 typedef struct
543 {
544 unsigned int UARTEN : 1;
545 unsigned int SIREN : 1;
546 unsigned int SIRLP : 1;
547 unsigned int : 4;
548 unsigned int LBE : 1;
549 unsigned int TXE : 1;
550 unsigned int RXE : 1;
551 unsigned int DTR : 1;
552 unsigned int RTS : 1;
553 unsigned int OUT1 : 1;
554 unsigned int OUT2 : 1;
555 unsigned int RTSEN : 1;
556 unsigned int CTSEN : 1;
557 unsigned int : 16;
558 } uart_crbits;
559 #define UART_CRbits (* (volatile uart_crbits*) (uart + 12))
560 #define UART_CR (*(volatile unsigned int *) (uart + 12))
561
562
563 typedef struct
564 {
565 unsigned int RIRMIS : 1;
566 unsigned int CTSRMIS : 1;
567 unsigned int DCDRMIS : 1;
568 unsigned int DSRRMIS : 1;
569 unsigned int RXRIS : 1;
570 unsigned int TXRIS : 1;
571 unsigned int RTRIS : 1;
572 unsigned int FERIS : 1;
573 unsigned int PERIS : 1;
574 unsigned int BERIS : 1;
575 unsigned int OERIS : 1;
576 unsigned int : 21;
577 } uart_risbits;
578 #define UART_RISbits (* (volatile uart_risbits*) (uart + 15))
579 #define UART_RIS (*(volatile unsigned int *) (uart + 15))
580
581 /////////////////////////////////////////////////////////////////////
582 // PWM Registers
583 /////////////////////////////////////////////////////////////////////
584
585 typedef struct
586 {
587 unsigned PWEN1 :1;
588 unsigned MODE1 :1;
589 unsigned RPTL1 :1;
590 unsigned SBIT1 :1;
591 unsigned POLA1 :1;
592 unsigned USEF1 :1;
593 unsigned CLRF1 :1;
594 unsigned MSEN1 :1;
595 unsigned PWEN2 :1;
596 unsigned MODE2 :1;
597 unsigned RPTL2 :1;
598 unsigned SBIT2 :1;
599 unsigned POLA2 :1;
600 unsigned USEF2 :1;
601 unsigned :1;
602 unsigned MSEN2 :1;
603 unsigned :16;
604 } pwm_ctlbits;
605 #define PWM_CTLbits (* (volatile pwm_ctlbits *) (pwm + 0))
606 #define PWM_CTL (*(volatile unsigned int *) (pwm + 0))
607
608 #define PWM_RNG1 (*(volatile unsigned int *) (pwm + 4))
609 #define PWM_DAT1 (*(volatile unsigned int *)(pwm + 5))
610
611 /////////////////////////////////////////////////////////////////////
612 // Clock Manager Registers
613 /////////////////////////////////////////////////////////////////////
614
615 typedef struct
616 {
617 unsigned SRC :4;
618 unsigned ENAB :1;
619 unsigned KILL :1;
620 unsigned :1;
621 unsigned BUSY :1;
622 unsigned FLIP :1;
623 unsigned MASH :2;
624 unsigned :13;
625 unsigned PASSWD :8;
626 }cm_pwmctl_bits;
627 #define CM_PWMCTLbits (* (volatile cm_pwmctl_bits *) (cm_pwm + 40))
628 #define CM_PWMCTL (* (volatile unsigned int*) (cm_pwm + 40))
629
630 typedef struct
631 {
632 unsigned DIVF :12;
633 unsigned DIVI :12;
634 unsigned PASSWD :8;
635 } cm_pwmdivbits;
636 #define CM_PWMDIVbits (* (volatile cm_pwmdivbits *) (cm_pwm + 41))
637 #define CM_PWMDIV (*(volatile unsigned int *)(cm_pwm + 41))
638
639 /////////////////////////////////////////////////////////////////////
640 // General Functions
641 /////////////////////////////////////////////////////////////////////
642
643 // TODO: return error code instead of printing (mem_fd, reg_map)
644 void pioInit() {
645 int mem_fd;
646 void *reg_map;
647
648 // /dev/mem is a psuedo-driver for accessing memory in the Linux filesystem
649 if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) {
650 printf("can't open /dev/mem \n");
651 exit(-1);
652 }
653
654 reg_map = mmap(
655 NULL, //Address at which to start local mapping (null means don't-care)
656 BLOCK_SIZE, //Size of mapped memory block
657 PROT_READ|PROT_WRITE,// Enable both reading and writing to the mapped memory
658 MAP_SHARED, // This program does not have exclusive access to this memory
659 mem_fd, // Map to /dev/mem
660 GPIO_BASE); // Offset to GPIO peripheral
661
662 if (reg_map == MAP_FAILED) {
663 printf("gpio mmap error %d\n", (int)reg_map);
664 close(mem_fd);
665 exit(-1);
666 }
667
668 gpio = (volatile unsigned *)reg_map;
669
670 reg_map = mmap(
671 NULL, //Address at which to start local mapping (null means don't-care)
672 BLOCK_SIZE, //Size of mapped memory block
673 PROT_READ|PROT_WRITE,// Enable both reading and writing to the mapped memory
674 MAP_SHARED, // This program does not have exclusive access to this memory
675 mem_fd, // Map to /dev/mem
676 SPI0_BASE); // Offset to SPI peripheral
677
678 if (reg_map == MAP_FAILED) {
679 printf("spi mmap error %d\n", (int)reg_map);
680 close(mem_fd);
681 exit(-1);
682 }
683
684 spi = (volatile unsigned *)reg_map;
685
686 reg_map = mmap(
687 NULL, //Address at which to start local mapping (null means don't-care)
688 BLOCK_SIZE, //Size of mapped memory block
689 PROT_READ|PROT_WRITE,// Enable both reading and writing to the mapped memory
690 MAP_SHARED, // This program does not have exclusive access to this memory
691 mem_fd, // Map to /dev/mem
692 PWM_BASE); // Offset to PWM peripheral
693
694 if (reg_map == MAP_FAILED) {
695 printf("pwm mmap error %d\n", (int)reg_map);
696 close(mem_fd);
697 exit(-1);
698 }
699
700 pwm = (volatile unsigned *)reg_map;
701
702 reg_map = mmap(
703 NULL, //Address at which to start local mapping (null means don't-care)
704 BLOCK_SIZE, //Size of mapped memory block
705 PROT_READ|PROT_WRITE,// Enable both reading and writing to the mapped memory
706 MAP_SHARED, // This program does not have exclusive access to this memory
707 mem_fd, // Map to /dev/mem
708 SYS_TIMER_BASE); // Offset to Timer peripheral
709
710 if (reg_map == MAP_FAILED) {
711 printf("sys timer mmap error %d\n", (int)reg_map);
712 close(mem_fd);
713 exit(-1);
714 }
715
716 sys_timer = (volatile unsigned *)reg_map;
717
718 reg_map = mmap(
719 NULL, //Address at which to start local mapping (null means don't-care)
720 BLOCK_SIZE, //Size of mapped memory block
721 PROT_READ|PROT_WRITE,// Enable both reading and writing to the mapped memory
722 MAP_SHARED, // This program does not have exclusive access to this memory
723 mem_fd, // Map to /dev/mem
724 ARM_TIMER_BASE); // Offset to interrupts
725
726
727 if (reg_map == MAP_FAILED) {
728 printf("arm timer mmap error %d\n", (int)reg_map);
729 close(mem_fd);
730 exit(-1);
731 }
732
733 arm_timer = (volatile unsigned *)reg_map;
734
735 reg_map = mmap(
736 NULL, //Address at which to start local mapping (null means don't-care)
737 BLOCK_SIZE, //Size of mapped memory block
738 PROT_READ|PROT_WRITE,// Enable both reading and writing to the mapped memory
739 MAP_SHARED, // This program does not have exclusive access to this memory
740 mem_fd, // Map to /dev/mem
741 UART_BASE); // Offset to UART peripheral
742
743 if (reg_map == MAP_FAILED) {
744 printf("uart mmap error %d\n", (int)reg_map);
745 close(mem_fd);
746 exit(-1);
747 }
748
749 uart = (volatile unsigned *)reg_map;
750
751 reg_map = mmap(
752 NULL, //Address at which to start local mapping (null means don't-care)
753 BLOCK_SIZE, //Size of mapped memory block
754 PROT_READ|PROT_WRITE,// Enable both reading and writing to the mapped memory
755 MAP_SHARED, // This program does not have exclusive access to this memory
756 mem_fd, // Map to /dev/mem
757 CM_PWM_BASE); // Offset to ARM timer peripheral
758
759 if (reg_map == MAP_FAILED) {
760 printf("cm_pwm mmap error %d\n", (int)reg_map);
761 close(mem_fd);
762 exit(-1);
763 }
764
765 cm_pwm = (volatile unsigned *)reg_map;
766 close(mem_fd);
767 }
768
769 /////////////////////////////////////////////////////////////////////
770 // Interrupt Functions
771 /////////////////////////////////////////////////////////////////////
772
773 int irq1, irq2, irqbasic;
774
775 void noInterrupts(void) {
776 //save current interrupts
777 irq1 = IRQ_ENABLE1;
778 irq2 = IRQ_ENABLE2;
779 irqbasic = IRQ_ENABLE_BASIC;
780
781 //disable interrupts
782 IRQ_DISABLE1 = irq1;
783 IRQ_DISABLE2 = irq2;
784 IRQ_DISABLE_BASIC = irqbasic;
785 }
786
787 void interrupts(void) {
788 if(IRQ_ENABLE1 == 0){ // if interrupts are disabled
789 //restore interrupts
790 IRQ_ENABLE1 = irq1;
791 IRQ_ENABLE2 = irq2;
792 IRQ_ENABLE_BASIC = irqbasic;
793 }
794 }
795
796 /////////////////////////////////////////////////////////////////////
797 // GPIO Functions
798 /////////////////////////////////////////////////////////////////////
799
800 void pinMode(int pin, int function) {
801 int reg = pin/10;
802 int offset = (pin%10)*3;
803 GPFSEL[reg] &= ~((0b111 & ~function) << offset);
804 GPFSEL[reg] |= ((0b111 & function) << offset);
805 }
806
807 void digitalWrite(int pin, int val) {
808 int reg = pin / 32;
809 int offset = pin % 32;
810
811 if (val) GPSET[reg] = 1 << offset;
812 else GPCLR[reg] = 1 << offset;
813 }
814
815 int digitalRead(int pin) {
816 int reg = pin / 32;
817 int offset = pin % 32;
818
819 return (GPLEV[reg] >> offset) & 0x00000001;
820 }
821
822 void pinsMode(int pins[], int numPins, int fxn) {
823 int i;
824 for(i=0; i<numPins; ++i) {
825 pinMode(pins[i], fxn);
826 }
827 }
828
829 void digitalWrites(int pins[], int numPins, int val) {
830 int i;
831 for(i=0; i<numPins; i++) {
832 digitalWrite(pins[i], (val & 0x00000001));
833 val = val >> 1;
834 }
835 }
836
837 int digitalReads(int pins[], int numPins) {
838 int i, val = digitalRead(pins[0]);
839
840 for(i=1; i<numPins; i++) {
841 val |= (digitalRead(pins[i]) << i);
842 }
843 return val;
844 }
845
846 /////////////////////////////////////////////////////////////////////
847 // Timer Functions
848 /////////////////////////////////////////////////////////////////////
849
850 // RPi timer peripheral clock is 1MHz.
851 // M0 and M3 are used by the GPU, so we must use M1 or M2
852
853 void delayMicros(int micros) {
854 SYS_TIMER_C1 = SYS_TIMER_CLO + micros; // set the compare register
855 // 1000 clocks per millisecond
856 SYS_TIMER_CSbits.M1 = 1; // reset match flag to 0
857 while(SYS_TIMER_CSbits.M1 == 0); // wait until the match flag is set
858 }
859
860 void delayMillis(int millis) {
861 delayMicros(millis*1000); // 1000 microseconds per millisecond
862 }
863
864 /////////////////////////////////////////////////////////////////////
865 // SPI Functions
866 /////////////////////////////////////////////////////////////////////
867
868 void spiInit(int freq, int settings) {
869 //set GPIO 8 (CE), 9 (MISO), 10 (MOSI), 11 (SCLK) alt fxn 0 (SPI0)
870 pinMode(8, ALT0);
871 pinMode(9, ALT0);
872 pinMode(10, ALT0);
873 pinMode(11, ALT0);
874
875 //Note: clock divisor will be rounded to the nearest power of 2
876 SPI0CLK = 250000000/freq; // set SPI clock to 250MHz / freq
877 SPI0CS = settings;
878 SPI0CSbits.TA = 1; // turn SPI on with the "transfer active" bit
879 }
880
881 char spiSendReceive(char send){
882 SPI0FIFO = send; // send data to slave
883 while(!SPI0CSbits.DONE); // wait until SPI transmission complete
884 return SPI0FIFO; // return received data
885 }
886
887 short spiSendReceive16(short send) {
888 short rec;
889 SPI0CSbits.TA = 1; // turn SPI on with the "transfer active" bit
890 rec = spiSendReceive((send & 0xFF00) >> 8); // send data MSB first
891 rec = (rec << 8) | spiSendReceive(send & 0xFF);
892 SPI0CSbits.TA = 0; // turn off SPI
893 return rec;
894 }
895
896 /////////////////////////////////////////////////////////////////////
897 // UART Functions
898 /////////////////////////////////////////////////////////////////////
899
900 void uartInit(int baud) {
901 uint fb = 12000000/baud; // 3 MHz UART clock
902
903 pinMode(14, ALT0);
904 pinMode(15, ALT0);
905 UART_IBRD = fb >> 6; // 6 Fract, 16 Int bits of BRD
906 UART_FBRD = fb & 63;
907 UART_LCRHbits.WLEN = 3; // 8 Data, 1 Stop, 0 Parity, no FIFO, no Flow
908 UART_CRbits.UARTEN = 1; // Enable uart.
909 }
910
911 char getCharSerial(void) {
912 while (UART_FRbits.RXFE); // Wait until data is available.
913 return UART_DRbits.DATA; // Return char from serial port.
914 }
915
916
917 void putCharSerial(char c) {
918 while (!UART_FRbits.TXFE);
919 UART_DRbits.DATA = c;
920 }
921
922 /////////////////////////////////////////////////////////////////////
923 // Pulse Width Modulation Functions
924 /////////////////////////////////////////////////////////////////////
925
926 void pwmInit() {
927 pinMode(18, ALT5);
928
929 // Configure the clock manager to generate a 25 MHz PWM clock.
930 // Documentation on the clock manager is missing in the datasheet
931 // but found in "BCM2835 Audio and PWM Clocks" by G.J. van Loo 6 Feb 2013.
932 // Maximum operating frequency of PWM clock is 25 MHz.
933 // Writes to the clock manager registers require simultaneous writing
934 // a "password" of 5A to the top bits to reduce the risk of accidental writes.
935
936 CM_PWMCTL = 0; // Turn off PWM before changing
937 CM_PWMCTL = PWM_CLK_PASSWORD|0x20; // Turn off clock generator
938 while(CM_PWMCTLbits.BUSY); // Wait for generator to stop
939 CM_PWMCTL = PWM_CLK_PASSWORD|0x206; // Src = unfiltered 500 MHz CLKD
940 CM_PWMDIV = PWM_CLK_PASSWORD|(PLL_CLOCK_DIVISOR << 12); // PWM Freq = 25 MHz
941 CM_PWMCTL = CM_PWMCTL|PWM_CLK_PASSWORD|0x10; // Enable PWM clock
942 while (!CM_PWMCTLbits.BUSY); // Wait for generator to start
943 PWM_CTLbits.MSEN1 = 1; // Channel 1 in mark/space mode
944 PWM_CTLbits.PWEN1 = 1; // Enable pwm
945 }
946
947 /**
948 * dut is a value between 0 and 1
949 * freq is pwm frequency in Hz
950 */
951 void setPWM(float freq, float dut) {
952 PWM_RNG1 = (int)(CM_FREQUENCY / freq);
953 PWM_DAT1 = (int)(dut * (CM_FREQUENCY / freq));
954 }
955
956 void analogWrite(int val) {
957 setPWM(78125, val/255.0);
958 }
959
960 #endif
961
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